diff --git a/xc7/counter_test/Makefile b/xc7/counter_test/Makefile
index 6233086..6a8aa87 100644
--- a/xc7/counter_test/Makefile
+++ b/xc7/counter_test/Makefile
@@ -15,6 +15,11 @@ else ifeq ($(TARGET),arty_100)
   XDC:=${current_dir}/arty.xdc
   DEVICE:= xc7a100t_test
   BOARD_BUILDDIR := ${BUILDDIR}/arty_100
+else ifeq ($(TARGET),nexys4ddr)
+  PARTNAME:= xc7a100tcsg324-1
+  XDC:=${current_dir}/nexys4ddr.xdc
+  DEVICE:= xc7a100t_test
+  BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
 else ifeq ($(TARGET),zybo)
   PARTNAME:= xc7z010clg400-1
   XDC:=${current_dir}/zybo.xdc
diff --git a/xc7/counter_test/nexys4ddr.xdc b/xc7/counter_test/nexys4ddr.xdc
new file mode 100644
index 0000000..76c599e
--- /dev/null
+++ b/xc7/counter_test/nexys4ddr.xdc
@@ -0,0 +1,16 @@
+# Clock pin
+set_property PACKAGE_PIN E3 [get_ports {clk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
+
+# LEDs
+set_property PACKAGE_PIN H17  [get_ports {led[0]}]
+set_property PACKAGE_PIN K15  [get_ports {led[1]}]
+set_property PACKAGE_PIN J13  [get_ports {led[2]}]
+set_property PACKAGE_PIN N14  [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+
+# Clock constraints
+create_clock -period 10.0 [get_ports {clk}]
\ No newline at end of file