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f4pga-examples
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added support for Nexys4DDR board in counter_test 

Signed-off-by: Chandler Jearls <cjearls@vt.edu>
This commit is contained in:
Chandler Jearls 2021-04-21 16:34:26 +00:00
parent 9a114c44c0
commit 1e92d9c288
2 changed files with 21 additions and 0 deletions
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5
xc7/counter_test/Makefile
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@ -15,6 +15,11 @@ else ifeq ($(TARGET),arty_100)
XDC:=${current_dir}/arty.xdc XDC:=${current_dir}/arty.xdc
DEVICE:= xc7a100t_test DEVICE:= xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/arty_100 BOARD_BUILDDIR := ${BUILDDIR}/arty_100
else ifeq ($(TARGET),nexys4ddr)
PARTNAME:= xc7a100tcsg324-1
XDC:=${current_dir}/nexys4ddr.xdc
DEVICE:= xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
else ifeq ($(TARGET),zybo) else ifeq ($(TARGET),zybo)
PARTNAME:= xc7z010clg400-1 PARTNAME:= xc7z010clg400-1
XDC:=${current_dir}/zybo.xdc XDC:=${current_dir}/zybo.xdc

16
xc7/counter_test/nexys4ddr.xdc Normal file
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@ -0,0 +1,16 @@
# Clock pin
set_property PACKAGE_PIN E3 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
# LEDs
set_property PACKAGE_PIN H17 [get_ports {led[0]}]
set_property PACKAGE_PIN K15 [get_ports {led[1]}]
set_property PACKAGE_PIN J13 [get_ports {led[2]}]
set_property PACKAGE_PIN N14 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
# Clock constraints
create_clock -period 10.0 [get_ports {clk}]