diff --git a/.github/workflows/sphinx-tuttest.yml b/.github/workflows/sphinx-tuttest.yml index 6128988..759ebd2 100644 --- a/.github/workflows/sphinx-tuttest.yml +++ b/.github/workflows/sphinx-tuttest.yml @@ -57,6 +57,15 @@ jobs: - {fpga-fam: "xc7", os: "debian", os-version: "buster", example: "litex_linux"} - {fpga-fam: "xc7", os: "debian", os-version: "bullseye", example: "litex_linux"} - {fpga-fam: "xc7", os: "debian", os-version: "sid", example: "litex_linux"} + + - {fpga-fam: "xc7", os: "ubuntu", os-version: "xenial", example: "button_controller"} + - {fpga-fam: "xc7", os: "ubuntu", os-version: "bionic", example: "button_controller"} + - {fpga-fam: "xc7", os: "ubuntu", os-version: "focal", example: "button_controller"} + - {fpga-fam: "xc7", os: "centos", os-version: "7", example: "button_controller"} + - {fpga-fam: "xc7", os: "centos", os-version: "8", example: "button_controller"} + - {fpga-fam: "xc7", os: "debian", os-version: "buster", example: "button_controller"} + - {fpga-fam: "xc7", os: "debian", os-version: "bullseye", example: "button_controller"} + - {fpga-fam: "xc7", os: "debian", os-version: "sid", example: "button_controller"} env: LANG: "en_US.UTF-8" diff --git a/xc7/additional_examples/button_controller/button.sv b/xc7/additional_examples/button_controller/button.sv deleted file mode 100644 index 3e29d8f..0000000 --- a/xc7/additional_examples/button_controller/button.sv +++ /dev/null @@ -1,63 +0,0 @@ -`timescale 1ns / 1ps -`default_nettype none - -module debounce( - input wire logic clk, reset, noisy, - output logic debounced - ); - - logic timerDone, clrTimer; - - typedef enum logic[1:0] {s0, s1, s2, s3, ERR='X} stateType; - stateType ns, cs; - - logic[18:0] tA; - - timer_par #(500000, 19) T0(clk, clrTimer, 1'b1, timerDone, tA); - - always_comb - begin - ns = ERR; - clrTimer = 0; - debounced = 0; - - if (reset) - ns = s0; - else - case (cs) - s0: begin - clrTimer = 1'b1; - if (noisy) - ns = s1; - else - ns = s0; - end - s1: if (noisy && timerDone) - ns = s2; - else if (noisy && ~timerDone) - ns = s1; - else - ns = s0; - s2: begin - debounced = 1'b1; - clrTimer = 1'b1; - if (noisy) - ns = s2; - else - ns = s3; - end - s3: begin - debounced = 1'b1; - if (~noisy && timerDone) - ns = s0; - else if (~noisy && ~timerDone) - ns = s3; - else - ns = s2; - end - endcase - end - - always_ff @(posedge clk) - cs <= ns; -endmodule diff --git a/xc7/additional_examples/button_controller/button_controller.sv b/xc7/additional_examples/button_controller/button_controller.sv new file mode 100644 index 0000000..e36f7bf --- /dev/null +++ b/xc7/additional_examples/button_controller/button_controller.sv @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps `default_nettype none + +module top ( + input wire logic clk, + btnu, + btnc, + output logic [3:0] anode, + output logic [7:0] segment +); + + + logic sync; + logic syncToDebounce; + logic debounceToOneShot; + logic f1, f2; + logic f3, f4; + logic oneShotToCounter; + logic [7:0] counterToSevenSegment; + logic [7:0] counterToSevenSegment2; + logic oneShotToCounter2; + logic s0, s1; + debounce d0 ( + .clk(clk), + .reset(btnu), + .noisy(syncToDebounce), + .debounced(debounceToOneShot) + ); + + assign oneShotToCounter = f1 && ~f2; + + assign oneShotToCounter2 = f3 && ~f4; + + timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T0 ( + .clk(clk), + .reset(btnu), + .increment(oneShotToCounter), + .rolling_over(s0), + .count(counterToSevenSegment) + ); + + timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T1 ( + .clk(clk), + .reset(btnu), + .increment(oneShotToCounter2), + .rolling_over(s1), + .count(counterToSevenSegment2) + ); + + + display_control DC0 ( + .clk(clk), + .reset(btnu), + .dataIn({counterToSevenSegment2, counterToSevenSegment}), + .digitDisplay(4'b1111), + .digitPoint(4'b0000), + .anode(anode), + .segment(segment) + ); + + always_ff @(posedge clk) begin + + sync <= btnc; + syncToDebounce <= sync; + + f1 <= debounceToOneShot; + f2 <= f1; + + f3 <= syncToDebounce; + f4 <= f3; + end +endmodule diff --git a/xc7/additional_examples/button_controller/button_top.sv b/xc7/additional_examples/button_controller/button_top.sv deleted file mode 100644 index 83374a0..0000000 --- a/xc7/additional_examples/button_controller/button_top.sv +++ /dev/null @@ -1,47 +0,0 @@ -`timescale 1ns / 1ps -`default_nettype none - -module top( - input wire logic clk, btnu, btnc, - output logic[3:0] anode, - output logic[7:0] segment - ); - - - logic sync; - logic syncToDebounce; - logic debounceToOneShot; - logic f1, f2; - logic f3, f4; - logic oneShotToCounter; - logic[7:0] counterToSevenSegment; - logic[7:0] counterToSevenSegment2; - logic oneShotToCounter2; - logic s0, s1; - debounce d0(clk, btnu, syncToDebounce, debounceToOneShot); - - assign oneShotToCounter = f1 && ~f2; - - assign oneShotToCounter2 = f3 && ~f4; - - - timer_par #(256, 8) T0(clk, btnu, oneShotToCounter, s0, counterToSevenSegment); - - timer_par #(256, 8) T1(clk, btnu, oneShotToCounter2, s1, counterToSevenSegment2); - - - SevenSegmentControl SSC0 (clk, btnu, {counterToSevenSegment2, counterToSevenSegment}, 4'b1111, 4'b0000, anode, segment); - - always_ff @(posedge clk) - begin - - sync <= btnc; - syncToDebounce <= sync; - - f1 <= debounceToOneShot; - f2 <= f1; - - f3 <= syncToDebounce; - f4 <= f3; - end -endmodule diff --git a/xc7/additional_examples/button_controller/debounce.sv b/xc7/additional_examples/button_controller/debounce.sv new file mode 100644 index 0000000..1254d80 --- /dev/null +++ b/xc7/additional_examples/button_controller/debounce.sv @@ -0,0 +1,64 @@ +`timescale 1ns / 1ps `default_nettype none + +module debounce ( + input wire logic clk, + reset, + noisy, + output logic debounced +); + + logic timerDone, clrTimer; + + typedef enum logic [1:0] { + s0, + s1, + s2, + s3, + ERR = 'X + } state_type_e; + state_type_e ns, cs; + + logic [18:0] tA; + + timer #(.MOD_VALUE(500000), .BIT_WIDTH(19)) T0 ( + .clk(clk), + .reset(clrTimer), + .increment(1'b1), + .rolling_over(timerDone), + .count(tA) + ); + + always_comb begin + ns = ERR; + clrTimer = 0; + debounced = 0; + + if (reset) ns = s0; + else + case (cs) + s0: begin + clrTimer = 1'b1; + if (noisy) ns = s1; + else ns = s0; + end + s1: + if (noisy && timerDone) ns = s2; + else if (noisy && ~timerDone) ns = s1; + else ns = s0; + s2: begin + debounced = 1'b1; + clrTimer = 1'b1; + if (noisy) ns = s2; + else ns = s3; + end + s3: begin + debounced = 1'b1; + if (~noisy && timerDone) ns = s0; + else if (~noisy && ~timerDone) ns = s3; + else ns = s2; + end + endcase + end + + always_ff @(posedge clk) cs <= ns; +endmodule diff --git a/xc7/additional_examples/button_controller/SSControl.sv b/xc7/additional_examples/button_controller/display_control.sv similarity index 58% rename from xc7/additional_examples/button_controller/SSControl.sv rename to xc7/additional_examples/button_controller/display_control.sv index 8aa8378..1f71c59 100644 --- a/xc7/additional_examples/button_controller/SSControl.sv +++ b/xc7/additional_examples/button_controller/display_control.sv @@ -1,53 +1,51 @@ `default_nettype none -module SevenSegmentControl( - input wire logic clk, - input wire logic reset, - input wire logic [15:0] dataIn, - input wire logic [3:0] digitDisplay, - input wire logic [3:0] digitPoint, - output logic [3:0] anode, - output logic [7:0] segment - ); +module display_control ( + input wire logic clk, + input wire logic reset, + input wire logic [15:0] dataIn, + input wire logic [ 3:0] digitDisplay, + input wire logic [ 3:0] digitPoint, + output logic [ 3:0] anode, + output logic [ 7:0] segment +); - parameter integer COUNT_BITS = 17; - - logic [COUNT_BITS-1:0] count_val; - logic [1:0] anode_select; - logic [3:0] cur_anode; - logic [3:0] cur_data_in; - - always_ff @(posedge clk) begin - if (reset) - count_val <= 0; - else - count_val <= count_val + 1; - end + parameter integer COUNT_BITS = 17; - assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + logic [COUNT_BITS-1:0] count_val; + logic [ 1:0] anode_select; + logic [ 3:0] cur_anode; + logic [ 3:0] cur_data_in; - assign cur_anode = + always_ff @(posedge clk) begin + if (reset) count_val <= 0; + else count_val <= count_val + 1; + end + + assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + + assign cur_anode = (anode_select == 2'b00) ? 4'b1110 : (anode_select == 2'b01) ? 4'b1101 : (anode_select == 2'b10) ? 4'b1011 : 4'b0111; - - assign anode = cur_anode | (~digitDisplay); - - assign cur_data_in = + + assign anode = cur_anode | (~digitDisplay); + + assign cur_data_in = (anode_select == 2'b00) ? dataIn[3:0] : (anode_select == 2'b01) ? dataIn[7:4] : (anode_select == 2'b10) ? dataIn[11:8] : dataIn[15:12] ; - - assign segment[7] = + + assign segment[7] = (anode_select == 2'b00) ? ~digitPoint[0] : (anode_select == 2'b01) ? ~digitPoint[1] : (anode_select == 2'b10) ? ~digitPoint[2] : ~digitPoint[3] ; - assign segment[6:0] = + assign segment[6:0] = (cur_data_in == 0) ? 7'b1000000 : (cur_data_in == 1) ? 7'b1111001 : (cur_data_in == 2) ? 7'b0100100 : @@ -65,5 +63,5 @@ module SevenSegmentControl( (cur_data_in == 14) ? 7'b0000110 : 7'b0001110; - -endmodule \ No newline at end of file + +endmodule diff --git a/xc7/additional_examples/button_controller/timer.sv b/xc7/additional_examples/button_controller/timer.sv new file mode 100644 index 0000000..183326c --- /dev/null +++ b/xc7/additional_examples/button_controller/timer.sv @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps `default_nettype none + +module timer #( + parameter MOD_VALUE = 1, + parameter BIT_WIDTH = 1 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [BIT_WIDTH-1:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 0; + else if (increment) begin + if (rolling_over) count <= 0; + else count <= count + 1'b1; + end + + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule diff --git a/xc7/additional_examples/button_controller/timer_par.sv b/xc7/additional_examples/button_controller/timer_par.sv deleted file mode 100644 index 5737730..0000000 --- a/xc7/additional_examples/button_controller/timer_par.sv +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1ns / 1ps -`default_nettype none - -module timer_par #(parameter MOD_VALUE=1, parameter BIT_WIDTH = 1) ( - input wire logic clk, reset, increment, - output logic rolling_over, - output logic[BIT_WIDTH-1:0] count = 0 - ); - - always_ff @(posedge clk) - begin - if(reset) - count <= 0; - else if(increment) - begin - if(rolling_over) - count <= 0; - else - count <= count + 1'b1; - end - - end - - always_comb - begin - if(increment && (count==MOD_VALUE-1)) - rolling_over = 1'b1; - else - rolling_over = 1'b0; - end - -endmodule \ No newline at end of file