Allow to use Surelog to build examples

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

.github/workflows/sphinx-tuttest.yml

@@ -37,6 +37,61 @@ jobs:
       LANG: "en_US.UTF-8"
       DEBIAN_FRONTEND: "noninteractive"
       GHA_PREEMPTIBLE: "false"
+      SURELOG_CMD: ""
+
+    container: ${{matrix.os}}:${{matrix.os-version}}
+
+    steps:
+
+      - name: Setup repository
+        uses: actions/checkout@v2
+        with:
+          submodules: recursive
+
+      - name: Install utils
+        if: ${{matrix.os == 'ubuntu' || matrix.os == 'debian'}}
+        run: apt -qqy update && apt -qqy install wget locales && locale-gen $LANG
+
+      - name: Install utils
+        if: ${{matrix.os == 'centos'}}
+        run: yum -y install wget
+
+      - name: Install utils
+        if: ${{matrix.os == 'fedora'}}
+        run: dnf install -y wget
+
+      - name: Install tuttest
+        run: |
+          wget https://github.com/antmicro/tuttest/releases/download/v0.2-beta/tuttest -O /usr/bin/tuttest
+          chmod a+rx /usr/bin/tuttest
+
+      - name: Install SymbiFlow toolchain
+        run: bash .github/scripts/install-toolchain.sh ${{matrix.fpga-fam}} ${{matrix.os}}
+
+      - name: Build examples
+        run: bash .github/scripts/build-examples.sh ${{matrix.fpga-fam}} ${{matrix.example}}
+
+      - uses: actions/upload-artifact@v2
+        with:
+          name: symbiflow-examples-bitstreams
+          path: |
+            **/*.bit
+            **/plot_*.svg
+
+  Test-Surelog:
+    needs: Matrix
+    strategy:
+      fail-fast: false
+      matrix:
+        include: ${{ fromJson(needs.Matrix.outputs.matrix) }}
+    runs-on: ${{ matrix.runs-on }}
+    name: Surelog frontend - ${{ matrix.fpga-fam }} | ${{ matrix.os }} ${{ matrix.os-version }} | ${{ matrix.example }}
+
+    env:
+      LANG: "en_US.UTF-8"
+      DEBIAN_FRONTEND: "noninteractive"
+      GHA_PREEMPTIBLE: "false"
+      SURELOG_CMD: "-parse -DSYNTHESIS"
 
     container: ${{matrix.os}}:${{matrix.os-version}}
 

common/common.mk

@@ -44,6 +44,11 @@ ifneq (${PCF},)
   PCF_CMD := -p ${PCF}
 endif
 
+# Determine if we should use Surelog/UHDM to read sources
+ifneq (${SURELOG_CMD},)
+  SURELOG_OPT := -s ${SURELOG_CMD}
+endif
+
 .DELETE_ON_ERROR:
 
 # Build design
@@ -53,7 +58,7 @@ ${BOARD_BUILDDIR}:
 	mkdir -p ${BOARD_BUILDDIR}
 
 ${BOARD_BUILDDIR}/${TOP}.eblif: ${SOURCES} ${XDC} ${SDC} ${PCF} | ${BOARD_BUILDDIR}
-	cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${SOURCES} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} ${XDC_CMD} 2>&1 > /dev/null
+	cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} ${SURELOG_OPT} -v ${SOURCES} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} ${XDC_CMD}
 
 ${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
 	cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} ${SDC_CMD} 2>&1 > /dev/null

symbiflow_synth

@@ -0,0 +1,130 @@
+#!/bin/bash
+set -e
+
+MYPATH=`realpath $0`
+MYPATH=`dirname ${MYPATH}`
+
+export SHARE_DIR_PATH=`realpath ${MYPATH}/../share/symbiflow`
+export TECHMAP_PATH=${SHARE_DIR_PATH}/techmaps/xc7_vpr/techmap
+
+
+export UTILS_PATH=${SHARE_DIR_PATH}/scripts
+SYNTH_TCL_PATH=${UTILS_PATH}/xc7/synth.tcl
+CONV_TCL_PATH=${UTILS_PATH}/xc7/conv.tcl
+SPLIT_INOUTS=${UTILS_PATH}/split_inouts.py
+
+VERILOG_FILES=()
+XDC_FILES=()
+TOP=top
+DEVICE="*"
+PART=""
+SURELOG_CMD=()
+
+VERILOGLIST=0
+XDCLIST=0
+TOPNAME=0
+DEVICENAME=0
+PARTNAME=0
+SURELOG=0
+
+for arg in $@; do
+	echo $arg
+	case "$arg" in
+		-t|--top)
+			echo "adding top"
+			VERILOGLIST=0
+			XDCLIST=0
+			TOPNAME=1
+			DEVICENAME=0
+			PARTNAME=0
+			SURELOG=0
+			;;
+		-x|--xdc)
+			VERILOGLIST=0
+			XDCLIST=1
+			TOPNAME=0
+			DEVICENAME=0
+			PARTNAME=0
+			SURELOG=0
+			;;
+		-v|--verilog)
+			VERILOGLIST=1
+			XDCLIST=0
+			TOPNAME=0
+			DEVICENAME=0
+			PARTNAME=0
+			SURELOG=0
+			;;
+		-d|--device)
+			VERILOGLIST=0
+			XDCLIST=0
+			TOPNAME=0
+			DEVICENAME=1
+			PARTNAME=0
+			SURELOG=0
+			;;
+		-p|--part)
+			VERILOGLIST=0
+			XDCLIST=0
+			TOPNAME=0
+			DEVICENAME=0
+			PARTNAME=1
+			SURELOG=0
+			;;
+		-s|--surelog)
+                        VERILOGLIST=0
+                        XDCLIST=0
+                        TOPNAME=0
+                        DEVICENAME=0
+                        PARTNAME=0
+			SURELOG=1
+                       ;;
+		*)
+			if [ $VERILOGLIST -eq 1 ]; then
+				VERILOG_FILES+=($arg)
+			elif [ $XDCLIST -eq 1 ]; then
+				XDC_FILES+=($arg)
+			elif [ $TOPNAME -eq 1 ]; then
+				TOP=$arg
+			elif [ $DEVICENAME -eq 1 ]; then
+				DEVICE=$arg
+			elif [ $PARTNAME -eq 1 ]; then
+				PART=$arg
+                        elif [ $SURELOG -eq 1 ]; then
+                                SURELOG_CMD+=($arg)
+			else
+				echo "Usage: synth [-t|--top <top module name> -v|--verilog <Verilog files list> [-x|--xdc <XDC files list>]"
+				echo "             [-d|--device <device type (e.g. artix7)>] [-p|--part <part name>]"
+				echo "note: device and part parameters are required if xdc is passed"
+				exit 1
+			fi
+			;;
+	esac
+done
+
+if [ ${#VERILOG_FILES[@]} -eq 0 ]; then
+	echo "Please provide at least one Verilog file"
+	exit 1
+fi
+
+DATABASE_DIR=${DATABASE_DIR:=$(prjxray-config)}
+
+export TOP=${TOP}
+export USE_ROI="FALSE"
+export INPUT_XDC_FILES=${XDC_FILES[*]}
+export OUT_JSON=$TOP.json
+export OUT_SDC=${TOP}.sdc
+export SYNTH_JSON=${TOP}_io.json
+export OUT_SYNTH_V=${TOP}_synth.v
+export OUT_EBLIF=${TOP}.eblif
+export PART_JSON=`realpath ${DATABASE_DIR}/$DEVICE/$PART/part.json`
+export OUT_FASM_EXTRA=${TOP}_fasm_extra.fasm
+export PYTHON3=${PYTHON3:=$(which python3)}
+LOG=${TOP}_synth.log
+if [ -z "$SURELOG_CMD" ]; then
+yosys -p "tcl ${SYNTH_TCL_PATH}" -l $LOG ${VERILOG_FILES[*]}
+else
+yosys -p "plugin -i uhdm" -p "read_verilog_with_uhdm ${SURELOG_CMD[*]} ${VERILOG_FILES[*]}" -p "tcl ${SYNTH_TCL_PATH}" -l $LOG
+fi
+python3 ${SPLIT_INOUTS} -i ${OUT_JSON} -o ${SYNTH_JSON}
+yosys -p "read_json $SYNTH_JSON; tcl ${CONV_TCL_PATH}"

xc7/environment.yml

@@ -7,8 +7,9 @@ dependencies:
   - litex-hub::gcc-riscv64-elf-newlib=9.2.0=20201119_154229
   - litex-hub::prjxray-db=0.0_257_g0a0adde=20220114_081711
   - litex-hub::vtr-optimized=8.0.0_5105_g116f30cb8=20220114_081711
-  - litex-hub::yosys=0.13_4_g61324cf55=20220114_081711_py37
-  - litex-hub::symbiflow-yosys-plugins=1.0.0_7_599_gdb3a9c7=20220114_081711
+  - litex-hub::yosys
+  - litex-hub::symbiflow-yosys-plugins
+  - litex-hub::surelog
   - make
   - lxml
   - simplejson