diff --git a/xc7/pulse_width_led/Makefile b/xc7/pulse_width_led/Makefile index ba28c76..b3e9b7d 100644 --- a/xc7/pulse_width_led/Makefile +++ b/xc7/pulse_width_led/Makefile @@ -2,7 +2,7 @@ mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) current_dir := $(patsubst %/,%,$(dir $(mkfile_path))) TOP := top VERILOG := ${current_dir}/PWM.v -VERILOG += ${current_dir}/PWM_top.v +VERILOG += ${current_dir}/pulse_led.v DEVICE := xc7a50t_test BITSTREAM_DEVICE := artix7 BUILDDIR := build diff --git a/xc7/pulse_width_led/PWM.v b/xc7/pulse_width_led/PWM.v index f9ff8fd..74f33e1 100644 --- a/xc7/pulse_width_led/PWM.v +++ b/xc7/pulse_width_led/PWM.v @@ -1,17 +1,14 @@ -module PWM( -input wire clk, -input wire [13:0] width, -output reg pulse +module PWM ( + input wire clk, + input wire [13:0] width, + output reg pulse ); -reg[13:0] counter = 0; + reg [13:0] counter = 0; -always @(posedge clk) -begin -counter <= counter + 1; -if(counter < width) -pulse <= 1'b1; -else -pulse <= 1'b0; -end + always @(posedge clk) begin + counter <= counter + 1; + if (counter < width) pulse <= 1'b1; + else pulse <= 1'b0; + end endmodule diff --git a/xc7/pulse_width_led/PWM_top.v b/xc7/pulse_width_led/PWM_top.v deleted file mode 100644 index 78c496e..0000000 --- a/xc7/pulse_width_led/PWM_top.v +++ /dev/null @@ -1,18 +0,0 @@ -module top( -input wire clk, -input wire [3:0] sw, -input wire [3:0] btn, -output wire pulse_red, pulse_blue, pulse_green -); -wire [13:0] pulse_wideR, pulse_wideB, pulse_wideG; - -assign pulse_wideR = {1'b0, sw[3:1], 10'd0}; -assign pulse_wideG = {1'b0, sw[0], btn[3:2], 10'd0}; -assign pulse_wideB = {btn[1:0], 11'd0}; - -PWM R0(.clk(clk), .pulse(pulse_red), .width(pulse_wideR)); -PWM B0(.clk(clk), .pulse(pulse_green), .width(pulse_wideB)); -PWM G0(.clk(clk), .pulse(pulse_blue), .width(pulse_wideG)); - - -endmodule \ No newline at end of file diff --git a/xc7/pulse_width_led/pulse_led.v b/xc7/pulse_width_led/pulse_led.v new file mode 100644 index 0000000..ec8fb37 --- /dev/null +++ b/xc7/pulse_width_led/pulse_led.v @@ -0,0 +1,32 @@ +module top ( + input wire clk, + input wire [3:0] sw, + input wire [3:0] btn, + output wire pulse_red, + pulse_blue, + pulse_green +); + wire [13:0] pulse_wideR, pulse_wideB, pulse_wideG; + + assign pulse_wideR = {1'b0, sw[3:1], 10'd0}; + assign pulse_wideG = {1'b0, sw[0], btn[3:2], 10'd0}; + assign pulse_wideB = {btn[1:0], 11'd0}; + + PWM R0 ( + .clk (clk), + .pulse(pulse_red), + .width(pulse_wideR) + ); + PWM B0 ( + .clk (clk), + .pulse(pulse_green), + .width(pulse_wideB) + ); + PWM G0 ( + .clk (clk), + .pulse(pulse_blue), + .width(pulse_wideG) + ); + + +endmodule diff --git a/xc7/timer/clock.sv b/xc7/timer/clock.sv new file mode 100644 index 0000000..bc14e3a --- /dev/null +++ b/xc7/timer/clock.sv @@ -0,0 +1,31 @@ +`timescale 1ns / 1ps `default_nettype none + +module top ( + input wire logic clk, + btnc, + sw, + output logic [3:0] anode, + output logic [7:0] segment +); + + logic [15:0] digitData; + + timer TC0 ( + clk, + btnc, + sw, + digitData[3:0], + digitData[7:4], + digitData[11:8], + digitData[15:12] + ); + display_control SSC0 ( + clk, + btnc, + digitData, + 4'b1111, + 4'b0100, + anode, + segment + ); +endmodule diff --git a/xc7/timer/SSControl.sv b/xc7/timer/display_control.sv similarity index 58% rename from xc7/timer/SSControl.sv rename to xc7/timer/display_control.sv index b34c26a..ab0d7a5 100644 --- a/xc7/timer/SSControl.sv +++ b/xc7/timer/display_control.sv @@ -1,54 +1,52 @@ `default_nettype none -module SevenSegmentControl( - input wire logic clk, - input wire logic reset, - input wire logic [15:0] dataIn, - input wire logic [3:0] digitDisplay, - input wire logic [3:0] digitPoint, - output logic [3:0] anode, - output logic [7:0] segment - ); +module display_control ( + input wire logic clk, + input wire logic reset, + input wire logic [15:0] dataIn, + input wire logic [ 3:0] digitDisplay, + input wire logic [ 3:0] digitPoint, + output logic [ 3:0] anode, + output logic [ 7:0] segment +); - parameter integer COUNT_BITS = 17; - - logic [COUNT_BITS-1:0] count_val; - logic [1:0] anode_select; - logic [3:0] cur_anode; - logic [3:0] cur_data_in; - - - always_ff @(posedge clk) begin - if (reset) - count_val <= 0; - else - count_val <= count_val + 1; - end + parameter integer COUNT_BITS = 17; - assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + logic [COUNT_BITS-1:0] count_val; + logic [ 1:0] anode_select; + logic [ 3:0] cur_anode; + logic [ 3:0] cur_data_in; - assign cur_anode = + + always_ff @(posedge clk) begin + if (reset) count_val <= 0; + else count_val <= count_val + 1; + end + + assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + + assign cur_anode = (anode_select == 2'b00) ? 4'b1110 : (anode_select == 2'b01) ? 4'b1101 : (anode_select == 2'b10) ? 4'b1011 : 4'b0111; - - assign anode = cur_anode | (~digitDisplay); - - assign cur_data_in = + + assign anode = cur_anode | (~digitDisplay); + + assign cur_data_in = (anode_select == 2'b00) ? dataIn[3:0] : (anode_select == 2'b01) ? dataIn[7:4] : (anode_select == 2'b10) ? dataIn[11:8] : dataIn[15:12] ; - - assign segment[7] = + + assign segment[7] = (anode_select == 2'b00) ? ~digitPoint[0] : (anode_select == 2'b01) ? ~digitPoint[1] : (anode_select == 2'b10) ? ~digitPoint[2] : ~digitPoint[3] ; - assign segment[6:0] = + assign segment[6:0] = (cur_data_in == 0) ? 7'b1000000 : (cur_data_in == 1) ? 7'b1111001 : (cur_data_in == 2) ? 7'b0100100 : @@ -66,5 +64,5 @@ module SevenSegmentControl( (cur_data_in == 14) ? 7'b0000110 : 7'b0001110; - -endmodule \ No newline at end of file + +endmodule diff --git a/xc7/timer/modify_count.sv b/xc7/timer/modify_count.sv index be6dd4b..be7ee3f 100644 --- a/xc7/timer/modify_count.sv +++ b/xc7/timer/modify_count.sv @@ -1,30 +1,26 @@ -`default_nettype none - -module mod_counter #(parameter MOD_VALUE=10) ( - input wire logic clk, reset, increment, - output logic rolling_over, - output logic[3:0] count = 0 - ); - - always_ff @(posedge clk) - begin - if(reset) - count <= 4'b0000; - else if(increment) - begin - if(rolling_over) - count <= 4'b0000; - else - count <= count + 4'b0001; - end - end - - always_comb - begin - if(increment && (count==MOD_VALUE-1)) - rolling_over = 1'b1; - else - rolling_over = 1'b0; - end - -endmodule \ No newline at end of file +`default_nettype none + +module modify_count #( + parameter MOD_VALUE = 10 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [3:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 4'b0000; + else if (increment) begin + if (rolling_over) count <= 4'b0000; + else count <= count + 4'b0001; + end + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule diff --git a/xc7/timer/stwatch.sv b/xc7/timer/stwatch.sv deleted file mode 100644 index 98bbb99..0000000 --- a/xc7/timer/stwatch.sv +++ /dev/null @@ -1,19 +0,0 @@ -`timescale 1ns / 1ps -`default_nettype none - -module stopwatch( - input wire logic clk, reset, run, - output logic[3:0] digit0, digit1, digit2, digit3 - ); - - logic inc0, inc1, inc2, inc3, inc4; - - logic[23:0] timerCount; - - mod_counter #(10) M0(clk, reset, inc0, inc1, digit0); - mod_counter #(10) M1(clk, reset, inc1, inc2, digit1); - mod_counter #(10) M2(clk, reset, inc2, inc3, digit2); - mod_counter #(6) M3(clk, reset, inc3, inc4, digit3); - - timer #(1000000) T0(clk, reset, run, inc0, timerCount); -endmodule diff --git a/xc7/timer/time_counter.sv b/xc7/timer/time_counter.sv new file mode 100644 index 0000000..e6cbc20 --- /dev/null +++ b/xc7/timer/time_counter.sv @@ -0,0 +1,27 @@ +`timescale 1ns / 1ps `default_nettype none + +module time_counter #( + parameter MOD_VALUE = 1000000 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [23:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 0; + else if (increment) begin + if (rolling_over) count <= 0; + else count <= count + 1'b1; + end + + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule diff --git a/xc7/timer/timer.sv b/xc7/timer/timer.sv index 6678527..102a59a 100644 --- a/xc7/timer/timer.sv +++ b/xc7/timer/timer.sv @@ -1,32 +1,53 @@ -`timescale 1ns / 1ps -`default_nettype none +`timescale 1ns / 1ps `default_nettype none -module timer #(parameter MOD_VALUE=1000000) ( - input wire logic clk, reset, increment, - output logic rolling_over, - output logic[23:0] count = 0 - ); - - always_ff @(posedge clk) - begin - if(reset) - count <= 0; - else if(increment) - begin - if(rolling_over) - count <= 0; - else - count <= count + 1'b1; - end - - end - - always_comb - begin - if(increment && (count==MOD_VALUE-1)) - rolling_over = 1'b1; - else - rolling_over = 1'b0; - end - +module timer ( + input wire logic clk, + reset, + run, + output logic [3:0] digit0, + digit1, + digit2, + digit3 +); + + logic inc0, inc1, inc2, inc3, inc4; + + logic [23:0] timerCount; + + modify_count #(10) M0 ( + clk, + reset, + inc0, + inc1, + digit0 + ); + modify_count #(10) M1 ( + clk, + reset, + inc1, + inc2, + digit1 + ); + modify_count #(10) M2 ( + clk, + reset, + inc2, + inc3, + digit2 + ); + modify_count #(6) M3 ( + clk, + reset, + inc3, + inc4, + digit3 + ); + + time_counter #(1000000) T0 ( + clk, + reset, + run, + inc0, + timerCount + ); endmodule diff --git a/xc7/timer/timer_top.sv b/xc7/timer/timer_top.sv deleted file mode 100644 index cac3b2e..0000000 --- a/xc7/timer/timer_top.sv +++ /dev/null @@ -1,14 +0,0 @@ -`timescale 1ns / 1ps -`default_nettype none - -module top( - input wire logic clk, btnc, sw, - output logic[3:0] anode, - output logic[7:0] segment - ); - - logic[15:0] digitData; - - stopwatch SW0(clk, btnc, sw, digitData[3:0], digitData[7:4], digitData[11:8], digitData[15:12]); - SevenSegmentControl SSC0(clk, btnc, digitData, 4'b1111 , 4'b0100 , anode, segment); -endmodule