linux_litex: add XDC constraints
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
2bc7225b06
commit
768520b1b0
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@ -11,6 +11,7 @@ DEVICE := xc7a50t_test
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BITSTREAM_DEVICE := artix7
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PCF := ${current_dir}/arty.pcf
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SDC := ${current_dir}/arty.sdc
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XDC := ${current_dir}/arty.xdc
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BUILDDIR := build
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all: ${BUILDDIR}/${TOP}.bit
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@ -20,7 +21,7 @@ ${BUILDDIR}:
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ln -s ${MEM_INIT} ${BUILDDIR}
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${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
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cd ${BUILDDIR} && synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} 2>&1 > /dev/null
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cd ${BUILDDIR} && synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
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${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
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cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
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@ -0,0 +1,290 @@
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# ### serial:0.tx
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##set_property LOC D10 [get_ports serial_tx]
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set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
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# ### serial:0.rx
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##set_property LOC A9 [get_ports serial_rx]
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set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
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# ### clk100:0
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##set_property LOC E3 [get_ports clk100]
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set_property IOSTANDARD LVCMOS33 [get_ports clk100]
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# ### eth_ref_clk:0
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##set_property LOC G18 [get_ports eth_ref_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
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# ### cpu_reset:0
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##set_property LOC C2 [get_ports cpu_reset]
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set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
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# ### ddram:0.a
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##set_property LOC R2 [get_ports {ddram_a[0]} ]
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set_property SLEW FAST [get_ports {ddram_a[0]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]} ]
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# ### ddram:0.a
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##set_property LOC M6 [get_ports {ddram_a[1]} ]
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set_property SLEW FAST [get_ports {ddram_a[1]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]} ]
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# ### ddram:0.a
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##set_property LOC N4 [get_ports {ddram_a[2]} ]
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set_property SLEW FAST [get_ports {ddram_a[2]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]} ]
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# ### ddram:0.a
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##set_property LOC T1 [get_ports {ddram_a[3]} ]
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set_property SLEW FAST [get_ports {ddram_a[3]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]} ]
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# ### ddram:0.a
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##set_property LOC N6 [get_ports {ddram_a[4]} ]
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set_property SLEW FAST [get_ports {ddram_a[4]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]} ]
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# ### ddram:0.a
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##set_property LOC R7 [get_ports {ddram_a[5]} ]
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set_property SLEW FAST [get_ports {ddram_a[5]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]} ]
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# ### ddram:0.a
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##set_property LOC V6 [get_ports {ddram_a[6]} ]
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set_property SLEW FAST [get_ports {ddram_a[6]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]} ]
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# ### ddram:0.a
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##set_property LOC U7 [get_ports {ddram_a[7]} ]
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set_property SLEW FAST [get_ports {ddram_a[7]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]} ]
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# ### ddram:0.a
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##set_property LOC R8 [get_ports {ddram_a[8]} ]
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set_property SLEW FAST [get_ports {ddram_a[8]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]} ]
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# ### ddram:0.a
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##set_property LOC V7 [get_ports {ddram_a[9]} ]
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set_property SLEW FAST [get_ports {ddram_a[9]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]} ]
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# ### ddram:0.a
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##set_property LOC R6 [get_ports {ddram_a[10]} ]
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set_property SLEW FAST [get_ports {ddram_a[10]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]} ]
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# ### ddram:0.a
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##set_property LOC U6 [get_ports {ddram_a[11]} ]
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set_property SLEW FAST [get_ports {ddram_a[11]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]} ]
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# ### ddram:0.a
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##set_property LOC T6 [get_ports {ddram_a[12]} ]
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set_property SLEW FAST [get_ports {ddram_a[12]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]} ]
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# ### ddram:0.a
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##set_property LOC T8 [get_ports {ddram_a[13]} ]
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set_property SLEW FAST [get_ports {ddram_a[13]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]} ]
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# ### ddram:0.ba
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##set_property LOC R1 [get_ports {ddram_ba[0]} ]
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set_property SLEW FAST [get_ports {ddram_ba[0]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]} ]
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# ### ddram:0.ba
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# ### ddram:0.ba
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##set_property LOC P2 [get_ports {ddram_ba[2]} ]
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set_property SLEW FAST [get_ports {ddram_ba[2]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]} ]
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# ### ddram:0.ras_n
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##set_property LOC P3 [get_ports {ddram_ras_n]
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set_property SLEW FAST [get_ports ddram_ras_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
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# ### ddram:0.cas_n
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##set_property LOC M4 [get_ports {ddram_cas_n]
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set_property SLEW FAST [get_ports ddram_cas_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
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# ### ddram:0.we_n
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##set_property LOC P5 [get_ports {ddram_we_n]
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set_property SLEW FAST [get_ports ddram_we_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
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# ### ddram:0.cs_n
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##set_property LOC U8 [get_ports {ddram_cs_n]
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set_property SLEW FAST [get_ports ddram_cs_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
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# ### ddram:0.dm
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##set_property LOC L1 [get_ports {ddram_dm[0]} ]
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set_property SLEW FAST [get_ports {ddram_dm[0]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]} ]
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# ### ddram:0.dm
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##set_property LOC U1 [get_ports {ddram_dm[1]} ]
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set_property SLEW FAST [get_ports {ddram_dm[1]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]} ]
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# ### ddram:0.dq
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##set_property LOC K5 [get_ports {ddram_dq[0]} ]
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set_property SLEW FAST [get_ports {ddram_dq[0]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]} ]
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# ### ddram:0.dq
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##set_property LOC L3 [get_ports {ddram_dq[1]} ]
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set_property SLEW FAST [get_ports {ddram_dq[1]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]} ]
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# ### ddram:0.dq
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##set_property LOC K3 [get_ports {ddram_dq[2]} ]
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set_property SLEW FAST [get_ports {ddram_dq[2]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]} ]
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# ### ddram:0.dq
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##set_property LOC L6 [get_ports {ddram_dq[3]} ]
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set_property SLEW FAST [get_ports {ddram_dq[3]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]} ]
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# ### ddram:0.dq
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##set_property LOC M3 [get_ports {ddram_dq[4]} ]
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set_property SLEW FAST [get_ports {ddram_dq[4]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]} ]
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# ### ddram:0.dq
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##set_property LOC M1 [get_ports {ddram_dq[5]} ]
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set_property SLEW FAST [get_ports {ddram_dq[5]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]} ]
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# ### ddram:0.dq
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##set_property LOC L4 [get_ports {ddram_dq[6]} ]
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set_property SLEW FAST [get_ports {ddram_dq[6]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]} ]
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# ### ddram:0.dq
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##set_property LOC M2 [get_ports {ddram_dq[7]} ]
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set_property SLEW FAST [get_ports {ddram_dq[7]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]} ]
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# ### ddram:0.dq
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##set_property LOC V4 [get_ports {ddram_dq[8]} ]
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set_property SLEW FAST [get_ports {ddram_dq[8]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]} ]
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# ### ddram:0.dq
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##set_property LOC T5 [get_ports {ddram_dq[9]} ]
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set_property SLEW FAST [get_ports {ddram_dq[9]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]} ]
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# ### ddram:0.dq
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##set_property LOC U4 [get_ports {ddram_dq[10]} ]
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set_property SLEW FAST [get_ports {ddram_dq[10]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]} ]
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# ### ddram:0.dq
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##set_property LOC V5 [get_ports {ddram_dq[11]} ]
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set_property SLEW FAST [get_ports {ddram_dq[11]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]} ]
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# ### ddram:0.dq
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##set_property LOC V1 [get_ports {ddram_dq[12]} ]
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set_property SLEW FAST [get_ports {ddram_dq[12]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]} ]
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# ### ddram:0.dq
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##set_property LOC T3 [get_ports {ddram_dq[13]} ]
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set_property SLEW FAST [get_ports {ddram_dq[13]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]} ]
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# ### ddram:0.dq
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##set_property LOC U3 [get_ports {ddram_dq[14]} ]
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set_property SLEW FAST [get_ports {ddram_dq[14]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]} ]
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# ### ddram:0.dq
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##set_property LOC R3 [get_ports {ddram_dq[15]} ]
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set_property SLEW FAST [get_ports {ddram_dq[15]} ]
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set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]} ]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]} ]
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# ### ddram:0.dqs_p
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##set_property LOC N2 [get_ports {ddram_dqs_p[0]} ]
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set_property SLEW FAST [get_ports {ddram_dqs_p[0]} ]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]} ]
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# ### ddram:0.dqs_p
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##set_property LOC U2 [get_ports {ddram_dqs_p[1]} ]
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set_property SLEW FAST [get_ports {ddram_dqs_p[1]} ]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]} ]
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# ### ddram:0.dqs_n
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##set_property LOC N1 [get_ports {ddram_dqs_n[0]} ]
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set_property SLEW FAST [get_ports {ddram_dqs_n[0]} ]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]} ]
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# ### ddram:0.dqs_n
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##set_property LOC V2 [get_ports {ddram_dqs_n[1]} ]
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set_property SLEW FAST [get_ports {ddram_dqs_n[1]} ]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]} ]
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# ### ddram:0.clk_p
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##set_property LOC U9 [get_ports ddram_clk_p]
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set_property SLEW FAST [get_ports ddram_clk_p]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
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# ### ddram:0.clk_n
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##set_property LOC V9 [get_ports ddram_clk_n]
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set_property SLEW FAST [get_ports ddram_clk_n]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
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# ### ddram:0.cke
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##set_property LOC N5 [get_ports ddram_cke]
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set_property SLEW FAST [get_ports ddram_cke]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
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# ### ddram:0.odt
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##set_property LOC R5 [get_ports ddram_odt]
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set_property SLEW FAST [get_ports ddram_odt]
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set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
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# ### ddram:0.reset_n
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##set_property LOC K6 [get_ports ddram_reset_n]
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set_property SLEW FAST [get_ports ddram_reset_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
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# ## eth:0.rst_n
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#set_property LOC C16 [get_ports eth_rst_n]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rst_n]
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# ## eth:0.mdio
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#set_property LOC K13 [get_ports eth_mdio]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_mdio]
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# ## eth:0.mdc
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#set_property LOC F16 [get_ports eth_mdc]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_mdc]
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# ## eth:0.rx_dv
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#set_property LOC G16 [get_ports eth_rx_dv]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_dv]
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# ## eth:0.rx_er
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#set_property LOC C17 [get_ports eth_rx_er]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_er]
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# ## eth:0.rx_data
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#set_property LOC D18 [get_ports {eth_rx_data[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}]
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# ## eth:0.rx_data
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#set_property LOC E17 [get_ports {eth_rx_data[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}]
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# ## eth:0.rx_data
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#set_property LOC E18 [get_ports {eth_rx_data[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}]
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# ## eth:0.rx_data
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#set_property LOC G17 [get_ports {eth_rx_data[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}]
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# ## eth:0.tx_en
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#set_property LOC H15 [get_ports eth_tx_en]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_en]
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# ## eth:0.tx_data
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#set_property LOC H14 [get_ports {eth_tx_data[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}]
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# ## eth:0.tx_data
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#set_property LOC J14 [get_ports {eth_tx_data[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}]
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# ## eth:0.tx_data
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#set_property LOC J13 [get_ports {eth_tx_data[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}]
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# ## eth:0.tx_data
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#set_property LOC H17 [get_ports {eth_tx_data[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}]
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# ## eth:0.col
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#set_property LOC D17 [get_ports eth_col]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_col]
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# ## eth:0.crs
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#set_property LOC G14 [get_ports eth_crs]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_crs]
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set_property INTERNAL_VREF 0.750 [get_iobanks 34]
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#create_clock -name sys_clk -period 16.666 [get_nets sys_clk]
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#
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#create_clock -name clk100 -period 10.0 [get_nets clk100]
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#
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#create_clock -name eth_rx_clk -period 40.0 [get_nets eth_rx_clk]
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#
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#create_clock -name eth_tx_clk -period 40.0 [get_nets eth_tx_clk]
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#
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#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous
|
||||
#
|
||||
#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
#
|
||||
#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
#
|
||||
#set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
|
||||
#
|
||||
#set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
#
|
||||
#set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
Loading…
Reference in New Issue