diff --git a/xc7/counter_test/README.rst b/xc7/counter_test/README.rst
index 5035092..80e766d 100644
--- a/xc7/counter_test/README.rst
+++ b/xc7/counter_test/README.rst
@@ -28,11 +28,17 @@ counter example, depending on your hardware, run:
    TARGET="zybo" make -C counter_test
 
 
+At completion, the bitstreams are located in the build directory:
+
+.. code-block:: bash
+
+   cd counter_test/build/<board>
+
 Now, for **Arty and Basys3**, you can upload the design with:
 
 .. code-block:: bash
 
-   openocd -f ${INSTALL_DIR}/conda/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
+   openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
 
 
 The result should be as follows:
diff --git a/xc7/counter_test/arty.xdc b/xc7/counter_test/arty.xdc
index 4d31d44..79e583f 100644
--- a/xc7/counter_test/arty.xdc
+++ b/xc7/counter_test/arty.xdc
@@ -7,10 +7,10 @@ set_property PACKAGE_PIN H5  [get_ports {led[0]}]
 set_property PACKAGE_PIN J5  [get_ports {led[1]}]
 set_property PACKAGE_PIN T9  [get_ports {led[2]}]
 set_property PACKAGE_PIN T10 [get_ports {led[3]}]
-set_property IOSTANDARD LVCOMOS33 [get_ports {led[0]}]
-set_property IOSTANDARD LVCOMOS33 [get_ports {led[1]}]
-set_property IOSTANDARD LVCOMOS33 [get_ports {led[2]}]
-set_property IOSTANDARD LVCOMOS33 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
 
 # Clock constraints
 create_clock -period 10.0 [get_ports {clk}]
diff --git a/xc7/counter_test/basys3.xdc b/xc7/counter_test/basys3.xdc
index c6df5a9..112fa3e 100644
--- a/xc7/counter_test/basys3.xdc
+++ b/xc7/counter_test/basys3.xdc
@@ -7,10 +7,10 @@ set_property PACKAGE_PIN U16 [get_ports {led[0]}]
 set_property PACKAGE_PIN E19 [get_ports {led[1]}]
 set_property PACKAGE_PIN U19 [get_ports {led[2]}]
 set_property PACKAGE_PIN V19 [get_ports {led[3]}]
-set_property IOSTANDARD LVCOMOS33 [get_ports {led[0]}]
-set_property IOSTANDARD LVCOMOS33 [get_ports {led[1]}]
-set_property IOSTANDARD LVCOMOS33 [get_ports {led[2]}]
-set_property IOSTANDARD LVCOMOS33 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
 
 # Clock constraints
 create_clock -period 10.0 [get_ports {clk}]
diff --git a/xc7/environment.yml b/xc7/environment.yml
index f293816..1e3b25c 100644
--- a/xc7/environment.yml
+++ b/xc7/environment.yml
@@ -7,6 +7,7 @@ dependencies:
   - litex-hub::symbiflow-yosys-plugins=1.0.0_7_g59ff1e6_23_g3a95697_17_g00b887b_0194_g40efa51=20201120_145821
   - litex-hub::prjxray-tools=0.1_2697_g0f939808=20201120_145821
   - litex-hub::prjxray-db=0.0_0239_gd87c844=20201120_145821
+  - litex-hub::openocd=v0.11.0_rc1_1_g0dd3b7fa6=20201209_175951
   - make
   - lxml
   - simplejson
diff --git a/xc7/linux_litex_demo/README.rst b/xc7/linux_litex_demo/README.rst
index 950435d..cee6aa9 100644
--- a/xc7/linux_litex_demo/README.rst
+++ b/xc7/linux_litex_demo/README.rst
@@ -29,11 +29,17 @@ To build the linux-litex-demo example, depending on your hardware, run:
 
    TARGET="arty_100" make -C linux_litex_demo
 
+At completion, the bitstreams are located in the build directory:
+
+.. code-block:: bash
+
+   cd linux_litex_demo/build/<board>
+
 Now you can upload the design with:
 
 .. code-block:: bash
 
-   openocd -f ${INSTALL_DIR}/conda/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
+   openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
 
 .. note::
 
diff --git a/xc7/picosoc_demo/README.rst b/xc7/picosoc_demo/README.rst
index 0f4fa70..b623688 100644
--- a/xc7/picosoc_demo/README.rst
+++ b/xc7/picosoc_demo/README.rst
@@ -21,11 +21,17 @@ picosoc example, run the following commands:
 
    TARGET="basys3" make -C picosoc_demo
 
+At completion, the bitstreams are located in the build directory:
+
+.. code-block:: bash
+
+   cd picosoc_demo/build/<board>
+
 Now you can upload the design with:
 
 .. code-block:: bash
 
-   openocd -f ${INSTALL_DIR}/conda/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
+   openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
 
 
 You should observe the following line in the OpenOCD output: