From 7d011bc4b3b922d84ae6f676953f2846c55b5005 Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Sat, 10 Sep 2022 02:39:35 +0200 Subject: [PATCH 1/2] docs/building-examples: add linux_litex_demo and litex_sata_demo Signed-off-by: Unai Martinez-Corral --- docs/building-examples.rst | 7 ++++--- docs/xc7/linux_litex_demo.rst | 2 ++ docs/xc7/litex_sata_demo.rst | 2 ++ 3 files changed, 8 insertions(+), 3 deletions(-) create mode 100644 docs/xc7/linux_litex_demo.rst create mode 100644 docs/xc7/litex_sata_demo.rst diff --git a/docs/building-examples.rst b/docs/building-examples.rst index 8f0a547..1863a7a 100644 --- a/docs/building-examples.rst +++ b/docs/building-examples.rst @@ -77,11 +77,12 @@ Then, follow the guidelines for each example: .. toctree:: xc7/counter_test - xc7/picosoc_demo - xc7/litex_demo xc7/timer xc7/pulse_width_led - + xc7/picosoc_demo + xc7/litex_demo + xc7/linux_litex_demo + xc7/litex_sata_demo QuickLogic EOS S3 ================= diff --git a/docs/xc7/linux_litex_demo.rst b/docs/xc7/linux_litex_demo.rst new file mode 100644 index 0000000..e608f67 --- /dev/null +++ b/docs/xc7/linux_litex_demo.rst @@ -0,0 +1,2 @@ +.. jinja:: xc7_linux_litex_demo + :file: templates/example.jinja diff --git a/docs/xc7/litex_sata_demo.rst b/docs/xc7/litex_sata_demo.rst new file mode 100644 index 0000000..981ffd0 --- /dev/null +++ b/docs/xc7/litex_sata_demo.rst @@ -0,0 +1,2 @@ +.. jinja:: xc7_litex_sata_demo + :file: templates/example.jinja From c321cd981ee5df761b4f2a33cf447cf45ca19cdd Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Sat, 10 Sep 2022 02:39:35 +0200 Subject: [PATCH 2/2] litex_sata_demo/readme: avoid tables, lists or roles until the jinja template is fixed Signed-off-by: Unai Martinez-Corral --- xc7/litex_sata_demo/README.rst | 39 +++++++++++++++++----------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/xc7/litex_sata_demo/README.rst b/xc7/litex_sata_demo/README.rst index 93f2b19..7da2dd2 100644 --- a/xc7/litex_sata_demo/README.rst +++ b/xc7/litex_sata_demo/README.rst @@ -1,14 +1,15 @@ LiteX SATA demo ~~~~~~~~~~~~~~~ -This example design features a Litex SoC based around VexRiscv soft -CPU. It also includes a DDR controller and a SATA core. +This example design features a Litex SoC based around VexRiscv soft CPU. +It also includes a DDR controller and a SATA core. -The design targets the `Nexys Video `_ board, mounting an Artix-7 200T FPGA, -and the `FMC adapter board `_, mounting an M.2 SSD. - -To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs. Then depending on your hardware, run: +The design targets the `Nexys Video `_ board, +mounting an Artix-7 200T FPGA, and the `FMC adapter board `_, +mounting an M.2 SSD. +To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs. +Then depending on your hardware, run: .. code-block:: bash :name: example-litex-sata-nexys-video-group @@ -21,18 +22,16 @@ At completion, the bitstreams are located in the build directory: litex_sata_demo/build/ -To generate the source files for this test, the following packages were used: +.. NOTE:: + To generate the source files for this test, the following packages were used: + ``enjoy-digital/litex@95b310ee0f0d9e78e00eb32b71324b25265da4f4``, + ``enjoy-digital/litesata@fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7``, + ``enjoy-digital/litedram@2c60861929a317af697267d6219da43d10dcf1fa``, + ``enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91``, + ``litex-hub/litex-boards@ea58ef94a784308ae024a1d201d603bc8459a590``, + and + ``m-labs/migen@c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5``. -=========================================================== ======================================== -Repo URL SHA -=========================================================== ======================================== -`LiteX `_ 95b310ee0f0d9e78e00eb32b71324b25265da4f4 -`LiteSATA `_ fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7 -`LiteDRAM `_ 2c60861929a317af697267d6219da43d10dcf1fa -`LiteICLink `_ 0980a7cf4ffcb0b69a84fa0343a66180408b2a91 -`LiteX Boards `_ ea58ef94a784308ae024a1d201d603bc8459a590 -`migen `_ c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5 -=========================================================== ======================================== - -The generated verilog design file (litesata.v) contains a couple of fixes to properly work with the Yosys+VPR flow. -The fixes are around the GTP high speed transceivers hard blocks. +.. NOTE:: + The generated verilog design file (litesata.v) contains a couple of fixes to properly work with the Yosys+VPR flow. + The fixes are around the GTP high speed transceivers hard blocks.