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Merge pull request #363 from antmicro/umarcor/docs/litex 

docs/building-examples: add linux_litex_demo and litex_sata_demo
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Tomasz Michalak 2022-12-16 11:45:39 +01:00 committed by GitHub
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7
docs/building-examples.rst
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@ -77,11 +77,12 @@ Then, follow the guidelines for each example:
.. toctree::
xc7/counter_test
xc7/picosoc_demo
xc7/litex_demo
xc7/timer
xc7/pulse_width_led
xc7/picosoc_demo
xc7/litex_demo
xc7/linux_litex_demo
xc7/litex_sata_demo
QuickLogic EOS S3
=================

2
docs/xc7/linux_litex_demo.rst Normal file
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@ -0,0 +1,2 @@
.. jinja:: xc7_linux_litex_demo
:file: templates/example.jinja

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docs/xc7/litex_sata_demo.rst Normal file
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@ -0,0 +1,2 @@
.. jinja:: xc7_litex_sata_demo
:file: templates/example.jinja

33
xc7/litex_sata_demo/README.rst
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@ -1,14 +1,15 @@
LiteX SATA demo
~~~~~~~~~~~~~~~
This example design features a Litex SoC based around VexRiscv soft
CPU. It also includes a DDR controller and a SATA core.
This example design features a Litex SoC based around VexRiscv soft CPU.
It also includes a DDR controller and a SATA core.
The design targets the `Nexys Video <https://digilent.com/reference/programmable-logic/nexys-video/start>`_ board, mounting an Artix-7 200T FPGA,
and the `FMC adapter board <https://github.com/antmicro/fmc-sata-adapter>`_, mounting an M.2 SSD.
To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs. Then depending on your hardware, run:
The design targets the `Nexys Video <https://digilent.com/reference/programmable-logic/nexys-video/start>`_ board,
mounting an Artix-7 200T FPGA, and the `FMC adapter board <https://github.com/antmicro/fmc-sata-adapter>`_,
mounting an M.2 SSD.
To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs.
Then depending on your hardware, run:
.. code-block:: bash
:name: example-litex-sata-nexys-video-group
@ -21,18 +22,16 @@ At completion, the bitstreams are located in the build directory:
litex_sata_demo/build/<board>
.. NOTE::
To generate the source files for this test, the following packages were used:
``enjoy-digital/litex@95b310ee0f0d9e78e00eb32b71324b25265da4f4``,
``enjoy-digital/litesata@fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7``,
``enjoy-digital/litedram@2c60861929a317af697267d6219da43d10dcf1fa``,
``enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91``,
``litex-hub/litex-boards@ea58ef94a784308ae024a1d201d603bc8459a590``,
and
``m-labs/migen@c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5``.
=========================================================== ========================================
Repo URL SHA
=========================================================== ========================================
`LiteX <https://github.com/enjoy-digital/litex>`_ 95b310ee0f0d9e78e00eb32b71324b25265da4f4
`LiteSATA <https://github.com/enjoy-digital/litesata>`_ fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7
`LiteDRAM <https://github.com/enjoy-digital/litedram>`_ 2c60861929a317af697267d6219da43d10dcf1fa
`LiteICLink <https://github.com/enjoy-digital/liteiclink>`_ 0980a7cf4ffcb0b69a84fa0343a66180408b2a91
`LiteX Boards <https://github.com/litex-hub/litex-boards>`_ ea58ef94a784308ae024a1d201d603bc8459a590
`migen <https://github.com/m-labs/migen>`_ c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5
=========================================================== ========================================
.. NOTE::
The generated verilog design file (litesata.v) contains a couple of fixes to properly work with the Yosys+VPR flow.
The fixes are around the GTP high speed transceivers hard blocks.