picosoc: Add arty35 and arty100 boards
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
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f0134981b9
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@ -1,8 +1,7 @@
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mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
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current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
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TOP := basys3_demo
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VERILOG := ${current_dir}/basys3_demo_no_roi.v \
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${current_dir}/picosoc_noflash.v \
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TOP := top
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VERILOG := ${current_dir}/picosoc_noflash.v \
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${current_dir}/picorv32.v \
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${current_dir}/simpleuart.v \
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${current_dir}/progmem.v
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@ -10,9 +9,27 @@ PARTNAME := xc7a35tcpg236-1
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DEVICE := xc7a50t_test
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BITSTREAM_DEVICE := artix7
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PCF := ${current_dir}/basys3.pcf
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SDC := ${current_dir}/basys3.sdc
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SDC := ${current_dir}/picosoc.sdc
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BUILDDIR := build
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ifeq ($(TARGET),arty_35)
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VERILOG += ${current_dir}/arty.v
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PARTNAME := xc7a35tcsg324-1
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PCF :=${current_dir}/arty.pcf
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BOARD_BUILDDIR := ${BUILDDIR}/arty_35
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else ifeq ($(TARGET),arty_100)
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VERILOG += ${current_dir}/arty.v
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PARTNAME := xc7a100tcsg324-1
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PCF:=${current_dir}/arty.pcf
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DEVICE := xc7a100t_test
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BOARD_BUILDDIR := ${BUILDDIR}/arty_100
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else
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VERILOG += ${current_dir}/basys3.v
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PARTNAME := xc7a35tcpg236-1
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PCF := ${current_dir}/basys3.pcf
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BOARD_BUILDDIR := ${BUILDDIR}/basys3
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endif
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all: ${BUILDDIR}/${TOP}.bit
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${BUILDDIR}:
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@ -0,0 +1,12 @@
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# 100 MHz CLK
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set_io clk E3
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# UART
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set_io rx A9
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set_io tx D10
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# LEDs
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set_io led[0] H5
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set_io led[1] J5
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set_io led[2] T9
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set_io led[3] T10
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@ -0,0 +1,86 @@
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/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module top (
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input clk,
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output tx,
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input rx,
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input [3:0] sw,
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output [3:0] led
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);
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wire clk_bufg;
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BUFG bufg (.I(clk), .O(clk_bufg));
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reg [5:0] reset_cnt = 0;
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wire resetn = &reset_cnt;
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always @(posedge clk_bufg) begin
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reset_cnt <= reset_cnt + !resetn;
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end
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wire iomem_valid;
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reg iomem_ready;
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wire [3:0] iomem_wstrb;
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wire [31:0] iomem_addr;
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wire [31:0] iomem_wdata;
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reg [31:0] iomem_rdata;
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reg [31:0] gpio;
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assign led = gpio[3:0];
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always @(posedge clk_bufg) begin
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if (!resetn) begin
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gpio <= 0;
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end else begin
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iomem_ready <= 0;
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if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
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iomem_ready <= 1;
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iomem_rdata <= {4{sw, gpio[3:0]}};
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if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
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if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
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if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
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if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
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end
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end
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end
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picosoc_noflash soc (
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.clk (clk_bufg),
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.resetn (resetn ),
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.ser_tx (tx),
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.ser_rx (rx),
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.irq_5 (1'b0 ),
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.irq_6 (1'b0 ),
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.irq_7 (1'b0 ),
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.iomem_valid (iomem_valid ),
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.iomem_ready (iomem_ready ),
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.iomem_wstrb (iomem_wstrb ),
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.iomem_addr (iomem_addr ),
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.iomem_wdata (iomem_wdata ),
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.iomem_rdata (iomem_rdata )
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);
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endmodule
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@ -17,13 +17,13 @@
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*
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*/
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module basys3_demo (
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module top (
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input clk,
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output tx,
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input rx,
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input [15:0] sw,
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input [15:0] sw,
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output [15:0] led
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);
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