picosoc: Add arty35 and arty100 boards

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak 2020-12-08 13:06:54 +01:00
parent f0134981b9
commit 937ccab442
5 changed files with 121 additions and 6 deletions

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@ -1,8 +1,7 @@
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
TOP := basys3_demo
VERILOG := ${current_dir}/basys3_demo_no_roi.v \
${current_dir}/picosoc_noflash.v \
TOP := top
VERILOG := ${current_dir}/picosoc_noflash.v \
${current_dir}/picorv32.v \
${current_dir}/simpleuart.v \
${current_dir}/progmem.v
@ -10,9 +9,27 @@ PARTNAME := xc7a35tcpg236-1
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
PCF := ${current_dir}/basys3.pcf
SDC := ${current_dir}/basys3.sdc
SDC := ${current_dir}/picosoc.sdc
BUILDDIR := build
ifeq ($(TARGET),arty_35)
VERILOG += ${current_dir}/arty.v
PARTNAME := xc7a35tcsg324-1
PCF :=${current_dir}/arty.pcf
BOARD_BUILDDIR := ${BUILDDIR}/arty_35
else ifeq ($(TARGET),arty_100)
VERILOG += ${current_dir}/arty.v
PARTNAME := xc7a100tcsg324-1
PCF:=${current_dir}/arty.pcf
DEVICE := xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/arty_100
else
VERILOG += ${current_dir}/basys3.v
PARTNAME := xc7a35tcpg236-1
PCF := ${current_dir}/basys3.pcf
BOARD_BUILDDIR := ${BUILDDIR}/basys3
endif
all: ${BUILDDIR}/${TOP}.bit
${BUILDDIR}:

12
xc7/picosoc_demo/arty.pcf Normal file
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@ -0,0 +1,12 @@
# 100 MHz CLK
set_io clk E3
# UART
set_io rx A9
set_io tx D10
# LEDs
set_io led[0] H5
set_io led[1] J5
set_io led[2] T9
set_io led[3] T10

86
xc7/picosoc_demo/arty.v Normal file
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@ -0,0 +1,86 @@
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module top (
input clk,
output tx,
input rx,
input [3:0] sw,
output [3:0] led
);
wire clk_bufg;
BUFG bufg (.I(clk), .O(clk_bufg));
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[3:0];
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {4{sw, gpio[3:0]}};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk_bufg),
.resetn (resetn ),
.ser_tx (tx),
.ser_rx (rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
endmodule

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@ -17,13 +17,13 @@
*
*/
module basys3_demo (
module top (
input clk,
output tx,
input rx,
input [15:0] sw,
input [15:0] sw,
output [15:0] led
);