From a0b165eb902a07d4e2c06d55f8c01226c50ae4b7 Mon Sep 17 00:00:00 2001
From: Alessandro Comodi <acomodi@antmicro.com>
Date: Mon, 21 Dec 2020 15:11:34 +0100
Subject: [PATCH] xc7: added litex to readme

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
---
 xc7/README.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xc7/README.rst b/xc7/README.rst
index 72f9c5a..601fc6e 100644
--- a/xc7/README.rst
+++ b/xc7/README.rst
@@ -3,6 +3,7 @@ SymbiFlow Toolchain Examples for Xilinx 7 Series
 
 #. ``counter`` - simple 4-bit counter driving LEDs. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__, the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__, and the `Zybo Z7 board <https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/>`__
 #. ``picosoc`` - `picorv32 <https://github.com/cliffordwolf/picorv32>`__ based SoC. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__.
+#. ``litex`` - Series of `LiteX-based <https://github.com/enjoy-digital/litex>`__ designs, that feature different CPU types and LiteX modules.
 #. ``linux_litex`` - `LiteX <https://github.com/enjoy-digital/litex>`__ based system with Linux capable `VexRiscv core <https://github.com/SpinalHDL/VexRiscv>`__. The design includes `DDR <https://github.com/enjoy-digital/litedram>`__ and `Ethernet <https://github.com/enjoy-digital/liteeth>`__ controllers. The design targets the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__.
 
 The Linux images for the ``linux_litex`` example can be built following the `linux on litex vexriscv <https://github.com/litex-hub/linux-on-litex-vexriscv>`__ instructions.