diff --git a/xc7/litex_demo/README.rst b/xc7/litex_demo/README.rst index 5ef7cde..62f7f63 100644 --- a/xc7/litex_demo/README.rst +++ b/xc7/litex_demo/README.rst @@ -23,24 +23,24 @@ There are multiple CPU types supported, choose one from the below commands to ge .. code-block:: bash :name: example-litex_picorv32-a35t-group - ./arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_35 --board-variant a7-35 --build + ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_35 --variant a7-35 --build .. code-block:: bash :name: example-litex_picorv32-a100t-group - ./arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_100 --board-variant a7-100 --build + ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_100 --variant a7-100 --build **VexRiscv** .. code-block:: bash :name: example-litex_vexriscv-a35t-group - ./arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_35 --board-variant a7-35 --build + ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_35 --variant a7-35 --build .. code-block:: bash :name: example-litex_vexriscv-a100t-group - ./arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_100 --board-variant a7-100 --build + ./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_100 --variant a7-100 --build Depending on which board and CPU-type you selected, the bitstream is loacted in: diff --git a/xc7/litex_demo/arty.py b/xc7/litex_demo/arty.py deleted file mode 100755 index 9cdc667..0000000 --- a/xc7/litex_demo/arty.py +++ /dev/null @@ -1,156 +0,0 @@ -#!/usr/bin/env python3 -# -# This file is part of LiteX. -# -# Copyright (c) 2015-2019 Florent Kermarrec -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: BSD-2-Clause - -import os -import argparse - -from migen import * - -from litex.boards.platforms import arty -from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict - -from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * -from litex.soc.integration.builder import * -from litex.soc.cores.led import LedChaser - -from litedram.modules import MT41K128M16 -from litedram.phy import s7ddrphy - -from liteeth.phy.mii import LiteEthPHYMII - -# CRG ---------------------------------------------------------------------------------------------- - -class _CRG(Module): - def __init__(self, platform, sys_clk_freq): - self.rst = Signal() - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_idelay = ClockDomain() - self.clock_domains.cd_eth = ClockDomain() - - # # # - - self.submodules.pll = pll = S7PLL(speedgrade=-1) - self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst) - pll.register_clkin(platform.request("clk100"), 100e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_idelay, 200e6) - pll.create_clkout(self.cd_eth, 25e6) - - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) - - self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk) - -# BaseSoC ------------------------------------------------------------------------------------------ - -class BaseSoC(SoCCore): - def __init__( - self, - toolchain="vivado", - sys_clk_freq=int(100e6), - with_ethernet=False, - with_etherbone=False, - ident_version=True, - board_variant="a7-35", - **kwargs - ): - platform = arty.Platform(variant=board_variant, toolchain=toolchain) - - # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, sys_clk_freq, - ident = "LiteX SoC on Arty A7", - ident_version = ident_version, - **kwargs) - - # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) - - # DDR3 SDRAM ------------------------------------------------------------------------------- - if not self.integrated_main_ram_size: - self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), - memtype = "DDR3", - nphases = 4, - sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") - self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K128M16(sys_clk_freq, "1:4"), - origin = self.mem_map["main_ram"], - size = kwargs.get("max_sdram_size", 0x40000000), - l2_cache_size = kwargs.get("l2_size", 8192), - l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = True - ) - - # Ethernet / Etherbone --------------------------------------------------------------------- - if with_ethernet or with_etherbone: - self.submodules.ethphy = LiteEthPHYMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - if with_ethernet: - self.add_ethernet(phy=self.ethphy) - if with_etherbone: - self.add_etherbone(phy=self.ethphy) - - # Leds ------------------------------------------------------------------------------------- - self.submodules.leds = LedChaser( - pads = platform.request_all("user_led"), - sys_clk_freq = sys_clk_freq) - self.add_csr("leds") - -# Build -------------------------------------------------------------------------------------------- - -def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") - parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)") - parser.add_argument("--board-variant", default="a7-35", help="Board variant (default: a7-35)") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") - parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") - parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") - parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output") - builder_args(parser) - soc_sdram_args(parser) - vivado_build_args(parser) - args = parser.parse_args() - - assert not (args.with_ethernet and args.with_etherbone) - soc = BaseSoC( - toolchain = args.toolchain, - sys_clk_freq = int(float(args.sys_clk_freq)), - with_ethernet = args.with_ethernet, - with_etherbone = args.with_etherbone, - ident_version = args.no_ident_version, - board_variant = args.board_variant, - **soc_sdram_argdict(args) - ) - assert not (args.with_spi_sdcard and args.with_sdcard) - soc.platform.add_extension(arty._sdcard_pmod_io) - if args.with_spi_sdcard: - soc.add_spi_sdcard() - if args.with_sdcard: - soc.add_sdcard() - builder = Builder(soc, **builder_argdict(args)) - builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {} - builder.build(**builder_kwargs, run=args.build) - - if args.load: - prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) - -if __name__ == "__main__": - main() diff --git a/xc7/litex_demo/requirements.txt b/xc7/litex_demo/requirements.txt index e1d2cd6..369ed30 100644 --- a/xc7/litex_demo/requirements.txt +++ b/xc7/litex_demo/requirements.txt @@ -1,5 +1,5 @@ # LiteX --e git+https://github.com/enjoy-digital/litex@4092180662ec62cf28b9283a020f1ff7f0892c19#egg=litex +-e git+https://github.com/enjoy-digital/litex@afbac26e8015fdca70e7b2bc1477db31f7860c38#egg=litex -e git+https://github.com/enjoy-digital/litedram@103072c68a2e3ec9c81f198e50e5427e5780580c#egg=litedram -e git+https://github.com/enjoy-digital/liteeth@617400fe9e5b902e6bfd39a7c32ef5b255bc10c0#egg=liteeth -e git+https://github.com/enjoy-digital/liteiclink@8b29505096406d242685bf71b16a0ce4e4be54aa#egg=liteiclink