From e18e544825c8ab99748ac6a5ee8ed34d24788414 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Wed, 24 Nov 2021 15:46:06 +0100 Subject: [PATCH] xc7: add lite SATA example Signed-off-by: Alessandro Comodi --- xc7/litex_sata_demo/Makefile | 8 + xc7/litex_sata_demo/README.rst | 21 + xc7/litex_sata_demo/VexRiscv.v | 5849 +++++++++ xc7/litex_sata_demo/litesata.v | 17870 ++++++++++++++++++++++++++ xc7/litex_sata_demo/mem.init | 9589 ++++++++++++++ xc7/litex_sata_demo/mem_1.init | 0 xc7/litex_sata_demo/mem_2.init | 45 + xc7/litex_sata_demo/nexys_video.xdc | 340 + 8 files changed, 33722 insertions(+) create mode 100644 xc7/litex_sata_demo/Makefile create mode 100644 xc7/litex_sata_demo/README.rst create mode 100644 xc7/litex_sata_demo/VexRiscv.v create mode 100644 xc7/litex_sata_demo/litesata.v create mode 100644 xc7/litex_sata_demo/mem.init create mode 100644 xc7/litex_sata_demo/mem_1.init create mode 100644 xc7/litex_sata_demo/mem_2.init create mode 100644 xc7/litex_sata_demo/nexys_video.xdc diff --git a/xc7/litex_sata_demo/Makefile b/xc7/litex_sata_demo/Makefile new file mode 100644 index 0000000..620d901 --- /dev/null +++ b/xc7/litex_sata_demo/Makefile @@ -0,0 +1,8 @@ +current_dir := ${CURDIR} +TOP := top +SOURCES := ${current_dir}/litesata.v \ + ${current_dir}/VexRiscv.v + +XDC := ${current_dir}/nexys_video.xdc + +include ${current_dir}/../../common/common.mk diff --git a/xc7/litex_sata_demo/README.rst b/xc7/litex_sata_demo/README.rst new file mode 100644 index 0000000..625ad62 --- /dev/null +++ b/xc7/litex_sata_demo/README.rst @@ -0,0 +1,21 @@ +LiteX SATA demo +~~~~~~~~~~~~~~~ + +This example design features a Litex SoC based around VexRiscv soft +CPU. It also includes a DDR controller and a SATA core . To build the litex SATA example, +run the following commands: + +To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs. Then depending on your hardware, run: + + +.. code-block:: bash + :name: example-litex-sata-nexys-video-group + + TARGET="nexys_video" make -C litex_sata_demo + +At completion, the bitstreams are located in the build directory: + +.. code-block:: bash + + litex_sata_demo/build/ + diff --git a/xc7/litex_sata_demo/VexRiscv.v b/xc7/litex_sata_demo/VexRiscv.v new file mode 100644 index 0000000..9ee4975 --- /dev/null +++ b/xc7/litex_sata_demo/VexRiscv.v @@ -0,0 +1,5849 @@ +// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 +// Date : 23/03/2020, 17:06:19 +// Component : VexRiscv + + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [21:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [21:0] _zz_16_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [6:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_7_; + wire [9:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; + assign _zz_12_ = (! lineLoader_flushCounter[7]); + assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_14_ = _zz_7_[0 : 0]; + assign _zz_15_ = _zz_7_[1 : 1]; + assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_10_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_11_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_12_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_10_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_11_; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; + assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_13_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_12_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); + end + _zz_3_ <= lineLoader_flushCounter[7]; + if(_zz_13_)begin + lineLoader_flushCounter <= (8'b00000000); + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + input io_cpu_memory_isRemoved, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + output io_cpu_memory_mmuBus_cmd_isValid, + output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, + output io_cpu_memory_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, + input io_cpu_memory_mmuBus_rsp_isIoAccess, + input io_cpu_memory_mmuBus_rsp_allowRead, + input io_cpu_memory_mmuBus_rsp_allowWrite, + input io_cpu_memory_mmuBus_rsp_allowExecute, + input io_cpu_memory_mmuBus_rsp_exception, + input io_cpu_memory_mmuBus_rsp_refilling, + output io_cpu_memory_mmuBus_end, + input io_cpu_memory_mmuBus_busy, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output reg io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [21:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire _zz_14_; + wire _zz_15_; + wire _zz_16_; + wire _zz_17_; + wire [0:0] _zz_18_; + wire [0:0] _zz_19_; + wire [0:0] _zz_20_; + wire [2:0] _zz_21_; + wire [1:0] _zz_22_; + wire [21:0] _zz_23_; + reg _zz_1_; + reg _zz_2_; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3_; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4_; + wire _zz_5_; + wire [31:0] ways_0_dataReadRsp; + reg [3:0] _zz_6_; + wire [3:0] stage0_mask; + wire [0:0] stage0_colisions; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg [3:0] stageA_mask; + wire stageA_wayHits_0; + reg [0:0] stage0_colisions_regNextWhen; + wire [0:0] _zz_7_; + wire [0:0] stageA_colisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + wire [0:0] _zz_8_; + reg [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg [0:0] stageB_colisions; + reg stageB_loaderValid; + reg stageB_flusher_valid; + wire [31:0] stageB_requestDataBypass; + wire stageB_isAmo; + reg stageB_memCmdSent; + wire [0:0] _zz_9_; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_24_; + reg [7:0] _zz_25_; + reg [7:0] _zz_26_; + reg [7:0] _zz_27_; + assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); + assign _zz_15_ = (loader_valid && io_mem_rsp_valid); + assign _zz_16_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + assign _zz_17_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign _zz_18_ = _zz_4_[0 : 0]; + assign _zz_19_ = _zz_4_[1 : 1]; + assign _zz_20_ = loader_counter_willIncrement; + assign _zz_21_ = {2'd0, _zz_20_}; + assign _zz_22_ = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_23_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_23_; + end + end + + always @ (posedge clk) begin + if(_zz_3_) begin + _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (*) begin + _zz_11_ = {_zz_27_, _zz_26_, _zz_25_, _zz_24_}; + end + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1_) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1_) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1_) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1_) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (posedge clk) begin + if(_zz_5_) begin + _zz_24_ <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_25_ <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_26_ <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_27_ <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2_ = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4_ = _zz_10_; + assign ways_0_tagsReadRsp_valid = _zz_18_[0]; + assign ways_0_tagsReadRsp_error = _zz_19_[0]; + assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; + assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRsp = _zz_11_; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12_)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = (7'bxxxxxxx); + if(_zz_12_)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12_)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = (10'bxxxxxxxxxx); + if(_zz_12_)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13_)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = (1'bx); + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = (1'b1); + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = (7'bxxxxxxx); + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_15_)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = (1'bx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = (10'bxxxxxxxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_data = stageB_requestDataBypass; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = (4'bxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_mask = stageB_mask; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_mask = (4'b1111); + end + end + + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6_ = (4'b0001); + end + 2'b01 : begin + _zz_6_ = (4'b0011); + end + default : begin + _zz_6_ = (4'b1111); + end + endcase + end + + assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); + assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; + assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; + assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign _zz_8_[0] = stageA_wayHits_0; + assign stageB_waysHit = (stageB_waysHits != (1'b0)); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + if(_zz_13_)begin + stageB_loaderValid = 1'b0; + end + end + + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_14_)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + if(_zz_13_)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(_zz_16_)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_requestDataBypass = stageB_request_data; + assign stageB_isAmo = 1'b0; + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin + io_cpu_redo = 1'b1; + end + end + end + end + if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin + io_cpu_redo = 1'b1; + end + if(loader_valid)begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); + end + end + + assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_valid = (! stageB_memCmdSent); + end else begin + if(_zz_14_)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! stageB_memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = (3'bxxx); + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + io_mem_cmd_payload_length = (3'b111); + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_last = 1'bx; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + io_mem_cmd_payload_last = 1'b1; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + always @ (*) begin + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_data = io_mem_rsp_payload_data; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9_[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_15_)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_21_); + if(loader_counter_willClear)begin + loader_counter_valueNext = (3'b000); + end + end + + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stage0_colisions_regNextWhen <= stage0_colisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + end + if(_zz_17_)begin + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHits <= _zz_8_; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_colisions <= stageA_colisions; + end + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("ERROR writeBack stuck by another plugin is not allowed"); + end + end + + always @ (posedge clk) begin + if(reset) begin + stageB_flusher_valid <= 1'b1; + stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); + stageB_memCmdSent <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= (3'b000); + loader_waysAllocator <= (1'b1); + loader_error <= 1'b0; + end else begin + if(_zz_17_)begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; + end + if(stageB_flusher_valid)begin + if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); + end else begin + stageB_flusher_valid <= 1'b0; + end + end + if(_zz_16_)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); + stageB_flusher_valid <= 1'b1; + end + if(io_mem_cmd_ready)begin + stageB_memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_memCmdSent <= 1'b0; + end + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(_zz_15_)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_counter_willOverflow)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_22_[0:0]; + end + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset); + wire _zz_221_; + wire _zz_222_; + wire _zz_223_; + wire _zz_224_; + wire [31:0] _zz_225_; + wire _zz_226_; + wire _zz_227_; + wire _zz_228_; + reg _zz_229_; + wire _zz_230_; + wire [31:0] _zz_231_; + wire _zz_232_; + wire [31:0] _zz_233_; + reg _zz_234_; + wire _zz_235_; + wire _zz_236_; + wire [31:0] _zz_237_; + wire _zz_238_; + wire _zz_239_; + reg [31:0] _zz_240_; + reg [31:0] _zz_241_; + reg [31:0] _zz_242_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1__io_cpu_memory_isWrite; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + wire dataCache_1__io_cpu_memory_mmuBus_end; + wire dataCache_1__io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1__io_cpu_writeBack_data; + wire dataCache_1__io_cpu_writeBack_mmuException; + wire dataCache_1__io_cpu_writeBack_unalignedAccess; + wire dataCache_1__io_cpu_writeBack_accessError; + wire dataCache_1__io_cpu_writeBack_isWrite; + wire dataCache_1__io_cpu_flush_ready; + wire dataCache_1__io_cpu_redo; + wire dataCache_1__io_mem_cmd_valid; + wire dataCache_1__io_mem_cmd_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_payload_length; + wire dataCache_1__io_mem_cmd_payload_last; + wire _zz_243_; + wire _zz_244_; + wire _zz_245_; + wire _zz_246_; + wire _zz_247_; + wire _zz_248_; + wire _zz_249_; + wire _zz_250_; + wire _zz_251_; + wire _zz_252_; + wire _zz_253_; + wire _zz_254_; + wire _zz_255_; + wire _zz_256_; + wire [1:0] _zz_257_; + wire _zz_258_; + wire _zz_259_; + wire _zz_260_; + wire _zz_261_; + wire _zz_262_; + wire _zz_263_; + wire _zz_264_; + wire _zz_265_; + wire _zz_266_; + wire [1:0] _zz_267_; + wire _zz_268_; + wire _zz_269_; + wire _zz_270_; + wire _zz_271_; + wire _zz_272_; + wire _zz_273_; + wire _zz_274_; + wire [1:0] _zz_275_; + wire _zz_276_; + wire [1:0] _zz_277_; + wire [4:0] _zz_278_; + wire [2:0] _zz_279_; + wire [31:0] _zz_280_; + wire [11:0] _zz_281_; + wire [31:0] _zz_282_; + wire [19:0] _zz_283_; + wire [11:0] _zz_284_; + wire [31:0] _zz_285_; + wire [31:0] _zz_286_; + wire [19:0] _zz_287_; + wire [11:0] _zz_288_; + wire [2:0] _zz_289_; + wire [2:0] _zz_290_; + wire [0:0] _zz_291_; + wire [0:0] _zz_292_; + wire [0:0] _zz_293_; + wire [0:0] _zz_294_; + wire [0:0] _zz_295_; + wire [0:0] _zz_296_; + wire [0:0] _zz_297_; + wire [0:0] _zz_298_; + wire [0:0] _zz_299_; + wire [0:0] _zz_300_; + wire [0:0] _zz_301_; + wire [0:0] _zz_302_; + wire [0:0] _zz_303_; + wire [0:0] _zz_304_; + wire [0:0] _zz_305_; + wire [0:0] _zz_306_; + wire [0:0] _zz_307_; + wire [0:0] _zz_308_; + wire [2:0] _zz_309_; + wire [4:0] _zz_310_; + wire [11:0] _zz_311_; + wire [11:0] _zz_312_; + wire [31:0] _zz_313_; + wire [31:0] _zz_314_; + wire [31:0] _zz_315_; + wire [31:0] _zz_316_; + wire [31:0] _zz_317_; + wire [31:0] _zz_318_; + wire [31:0] _zz_319_; + wire [32:0] _zz_320_; + wire [31:0] _zz_321_; + wire [32:0] _zz_322_; + wire [11:0] _zz_323_; + wire [19:0] _zz_324_; + wire [11:0] _zz_325_; + wire [31:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire [11:0] _zz_329_; + wire [19:0] _zz_330_; + wire [11:0] _zz_331_; + wire [2:0] _zz_332_; + wire [1:0] _zz_333_; + wire [1:0] _zz_334_; + wire [51:0] _zz_335_; + wire [51:0] _zz_336_; + wire [51:0] _zz_337_; + wire [32:0] _zz_338_; + wire [51:0] _zz_339_; + wire [49:0] _zz_340_; + wire [51:0] _zz_341_; + wire [49:0] _zz_342_; + wire [51:0] _zz_343_; + wire [65:0] _zz_344_; + wire [65:0] _zz_345_; + wire [31:0] _zz_346_; + wire [31:0] _zz_347_; + wire [0:0] _zz_348_; + wire [5:0] _zz_349_; + wire [32:0] _zz_350_; + wire [32:0] _zz_351_; + wire [31:0] _zz_352_; + wire [31:0] _zz_353_; + wire [32:0] _zz_354_; + wire [32:0] _zz_355_; + wire [32:0] _zz_356_; + wire [0:0] _zz_357_; + wire [32:0] _zz_358_; + wire [0:0] _zz_359_; + wire [32:0] _zz_360_; + wire [0:0] _zz_361_; + wire [31:0] _zz_362_; + wire [0:0] _zz_363_; + wire [0:0] _zz_364_; + wire [0:0] _zz_365_; + wire [0:0] _zz_366_; + wire [0:0] _zz_367_; + wire [0:0] _zz_368_; + wire [26:0] _zz_369_; + wire _zz_370_; + wire _zz_371_; + wire [2:0] _zz_372_; + wire _zz_373_; + wire _zz_374_; + wire _zz_375_; + wire [31:0] _zz_376_; + wire [31:0] _zz_377_; + wire [31:0] _zz_378_; + wire [0:0] _zz_379_; + wire [2:0] _zz_380_; + wire [0:0] _zz_381_; + wire [0:0] _zz_382_; + wire _zz_383_; + wire [0:0] _zz_384_; + wire [25:0] _zz_385_; + wire [31:0] _zz_386_; + wire [31:0] _zz_387_; + wire [31:0] _zz_388_; + wire _zz_389_; + wire _zz_390_; + wire [31:0] _zz_391_; + wire [0:0] _zz_392_; + wire [2:0] _zz_393_; + wire [0:0] _zz_394_; + wire [0:0] _zz_395_; + wire [0:0] _zz_396_; + wire [0:0] _zz_397_; + wire _zz_398_; + wire [0:0] _zz_399_; + wire [22:0] _zz_400_; + wire [31:0] _zz_401_; + wire [31:0] _zz_402_; + wire [31:0] _zz_403_; + wire [31:0] _zz_404_; + wire _zz_405_; + wire [0:0] _zz_406_; + wire [0:0] _zz_407_; + wire [31:0] _zz_408_; + wire [31:0] _zz_409_; + wire [31:0] _zz_410_; + wire [31:0] _zz_411_; + wire [31:0] _zz_412_; + wire [31:0] _zz_413_; + wire _zz_414_; + wire [0:0] _zz_415_; + wire [0:0] _zz_416_; + wire _zz_417_; + wire [0:0] _zz_418_; + wire [20:0] _zz_419_; + wire [31:0] _zz_420_; + wire [31:0] _zz_421_; + wire [31:0] _zz_422_; + wire [31:0] _zz_423_; + wire [31:0] _zz_424_; + wire [4:0] _zz_425_; + wire [4:0] _zz_426_; + wire _zz_427_; + wire [0:0] _zz_428_; + wire [17:0] _zz_429_; + wire [31:0] _zz_430_; + wire _zz_431_; + wire [0:0] _zz_432_; + wire [0:0] _zz_433_; + wire [31:0] _zz_434_; + wire [31:0] _zz_435_; + wire [31:0] _zz_436_; + wire [1:0] _zz_437_; + wire [1:0] _zz_438_; + wire _zz_439_; + wire [0:0] _zz_440_; + wire [13:0] _zz_441_; + wire [31:0] _zz_442_; + wire [31:0] _zz_443_; + wire [31:0] _zz_444_; + wire [31:0] _zz_445_; + wire _zz_446_; + wire [0:0] _zz_447_; + wire [0:0] _zz_448_; + wire [0:0] _zz_449_; + wire [0:0] _zz_450_; + wire _zz_451_; + wire [0:0] _zz_452_; + wire [10:0] _zz_453_; + wire [31:0] _zz_454_; + wire [31:0] _zz_455_; + wire [0:0] _zz_456_; + wire [3:0] _zz_457_; + wire [0:0] _zz_458_; + wire [0:0] _zz_459_; + wire [0:0] _zz_460_; + wire [0:0] _zz_461_; + wire _zz_462_; + wire [0:0] _zz_463_; + wire [7:0] _zz_464_; + wire [31:0] _zz_465_; + wire [31:0] _zz_466_; + wire [31:0] _zz_467_; + wire _zz_468_; + wire [0:0] _zz_469_; + wire [0:0] _zz_470_; + wire [31:0] _zz_471_; + wire [31:0] _zz_472_; + wire [31:0] _zz_473_; + wire [31:0] _zz_474_; + wire [31:0] _zz_475_; + wire [0:0] _zz_476_; + wire [1:0] _zz_477_; + wire [2:0] _zz_478_; + wire [2:0] _zz_479_; + wire _zz_480_; + wire [0:0] _zz_481_; + wire [4:0] _zz_482_; + wire [31:0] _zz_483_; + wire [31:0] _zz_484_; + wire [31:0] _zz_485_; + wire [31:0] _zz_486_; + wire [31:0] _zz_487_; + wire [31:0] _zz_488_; + wire [31:0] _zz_489_; + wire _zz_490_; + wire _zz_491_; + wire _zz_492_; + wire [0:0] _zz_493_; + wire [0:0] _zz_494_; + wire _zz_495_; + wire [1:0] _zz_496_; + wire [1:0] _zz_497_; + wire _zz_498_; + wire [0:0] _zz_499_; + wire [2:0] _zz_500_; + wire [31:0] _zz_501_; + wire [31:0] _zz_502_; + wire [31:0] _zz_503_; + wire [31:0] _zz_504_; + wire [31:0] _zz_505_; + wire [31:0] _zz_506_; + wire [31:0] _zz_507_; + wire [31:0] _zz_508_; + wire _zz_509_; + wire [0:0] _zz_510_; + wire [0:0] _zz_511_; + wire [1:0] _zz_512_; + wire [1:0] _zz_513_; + wire _zz_514_; + wire [0:0] _zz_515_; + wire [0:0] _zz_516_; + wire [31:0] _zz_517_; + wire [31:0] _zz_518_; + wire [31:0] _zz_519_; + wire [31:0] _zz_520_; + wire [31:0] _zz_521_; + wire _zz_522_; + wire _zz_523_; + wire [0:0] _zz_524_; + wire [1:0] _zz_525_; + wire _zz_526_; + wire [31:0] _zz_527_; + wire [31:0] _zz_528_; + wire [31:0] _zz_529_; + wire _zz_530_; + wire [0:0] _zz_531_; + wire [13:0] _zz_532_; + wire [31:0] _zz_533_; + wire [31:0] _zz_534_; + wire [31:0] _zz_535_; + wire _zz_536_; + wire [0:0] _zz_537_; + wire [7:0] _zz_538_; + wire [31:0] _zz_539_; + wire [31:0] _zz_540_; + wire [31:0] _zz_541_; + wire _zz_542_; + wire [0:0] _zz_543_; + wire [1:0] _zz_544_; + wire _zz_545_; + wire _zz_546_; + wire _zz_547_; + wire decode_SRC_LESS_UNSIGNED; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; + wire execute_BRANCH_DO; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire [31:0] execute_BRANCH_CALC; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_8_; + wire `AluCtrlEnum_defaultEncoding_type _zz_9_; + wire `AluCtrlEnum_defaultEncoding_type _zz_10_; + wire decode_CSR_WRITE_OPCODE; + wire [51:0] memory_MUL_LOW; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12_; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_13_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_14_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_15_; + wire decode_PREDICTION_HAD_BRANCHED2; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire [33:0] execute_MUL_HL; + wire [31:0] execute_SHIFT_RIGHT; + wire decode_IS_RS2_SIGNED; + wire decode_MEMORY_MANAGMENT; + wire [31:0] memory_PC; + wire decode_IS_CSR; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_16_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_17_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_18_; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire decode_SRC2_FORCE_ZERO; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_19_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; + wire [33:0] execute_MUL_LH; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_24_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_26_; + wire [31:0] execute_MUL_LL; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire [51:0] _zz_27_; + wire [33:0] _zz_28_; + wire [33:0] _zz_29_; + wire [33:0] _zz_30_; + wire [31:0] _zz_31_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_32_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; + wire _zz_34_; + wire _zz_35_; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_36_; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] _zz_37_; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire _zz_38_; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_39_; + wire _zz_40_; + wire _zz_41_; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_42_; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_43_; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_44_; + wire [31:0] _zz_45_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_46_; + wire _zz_47_; + wire [31:0] _zz_48_; + wire [31:0] _zz_49_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_50_; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_51_; + wire [31:0] _zz_52_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_53_; + wire [31:0] _zz_54_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_55_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_56_; + wire [31:0] _zz_57_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; + wire [31:0] _zz_59_; + wire _zz_60_; + reg _zz_61_; + wire [31:0] _zz_62_; + wire [31:0] _zz_63_; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire `EnvCtrlEnum_defaultEncoding_type _zz_64_; + wire _zz_65_; + wire _zz_66_; + wire _zz_67_; + wire _zz_68_; + wire _zz_69_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_70_; + wire _zz_71_; + wire _zz_72_; + wire _zz_73_; + wire `AluCtrlEnum_defaultEncoding_type _zz_74_; + wire _zz_75_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_76_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_77_; + wire _zz_78_; + wire _zz_79_; + wire _zz_80_; + wire _zz_81_; + wire _zz_82_; + wire _zz_83_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_84_; + wire _zz_85_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_86_; + wire _zz_87_; + wire _zz_88_; + reg [31:0] _zz_89_; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire [1:0] _zz_90_; + wire execute_MEMORY_MANAGMENT; + wire [31:0] execute_RS2; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + reg _zz_91_; + reg _zz_92_; + reg _zz_93_; + wire [31:0] _zz_94_; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_95_; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_96_; + reg [31:0] _zz_97_; + wire [31:0] decode_PC; + wire [31:0] _zz_98_; + wire [31:0] _zz_99_; + wire [31:0] _zz_100_; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_fetcherflushIt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* syn_keep , keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + wire IBusCachedPlugin_redoBranch_valid; + wire [31:0] IBusCachedPlugin_redoBranch_payload; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_101_; + wire [4:0] _zz_102_; + wire _zz_103_; + wire _zz_104_; + wire _zz_105_; + wire _zz_106_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_107_; + wire _zz_108_; + wire _zz_109_; + wire _zz_110_; + wire _zz_111_; + reg _zz_112_; + wire _zz_113_; + reg _zz_114_; + reg [31:0] _zz_115_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + reg IBusCachedPlugin_injector_decodeRemoved; + wire _zz_116_; + reg [18:0] _zz_117_; + wire _zz_118_; + reg [10:0] _zz_119_; + wire _zz_120_; + reg [18:0] _zz_121_; + reg _zz_122_; + wire _zz_123_; + reg [10:0] _zz_124_; + wire _zz_125_; + reg [18:0] _zz_126_; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_127_; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire dataCache_1__io_mem_cmd_s2mPipe_valid; + wire dataCache_1__io_mem_cmd_s2mPipe_ready; + wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; + reg _zz_128_; + reg _zz_129_; + reg [31:0] _zz_130_; + reg [31:0] _zz_131_; + reg [3:0] _zz_132_; + reg [2:0] _zz_133_; + reg _zz_134_; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg _zz_135_; + reg _zz_136_; + reg [31:0] _zz_137_; + reg [31:0] _zz_138_; + reg [3:0] _zz_139_; + reg [2:0] _zz_140_; + reg _zz_141_; + wire [31:0] _zz_142_; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_143_; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_144_; + reg [31:0] _zz_145_; + wire _zz_146_; + reg [31:0] _zz_147_; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [31:0] _zz_148_; + wire _zz_149_; + wire _zz_150_; + wire _zz_151_; + wire _zz_152_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_153_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_154_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_155_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_156_; + wire `AluCtrlEnum_defaultEncoding_type _zz_157_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_158_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_159_; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_160_; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_161_; + reg [31:0] _zz_162_; + wire _zz_163_; + reg [19:0] _zz_164_; + wire _zz_165_; + reg [19:0] _zz_166_; + reg [31:0] _zz_167_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_168_; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_169_; + reg _zz_170_; + reg _zz_171_; + wire _zz_172_; + reg _zz_173_; + reg [4:0] _zz_174_; + reg [31:0] _zz_175_; + wire _zz_176_; + wire _zz_177_; + wire _zz_178_; + wire _zz_179_; + wire _zz_180_; + wire _zz_181_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_182_; + reg _zz_183_; + reg _zz_184_; + wire _zz_185_; + reg [19:0] _zz_186_; + wire _zz_187_; + reg [10:0] _zz_188_; + wire _zz_189_; + reg [18:0] _zz_190_; + reg _zz_191_; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_192_; + reg [19:0] _zz_193_; + wire _zz_194_; + reg [10:0] _zz_195_; + wire _zz_196_; + reg [18:0] _zz_197_; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_198_; + wire _zz_199_; + wire _zz_200_; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_201_; + wire _zz_202_; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_203_; + wire [32:0] _zz_204_; + wire [32:0] _zz_205_; + wire [31:0] _zz_206_; + wire _zz_207_; + wire _zz_208_; + reg [32:0] _zz_209_; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_210_; + wire [31:0] _zz_211_; + reg [31:0] execute_to_memory_MUL_LL; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg [33:0] execute_to_memory_MUL_LH; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_IS_CSR; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg [31:0] decode_to_execute_RS2; + reg [33:0] execute_to_memory_MUL_HL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg decode_to_execute_IS_RS1_SIGNED; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_CSR_READ_OPCODE; + reg [31:0] decode_to_execute_RS1; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg execute_to_memory_BRANCH_DO; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg [2:0] _zz_212_; + reg _zz_213_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_214_; + wire _zz_215_; + wire _zz_216_; + wire _zz_217_; + wire _zz_218_; + wire _zz_219_; + reg _zz_220_; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1__string; + reg [39:0] _zz_2__string; + reg [39:0] _zz_3__string; + reg [39:0] _zz_4__string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5__string; + reg [39:0] _zz_6__string; + reg [39:0] _zz_7__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_8__string; + reg [63:0] _zz_9__string; + reg [63:0] _zz_10__string; + reg [31:0] _zz_11__string; + reg [31:0] _zz_12__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_13__string; + reg [23:0] _zz_14__string; + reg [23:0] _zz_15__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_16__string; + reg [95:0] _zz_17__string; + reg [95:0] _zz_18__string; + reg [71:0] _zz_19__string; + reg [71:0] _zz_20__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_21__string; + reg [71:0] _zz_22__string; + reg [71:0] _zz_23__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_24__string; + reg [39:0] _zz_25__string; + reg [39:0] _zz_26__string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_32__string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_33__string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_36__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_39__string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_44__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_46__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_51__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_53__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_56__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_58__string; + reg [39:0] _zz_64__string; + reg [39:0] _zz_70__string; + reg [63:0] _zz_74__string; + reg [23:0] _zz_76__string; + reg [31:0] _zz_77__string; + reg [95:0] _zz_84__string; + reg [71:0] _zz_86__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_95__string; + reg [71:0] _zz_153__string; + reg [95:0] _zz_154__string; + reg [31:0] _zz_155__string; + reg [23:0] _zz_156__string; + reg [63:0] _zz_157__string; + reg [39:0] _zz_158__string; + reg [39:0] _zz_159__string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_243_ = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_244_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_245_ = 1'b1; + assign _zz_246_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_247_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_248_ = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_249_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_91_)); + assign _zz_250_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_92_)); + assign _zz_251_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_93_)); + assign _zz_252_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); + assign _zz_253_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_254_ = (! memory_DivPlugin_div_done); + assign _zz_255_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_256_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_257_ = writeBack_INSTRUCTION[29 : 28]; + assign _zz_258_ = (! IBusCachedPlugin_iBusRsp_readyForError); + assign _zz_259_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_260_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_261_ = (1'b0 || (! 1'b1)); + assign _zz_262_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_263_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_264_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_265_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_266_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_267_ = execute_INSTRUCTION[13 : 12]; + assign _zz_268_ = (! memory_arbitration_isStuck); + assign _zz_269_ = (iBus_cmd_valid || (_zz_212_ != (3'b000))); + assign _zz_270_ = (_zz_239_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); + assign _zz_271_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); + assign _zz_272_ = ((_zz_198_ && 1'b1) && (! 1'b0)); + assign _zz_273_ = ((_zz_199_ && 1'b1) && (! 1'b0)); + assign _zz_274_ = ((_zz_200_ && 1'b1) && (! 1'b0)); + assign _zz_275_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_276_ = execute_INSTRUCTION[13]; + assign _zz_277_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_278_ = (_zz_101_ - (5'b00001)); + assign _zz_279_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_280_ = {29'd0, _zz_279_}; + assign _zz_281_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_282_ = {{_zz_117_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_283_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_284_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_285_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_286_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_287_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_288_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_289_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); + assign _zz_290_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); + assign _zz_291_ = _zz_148_[0 : 0]; + assign _zz_292_ = _zz_148_[3 : 3]; + assign _zz_293_ = _zz_148_[6 : 6]; + assign _zz_294_ = _zz_148_[8 : 8]; + assign _zz_295_ = _zz_148_[9 : 9]; + assign _zz_296_ = _zz_148_[10 : 10]; + assign _zz_297_ = _zz_148_[11 : 11]; + assign _zz_298_ = _zz_148_[12 : 12]; + assign _zz_299_ = _zz_148_[17 : 17]; + assign _zz_300_ = _zz_148_[20 : 20]; + assign _zz_301_ = _zz_148_[21 : 21]; + assign _zz_302_ = _zz_148_[22 : 22]; + assign _zz_303_ = _zz_148_[25 : 25]; + assign _zz_304_ = _zz_148_[26 : 26]; + assign _zz_305_ = _zz_148_[27 : 27]; + assign _zz_306_ = _zz_148_[28 : 28]; + assign _zz_307_ = _zz_148_[29 : 29]; + assign _zz_308_ = execute_SRC_LESS; + assign _zz_309_ = (3'b100); + assign _zz_310_ = execute_INSTRUCTION[19 : 15]; + assign _zz_311_ = execute_INSTRUCTION[31 : 20]; + assign _zz_312_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_313_ = ($signed(_zz_314_) + $signed(_zz_317_)); + assign _zz_314_ = ($signed(_zz_315_) + $signed(_zz_316_)); + assign _zz_315_ = execute_SRC1; + assign _zz_316_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_317_ = (execute_SRC_USE_SUB_LESS ? _zz_318_ : _zz_319_); + assign _zz_318_ = (32'b00000000000000000000000000000001); + assign _zz_319_ = (32'b00000000000000000000000000000000); + assign _zz_320_ = ($signed(_zz_322_) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_321_ = _zz_320_[31 : 0]; + assign _zz_322_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_323_ = execute_INSTRUCTION[31 : 20]; + assign _zz_324_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_325_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_326_ = {_zz_186_,execute_INSTRUCTION[31 : 20]}; + assign _zz_327_ = {{_zz_188_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_328_ = {{_zz_190_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_329_ = execute_INSTRUCTION[31 : 20]; + assign _zz_330_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_331_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_332_ = (3'b100); + assign _zz_333_ = (_zz_201_ & (~ _zz_334_)); + assign _zz_334_ = (_zz_201_ - (2'b01)); + assign _zz_335_ = ($signed(_zz_336_) + $signed(_zz_341_)); + assign _zz_336_ = ($signed(_zz_337_) + $signed(_zz_339_)); + assign _zz_337_ = (52'b0000000000000000000000000000000000000000000000000000); + assign _zz_338_ = {1'b0,memory_MUL_LL}; + assign _zz_339_ = {{19{_zz_338_[32]}}, _zz_338_}; + assign _zz_340_ = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_341_ = {{2{_zz_340_[49]}}, _zz_340_}; + assign _zz_342_ = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_343_ = {{2{_zz_342_[49]}}, _zz_342_}; + assign _zz_344_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_345_ = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_346_ = writeBack_MUL_LOW[31 : 0]; + assign _zz_347_ = writeBack_MulPlugin_result[63 : 32]; + assign _zz_348_ = memory_DivPlugin_div_counter_willIncrement; + assign _zz_349_ = {5'd0, _zz_348_}; + assign _zz_350_ = {1'd0, memory_DivPlugin_rs2}; + assign _zz_351_ = {_zz_203_,(! _zz_205_[32])}; + assign _zz_352_ = _zz_205_[31:0]; + assign _zz_353_ = _zz_204_[31:0]; + assign _zz_354_ = _zz_355_; + assign _zz_355_ = _zz_356_; + assign _zz_356_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_206_) : _zz_206_)} + _zz_358_); + assign _zz_357_ = memory_DivPlugin_div_needRevert; + assign _zz_358_ = {32'd0, _zz_357_}; + assign _zz_359_ = _zz_208_; + assign _zz_360_ = {32'd0, _zz_359_}; + assign _zz_361_ = _zz_207_; + assign _zz_362_ = {31'd0, _zz_361_}; + assign _zz_363_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_364_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_365_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_366_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_367_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_368_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_369_ = (iBus_cmd_payload_address >>> 5); + assign _zz_370_ = 1'b1; + assign _zz_371_ = 1'b1; + assign _zz_372_ = {_zz_104_,{_zz_106_,_zz_105_}}; + assign _zz_373_ = decode_INSTRUCTION[31]; + assign _zz_374_ = decode_INSTRUCTION[31]; + assign _zz_375_ = decode_INSTRUCTION[7]; + assign _zz_376_ = (32'b00010000000000000011000001010000); + assign _zz_377_ = (decode_INSTRUCTION & (32'b00010000010000000011000001010000)); + assign _zz_378_ = (32'b00010000000000000000000001010000); + assign _zz_379_ = ((decode_INSTRUCTION & _zz_386_) == (32'b00000000000000000000000000000000)); + assign _zz_380_ = {(_zz_387_ == _zz_388_),{_zz_389_,_zz_390_}}; + assign _zz_381_ = ((decode_INSTRUCTION & _zz_391_) == (32'b00000000000000000001000000001000)); + assign _zz_382_ = (1'b0); + assign _zz_383_ = ({_zz_151_,{_zz_392_,_zz_393_}} != (5'b00000)); + assign _zz_384_ = ({_zz_394_,_zz_395_} != (2'b00)); + assign _zz_385_ = {(_zz_396_ != _zz_397_),{_zz_398_,{_zz_399_,_zz_400_}}}; + assign _zz_386_ = (32'b00000000000000000000000001000100); + assign _zz_387_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); + assign _zz_388_ = (32'b00000000000000000000000000000000); + assign _zz_389_ = ((decode_INSTRUCTION & _zz_401_) == (32'b00000000000000000010000000000000)); + assign _zz_390_ = ((decode_INSTRUCTION & _zz_402_) == (32'b00000000000000000001000000000000)); + assign _zz_391_ = (32'b00000000000000000101000001001000); + assign _zz_392_ = (_zz_403_ == _zz_404_); + assign _zz_393_ = {_zz_405_,{_zz_406_,_zz_407_}}; + assign _zz_394_ = (_zz_408_ == _zz_409_); + assign _zz_395_ = (_zz_410_ == _zz_411_); + assign _zz_396_ = (_zz_412_ == _zz_413_); + assign _zz_397_ = (1'b0); + assign _zz_398_ = (_zz_414_ != (1'b0)); + assign _zz_399_ = (_zz_415_ != _zz_416_); + assign _zz_400_ = {_zz_417_,{_zz_418_,_zz_419_}}; + assign _zz_401_ = (32'b00000000000000000110000000000100); + assign _zz_402_ = (32'b00000000000000000101000000000100); + assign _zz_403_ = (decode_INSTRUCTION & (32'b00000000000000000010000000110000)); + assign _zz_404_ = (32'b00000000000000000010000000010000); + assign _zz_405_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000110000)) == (32'b00000000000000000000000000010000)); + assign _zz_406_ = ((decode_INSTRUCTION & _zz_420_) == (32'b00000000000000000010000000100000)); + assign _zz_407_ = ((decode_INSTRUCTION & _zz_421_) == (32'b00000000000000000000000000100000)); + assign _zz_408_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); + assign _zz_409_ = (32'b00000000000000000001000001010000); + assign _zz_410_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); + assign _zz_411_ = (32'b00000000000000000010000001010000); + assign _zz_412_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); + assign _zz_413_ = (32'b00000000000000000000000000100000); + assign _zz_414_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)); + assign _zz_415_ = ((decode_INSTRUCTION & _zz_422_) == (32'b00000000000000000010000000000000)); + assign _zz_416_ = (1'b0); + assign _zz_417_ = ((_zz_423_ == _zz_424_) != (1'b0)); + assign _zz_418_ = (_zz_152_ != (1'b0)); + assign _zz_419_ = {(_zz_425_ != _zz_426_),{_zz_427_,{_zz_428_,_zz_429_}}}; + assign _zz_420_ = (32'b00000010000000000010000001100000); + assign _zz_421_ = (32'b00000010000000000011000000100000); + assign _zz_422_ = (32'b00000000000000000011000000000000); + assign _zz_423_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_424_ = (32'b00000000000000000000000000100100); + assign _zz_425_ = {((decode_INSTRUCTION & _zz_430_) == (32'b00000000000000000000000001000000)),{_zz_151_,{_zz_431_,{_zz_432_,_zz_433_}}}}; + assign _zz_426_ = (5'b00000); + assign _zz_427_ = (((decode_INSTRUCTION & _zz_434_) == (32'b00000000000000000100000000010000)) != (1'b0)); + assign _zz_428_ = ((_zz_435_ == _zz_436_) != (1'b0)); + assign _zz_429_ = {(_zz_152_ != (1'b0)),{(_zz_437_ != _zz_438_),{_zz_439_,{_zz_440_,_zz_441_}}}}; + assign _zz_430_ = (32'b00000000000000000000000001000000); + assign _zz_431_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000100000)) == (32'b00000000000000000100000000100000)); + assign _zz_432_ = ((decode_INSTRUCTION & _zz_442_) == (32'b00000000000000000000000000010000)); + assign _zz_433_ = ((decode_INSTRUCTION & _zz_443_) == (32'b00000000000000000000000000100000)); + assign _zz_434_ = (32'b00000000000000000100000000010100); + assign _zz_435_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); + assign _zz_436_ = (32'b00000000000000000010000000010000); + assign _zz_437_ = {_zz_151_,(_zz_444_ == _zz_445_)}; + assign _zz_438_ = (2'b00); + assign _zz_439_ = ({_zz_151_,_zz_446_} != (2'b00)); + assign _zz_440_ = ({_zz_447_,_zz_448_} != (2'b00)); + assign _zz_441_ = {(_zz_449_ != _zz_450_),{_zz_451_,{_zz_452_,_zz_453_}}}; + assign _zz_442_ = (32'b00000000000000000000000000110000); + assign _zz_443_ = (32'b00000010000000000000000000100000); + assign _zz_444_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); + assign _zz_445_ = (32'b00000000000000000000000000100000); + assign _zz_446_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); + assign _zz_447_ = _zz_150_; + assign _zz_448_ = ((decode_INSTRUCTION & _zz_454_) == (32'b00000000000000000000000000000100)); + assign _zz_449_ = ((decode_INSTRUCTION & _zz_455_) == (32'b00000000000000000000000001000000)); + assign _zz_450_ = (1'b0); + assign _zz_451_ = ({_zz_150_,{_zz_456_,_zz_457_}} != (6'b000000)); + assign _zz_452_ = ({_zz_458_,_zz_459_} != (2'b00)); + assign _zz_453_ = {(_zz_460_ != _zz_461_),{_zz_462_,{_zz_463_,_zz_464_}}}; + assign _zz_454_ = (32'b00000000000000000000000000011100); + assign _zz_455_ = (32'b00000000000000000000000001011000); + assign _zz_456_ = ((decode_INSTRUCTION & _zz_465_) == (32'b00000000000000000001000000010000)); + assign _zz_457_ = {(_zz_466_ == _zz_467_),{_zz_468_,{_zz_469_,_zz_470_}}}; + assign _zz_458_ = ((decode_INSTRUCTION & _zz_471_) == (32'b00000000000000000010000000000000)); + assign _zz_459_ = ((decode_INSTRUCTION & _zz_472_) == (32'b00000000000000000001000000000000)); + assign _zz_460_ = ((decode_INSTRUCTION & _zz_473_) == (32'b00000010000000000100000000100000)); + assign _zz_461_ = (1'b0); + assign _zz_462_ = ((_zz_474_ == _zz_475_) != (1'b0)); + assign _zz_463_ = ({_zz_476_,_zz_477_} != (3'b000)); + assign _zz_464_ = {(_zz_478_ != _zz_479_),{_zz_480_,{_zz_481_,_zz_482_}}}; + assign _zz_465_ = (32'b00000000000000000001000000010000); + assign _zz_466_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); + assign _zz_467_ = (32'b00000000000000000010000000010000); + assign _zz_468_ = ((decode_INSTRUCTION & _zz_483_) == (32'b00000000000000000000000000010000)); + assign _zz_469_ = (_zz_484_ == _zz_485_); + assign _zz_470_ = (_zz_486_ == _zz_487_); + assign _zz_471_ = (32'b00000000000000000010000000010000); + assign _zz_472_ = (32'b00000000000000000101000000000000); + assign _zz_473_ = (32'b00000010000000000100000001100100); + assign _zz_474_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_475_ = (32'b00000000000000000000000000000000); + assign _zz_476_ = (_zz_488_ == _zz_489_); + assign _zz_477_ = {_zz_490_,_zz_491_}; + assign _zz_478_ = {_zz_492_,{_zz_493_,_zz_494_}}; + assign _zz_479_ = (3'b000); + assign _zz_480_ = (_zz_495_ != (1'b0)); + assign _zz_481_ = (_zz_496_ != _zz_497_); + assign _zz_482_ = {_zz_498_,{_zz_499_,_zz_500_}}; + assign _zz_483_ = (32'b00000000000000000000000001010000); + assign _zz_484_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); + assign _zz_485_ = (32'b00000000000000000000000000000100); + assign _zz_486_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); + assign _zz_487_ = (32'b00000000000000000000000000000000); + assign _zz_488_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_489_ = (32'b00000000000000000000000001000000); + assign _zz_490_ = ((decode_INSTRUCTION & _zz_501_) == (32'b00000000000000000010000000010000)); + assign _zz_491_ = ((decode_INSTRUCTION & _zz_502_) == (32'b01000000000000000000000000110000)); + assign _zz_492_ = ((decode_INSTRUCTION & _zz_503_) == (32'b00000000000000000000000001000000)); + assign _zz_493_ = (_zz_504_ == _zz_505_); + assign _zz_494_ = (_zz_506_ == _zz_507_); + assign _zz_495_ = ((decode_INSTRUCTION & _zz_508_) == (32'b00000000000000000100000000001000)); + assign _zz_496_ = {_zz_509_,_zz_149_}; + assign _zz_497_ = (2'b00); + assign _zz_498_ = ({_zz_510_,_zz_511_} != (2'b00)); + assign _zz_499_ = (_zz_512_ != _zz_513_); + assign _zz_500_ = {_zz_514_,{_zz_515_,_zz_516_}}; + assign _zz_501_ = (32'b00000000000000000010000000010100); + assign _zz_502_ = (32'b01000000000000000000000000110100); + assign _zz_503_ = (32'b00000000000000000000000001010000); + assign _zz_504_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); + assign _zz_505_ = (32'b00000000000000000000000000000000); + assign _zz_506_ = (decode_INSTRUCTION & (32'b00000000010000000011000001000000)); + assign _zz_507_ = (32'b00000000000000000000000001000000); + assign _zz_508_ = (32'b00000000000000000100000001001000); + assign _zz_509_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); + assign _zz_510_ = ((decode_INSTRUCTION & _zz_517_) == (32'b00000000000000000000000000000100)); + assign _zz_511_ = _zz_149_; + assign _zz_512_ = {(_zz_518_ == _zz_519_),(_zz_520_ == _zz_521_)}; + assign _zz_513_ = (2'b00); + assign _zz_514_ = ({_zz_522_,_zz_523_} != (2'b00)); + assign _zz_515_ = ({_zz_524_,_zz_525_} != (3'b000)); + assign _zz_516_ = (_zz_526_ != (1'b0)); + assign _zz_517_ = (32'b00000000000000000000000001000100); + assign _zz_518_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); + assign _zz_519_ = (32'b00000000000000000000000000100000); + assign _zz_520_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_521_ = (32'b00000000000000000000000000100000); + assign _zz_522_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000110100)) == (32'b00000000000000000101000000010000)); + assign _zz_523_ = ((decode_INSTRUCTION & (32'b00000010000000000111000001100100)) == (32'b00000000000000000101000000100000)); + assign _zz_524_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); + assign _zz_525_ = {((decode_INSTRUCTION & (32'b00000000000000000111000000110100)) == (32'b00000000000000000001000000010000)),((decode_INSTRUCTION & (32'b00000010000000000111000001010100)) == (32'b00000000000000000001000000010000))}; + assign _zz_526_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001110100)) == (32'b00000010000000000000000000110000)); + assign _zz_527_ = (32'b00000000000000000001000001111111); + assign _zz_528_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_529_ = (32'b00000000000000000010000001110011); + assign _zz_530_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_531_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_532_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_533_) == (32'b00000000000000000000000000000011)),{(_zz_534_ == _zz_535_),{_zz_536_,{_zz_537_,_zz_538_}}}}}}; + assign _zz_533_ = (32'b00000000000000000101000001011111); + assign _zz_534_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_535_ = (32'b00000000000000000000000001100011); + assign _zz_536_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_537_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_538_ = {((decode_INSTRUCTION & (32'b00000001111100000111000001111111)) == (32'b00000000000000000101000000001111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_539_) == (32'b00000000000000000001000000010011)),{(_zz_540_ == _zz_541_),{_zz_542_,{_zz_543_,_zz_544_}}}}}}; + assign _zz_539_ = (32'b11111100000000000011000001111111); + assign _zz_540_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_541_ = (32'b00000000000000000101000000110011); + assign _zz_542_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_543_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); + assign _zz_544_ = {((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)),((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011))}; + assign _zz_545_ = execute_INSTRUCTION[31]; + assign _zz_546_ = execute_INSTRUCTION[31]; + assign _zz_547_ = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_61_) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_370_) begin + _zz_240_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_371_) begin + _zz_241_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush(_zz_221_), + .io_cpu_prefetch_isValid(_zz_222_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_223_), + .io_cpu_fetch_isStuck(_zz_224_), + .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_225_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), + .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), + .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), + .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), + .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), + .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), + .io_cpu_decode_isValid(_zz_226_), + .io_cpu_decode_isStuck(_zz_227_), + .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), + .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), + .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), + .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), + .io_cpu_decode_isUser(_zz_228_), + .io_cpu_fill_valid(_zz_229_), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + DataCache dataCache_1_ ( + .io_cpu_execute_isValid(_zz_230_), + .io_cpu_execute_address(_zz_231_), + .io_cpu_execute_args_wr(execute_MEMORY_WR), + .io_cpu_execute_args_data(_zz_143_), + .io_cpu_execute_args_size(execute_DBusCachedPlugin_size), + .io_cpu_memory_isValid(_zz_232_), + .io_cpu_memory_isStuck(memory_arbitration_isStuck), + .io_cpu_memory_isRemoved(memory_arbitration_removeIt), + .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), + .io_cpu_memory_address(_zz_233_), + .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), + .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), + .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), + .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), + .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_234_), + .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), + .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), + .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), + .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), + .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), + .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), + .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), + .io_cpu_writeBack_isValid(_zz_235_), + .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), + .io_cpu_writeBack_isUser(_zz_236_), + .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), + .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), + .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), + .io_cpu_writeBack_address(_zz_237_), + .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), + .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), + .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), + .io_cpu_redo(dataCache_1__io_cpu_redo), + .io_cpu_flush_valid(_zz_238_), + .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), + .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), + .io_mem_cmd_ready(_zz_239_), + .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), + .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), + .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), + .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), + .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), + .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), + .io_mem_rsp_valid(dBus_rsp_valid), + .io_mem_rsp_payload_data(dBus_rsp_payload_data), + .io_mem_rsp_payload_error(dBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_372_) + 3'b000 : begin + _zz_242_ = DBusCachedPlugin_redoBranch_payload; + end + 3'b001 : begin + _zz_242_ = CsrPlugin_jumpInterface_payload; + end + 3'b010 : begin + _zz_242_ = BranchPlugin_jumpInterface_payload; + end + 3'b011 : begin + _zz_242_ = IBusCachedPlugin_redoBranch_payload; + end + default : begin + _zz_242_ = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL"; + default : _zz_1__string = "?????"; + endcase + end + always @(*) begin + case(_zz_2_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL"; + default : _zz_2__string = "?????"; + endcase + end + always @(*) begin + case(_zz_3_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL"; + default : _zz_3__string = "?????"; + endcase + end + always @(*) begin + case(_zz_4_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL"; + default : _zz_4__string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL"; + default : _zz_5__string = "?????"; + endcase + end + always @(*) begin + case(_zz_6_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL"; + default : _zz_6__string = "?????"; + endcase + end + always @(*) begin + case(_zz_7_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; + default : _zz_7__string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_8_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_8__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_8__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_8__string = "BITWISE "; + default : _zz_8__string = "????????"; + endcase + end + always @(*) begin + case(_zz_9_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE "; + default : _zz_9__string = "????????"; + endcase + end + always @(*) begin + case(_zz_10_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10__string = "BITWISE "; + default : _zz_10__string = "????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR"; + default : _zz_11__string = "????"; + endcase + end + always @(*) begin + case(_zz_12_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12__string = "JALR"; + default : _zz_12__string = "????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_13_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_13__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_13__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_13__string = "PC "; + default : _zz_13__string = "???"; + endcase + end + always @(*) begin + case(_zz_14_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_14__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_14__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_14__string = "PC "; + default : _zz_14__string = "???"; + endcase + end + always @(*) begin + case(_zz_15_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_15__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_15__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_15__string = "PC "; + default : _zz_15__string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_16_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_16__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_16__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_16__string = "URS1 "; + default : _zz_16__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_17_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_17__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_17__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_17__string = "URS1 "; + default : _zz_17__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_18_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_18__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_18__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_18__string = "URS1 "; + default : _zz_18__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_19_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_19__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_19__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_19__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_19__string = "SRA_1 "; + default : _zz_19__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_20_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; + default : _zz_20__string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_21_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; + default : _zz_21__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_22_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; + default : _zz_22__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_23_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 "; + default : _zz_23__string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_24_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_24__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_24__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_24__string = "AND_1"; + default : _zz_24__string = "?????"; + endcase + end + always @(*) begin + case(_zz_25_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25__string = "AND_1"; + default : _zz_25__string = "?????"; + endcase + end + always @(*) begin + case(_zz_26_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_26__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_26__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_26__string = "AND_1"; + default : _zz_26__string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_32__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_32__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32__string = "ECALL"; + default : _zz_32__string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33__string = "ECALL"; + default : _zz_33__string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_36_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_36__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_36__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_36__string = "ECALL"; + default : _zz_36__string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_39_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_39__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_39__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_39__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_39__string = "JALR"; + default : _zz_39__string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_44_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_44__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_44__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_44__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_44__string = "SRA_1 "; + default : _zz_44__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_46_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46__string = "SRA_1 "; + default : _zz_46__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_51_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_51__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_51__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_51__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_51__string = "PC "; + default : _zz_51__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_53_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_53__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_53__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_53__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_53__string = "URS1 "; + default : _zz_53__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; + default : _zz_56__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_58_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; + default : _zz_58__string = "?????"; + endcase + end + always @(*) begin + case(_zz_64_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_64__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_64__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_64__string = "ECALL"; + default : _zz_64__string = "?????"; + endcase + end + always @(*) begin + case(_zz_70_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_70__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_70__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_70__string = "AND_1"; + default : _zz_70__string = "?????"; + endcase + end + always @(*) begin + case(_zz_74_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_74__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_74__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_74__string = "BITWISE "; + default : _zz_74__string = "????????"; + endcase + end + always @(*) begin + case(_zz_76_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_76__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_76__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_76__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_76__string = "PC "; + default : _zz_76__string = "???"; + endcase + end + always @(*) begin + case(_zz_77_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_77__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_77__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_77__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_77__string = "JALR"; + default : _zz_77__string = "????"; + endcase + end + always @(*) begin + case(_zz_84_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_84__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_84__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_84__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_84__string = "URS1 "; + default : _zz_84__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_86_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_86__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_86__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_86__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_86__string = "SRA_1 "; + default : _zz_86__string = "?????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_95_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR"; + default : _zz_95__string = "????"; + endcase + end + always @(*) begin + case(_zz_153_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_153__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_153__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_153__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_153__string = "SRA_1 "; + default : _zz_153__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_154_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_154__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_154__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_154__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_154__string = "URS1 "; + default : _zz_154__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_155_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_155__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_155__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_155__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_155__string = "JALR"; + default : _zz_155__string = "????"; + endcase + end + always @(*) begin + case(_zz_156_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_156__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_156__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_156__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_156__string = "PC "; + default : _zz_156__string = "???"; + endcase + end + always @(*) begin + case(_zz_157_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_157__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_157__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_157__string = "BITWISE "; + default : _zz_157__string = "????????"; + endcase + end + always @(*) begin + case(_zz_158_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_158__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_158__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_158__string = "AND_1"; + default : _zz_158__string = "?????"; + endcase + end + always @(*) begin + case(_zz_159_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_159__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_159__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_159__string = "ECALL"; + default : _zz_159__string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + `endif + + assign decode_SRC_LESS_UNSIGNED = _zz_79_; + assign _zz_1_ = _zz_2_; + assign _zz_3_ = _zz_4_; + assign decode_ENV_CTRL = _zz_5_; + assign _zz_6_ = _zz_7_; + assign execute_BRANCH_DO = _zz_38_; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_69_; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_73_; + assign execute_BRANCH_CALC = _zz_37_; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_98_; + assign execute_REGFILE_WRITE_DATA = _zz_57_; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_90_; + assign decode_CSR_READ_OPCODE = _zz_34_; + assign decode_ALU_CTRL = _zz_8_; + assign _zz_9_ = _zz_10_; + assign decode_CSR_WRITE_OPCODE = _zz_35_; + assign memory_MUL_LOW = _zz_27_; + assign _zz_11_ = _zz_12_; + assign decode_IS_RS1_SIGNED = _zz_75_; + assign decode_IS_DIV = _zz_80_; + assign decode_SRC2_CTRL = _zz_13_; + assign _zz_14_ = _zz_15_; + assign decode_PREDICTION_HAD_BRANCHED2 = _zz_41_; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_87_; + assign execute_MUL_HL = _zz_29_; + assign execute_SHIFT_RIGHT = _zz_45_; + assign decode_IS_RS2_SIGNED = _zz_72_; + assign decode_MEMORY_MANAGMENT = _zz_83_; + assign memory_PC = execute_to_memory_PC; + assign decode_IS_CSR = _zz_68_; + assign decode_SRC1_CTRL = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_67_; + assign decode_SRC2_FORCE_ZERO = _zz_55_; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = _zz_28_; + assign _zz_19_ = _zz_20_; + assign decode_SHIFT_CTRL = _zz_21_; + assign _zz_22_ = _zz_23_; + assign execute_MUL_LH = _zz_30_; + assign decode_ALU_BITWISE_CTRL = _zz_24_; + assign _zz_25_ = _zz_26_; + assign execute_MUL_LL = _zz_31_; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_32_; + assign execute_ENV_CTRL = _zz_33_; + assign writeBack_ENV_CTRL = _zz_36_; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_40_; + assign execute_BRANCH_CTRL = _zz_39_; + assign decode_RS2_USE = _zz_85_; + assign decode_RS1_USE = _zz_65_; + always @ (*) begin + _zz_42_ = execute_REGFILE_WRITE_DATA; + if(_zz_243_)begin + _zz_42_ = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = _zz_62_; + if(_zz_173_)begin + if((_zz_174_ == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_175_; + end + end + if(_zz_244_)begin + if(_zz_245_)begin + if(_zz_177_)begin + decode_RS2 = _zz_89_; + end + end + end + if(_zz_246_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_179_)begin + decode_RS2 = _zz_43_; + end + end + end + if(_zz_247_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_181_)begin + decode_RS2 = _zz_42_; + end + end + end + end + + always @ (*) begin + decode_RS1 = _zz_63_; + if(_zz_173_)begin + if((_zz_174_ == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_175_; + end + end + if(_zz_244_)begin + if(_zz_245_)begin + if(_zz_176_)begin + decode_RS1 = _zz_89_; + end + end + end + if(_zz_246_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_178_)begin + decode_RS1 = _zz_43_; + end + end + end + if(_zz_247_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_180_)begin + decode_RS1 = _zz_42_; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_43_ = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_43_ = _zz_169_; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_43_ = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(_zz_248_)begin + _zz_43_ = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_44_; + assign execute_SHIFT_CTRL = _zz_46_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_50_ = execute_PC; + assign execute_SRC2_CTRL = _zz_51_; + assign execute_SRC1_CTRL = _zz_53_; + assign decode_SRC_USE_SUB_LESS = _zz_82_; + assign decode_SRC_ADD_ZERO = _zz_71_; + assign execute_SRC_ADD_SUB = _zz_49_; + assign execute_SRC_LESS = _zz_47_; + assign execute_ALU_CTRL = _zz_56_; + assign execute_SRC2 = _zz_52_; + assign execute_SRC1 = _zz_54_; + assign execute_ALU_BITWISE_CTRL = _zz_58_; + assign _zz_59_ = writeBack_INSTRUCTION; + assign _zz_60_ = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_61_ = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_61_ = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = _zz_94_; + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_78_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = _zz_88_; + assign decode_INSTRUCTION_READY = 1'b1; + always @ (*) begin + _zz_89_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_89_ = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_277_) + 2'b00 : begin + _zz_89_ = _zz_346_; + end + default : begin + _zz_89_ = _zz_347_; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = _zz_48_; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_81_; + assign decode_FLUSH_ALL = _zz_66_; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = _zz_91_; + if(_zz_249_)begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + end + end + + always @ (*) begin + _zz_91_ = _zz_92_; + if(_zz_250_)begin + _zz_91_ = 1'b1; + end + end + + always @ (*) begin + _zz_92_ = _zz_93_; + if(_zz_251_)begin + _zz_92_ = 1'b1; + end + end + + always @ (*) begin + _zz_93_ = 1'b0; + if(_zz_252_)begin + _zz_93_ = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_95_; + assign decode_INSTRUCTION = _zz_99_; + always @ (*) begin + _zz_96_ = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_96_ = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_97_ = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_97_ = IBusCachedPlugin_predictionJumpInterface_payload; + end + if(IBusCachedPlugin_redoBranch_valid)begin + _zz_97_ = IBusCachedPlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_100_; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_170_ || _zz_171_)))begin + decode_arbitration_haltByOther = 1'b1; + end + if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin + decode_arbitration_haltByOther = decode_arbitration_isValid; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_253_)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_redoBranch_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_253_)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if((_zz_238_ && (! dataCache_1__io_cpu_flush_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_243_)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(_zz_248_)begin + if(_zz_254_)begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1__io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_255_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_256_)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_255_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_256_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetcherflushIt = 1'b0; + if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin + IBusCachedPlugin_fetcherflushIt = 1'b1; + end + if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin + IBusCachedPlugin_fetcherflushIt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_255_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_256_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(_zz_255_)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + end + if(_zz_256_)begin + case(_zz_257_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); + assign _zz_101_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; + assign _zz_102_ = (_zz_101_ & (~ _zz_278_)); + assign _zz_103_ = _zz_102_[3]; + assign _zz_104_ = _zz_102_[4]; + assign _zz_105_ = (_zz_102_[1] || _zz_103_); + assign _zz_106_ = (_zz_102_[2] || _zz_103_); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_242_; + always @ (*) begin + IBusCachedPlugin_fetchPc_corrected = 1'b0; + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_corrected = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_280_); + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_107_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_107_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_107_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_108_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_108_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_108_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_109_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_109_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_110_; + assign _zz_110_ = ((1'b0 && (! _zz_111_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_111_ = _zz_112_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_111_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_113_ = _zz_114_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_113_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_115_; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + assign _zz_100_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_99_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_98_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign _zz_116_ = _zz_281_[11]; + always @ (*) begin + _zz_117_[18] = _zz_116_; + _zz_117_[17] = _zz_116_; + _zz_117_[16] = _zz_116_; + _zz_117_[15] = _zz_116_; + _zz_117_[14] = _zz_116_; + _zz_117_[13] = _zz_116_; + _zz_117_[12] = _zz_116_; + _zz_117_[11] = _zz_116_; + _zz_117_[10] = _zz_116_; + _zz_117_[9] = _zz_116_; + _zz_117_[8] = _zz_116_; + _zz_117_[7] = _zz_116_; + _zz_117_[6] = _zz_116_; + _zz_117_[5] = _zz_116_; + _zz_117_[4] = _zz_116_; + _zz_117_[3] = _zz_116_; + _zz_117_[2] = _zz_116_; + _zz_117_[1] = _zz_116_; + _zz_117_[0] = _zz_116_; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_282_[31])); + if(_zz_122_)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_118_ = _zz_283_[19]; + always @ (*) begin + _zz_119_[10] = _zz_118_; + _zz_119_[9] = _zz_118_; + _zz_119_[8] = _zz_118_; + _zz_119_[7] = _zz_118_; + _zz_119_[6] = _zz_118_; + _zz_119_[5] = _zz_118_; + _zz_119_[4] = _zz_118_; + _zz_119_[3] = _zz_118_; + _zz_119_[2] = _zz_118_; + _zz_119_[1] = _zz_118_; + _zz_119_[0] = _zz_118_; + end + + assign _zz_120_ = _zz_284_[11]; + always @ (*) begin + _zz_121_[18] = _zz_120_; + _zz_121_[17] = _zz_120_; + _zz_121_[16] = _zz_120_; + _zz_121_[15] = _zz_120_; + _zz_121_[14] = _zz_120_; + _zz_121_[13] = _zz_120_; + _zz_121_[12] = _zz_120_; + _zz_121_[11] = _zz_120_; + _zz_121_[10] = _zz_120_; + _zz_121_[9] = _zz_120_; + _zz_121_[8] = _zz_120_; + _zz_121_[7] = _zz_120_; + _zz_121_[6] = _zz_120_; + _zz_121_[5] = _zz_120_; + _zz_121_[4] = _zz_120_; + _zz_121_[3] = _zz_120_; + _zz_121_[2] = _zz_120_; + _zz_121_[1] = _zz_120_; + _zz_121_[0] = _zz_120_; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_122_ = _zz_285_[1]; + end + default : begin + _zz_122_ = _zz_286_[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_123_ = _zz_287_[19]; + always @ (*) begin + _zz_124_[10] = _zz_123_; + _zz_124_[9] = _zz_123_; + _zz_124_[8] = _zz_123_; + _zz_124_[7] = _zz_123_; + _zz_124_[6] = _zz_123_; + _zz_124_[5] = _zz_123_; + _zz_124_[4] = _zz_123_; + _zz_124_[3] = _zz_123_; + _zz_124_[2] = _zz_123_; + _zz_124_[1] = _zz_123_; + _zz_124_[0] = _zz_123_; + end + + assign _zz_125_ = _zz_288_[11]; + always @ (*) begin + _zz_126_[18] = _zz_125_; + _zz_126_[17] = _zz_125_; + _zz_126_[16] = _zz_125_; + _zz_126_[15] = _zz_125_; + _zz_126_[14] = _zz_125_; + _zz_126_[13] = _zz_125_; + _zz_126_[12] = _zz_125_; + _zz_126_[11] = _zz_125_; + _zz_126_[10] = _zz_125_; + _zz_126_[9] = _zz_125_; + _zz_126_[8] = _zz_125_; + _zz_126_[7] = _zz_125_; + _zz_126_[6] = _zz_125_; + _zz_126_[5] = _zz_125_; + _zz_126_[4] = _zz_125_; + _zz_126_[3] = _zz_125_; + _zz_126_[2] = _zz_125_; + _zz_126_[1] = _zz_125_; + _zz_126_[0] = _zz_125_; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_124_,{{{_zz_373_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_126_,{{{_zz_374_,_zz_375_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_222_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_225_ = (32'b00000000000000000000000000000000); + assign _zz_223_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_224_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_226_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_227_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_228_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_94_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_252_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_250_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_258_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + end + end + + always @ (*) begin + _zz_229_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_250_)begin + _zz_229_ = 1'b1; + end + if(_zz_258_)begin + _zz_229_ = 1'b0; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_251_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_249_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(_zz_251_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + if(_zz_249_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; + assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; + assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + assign _zz_221_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_128_); + assign _zz_239_ = (! _zz_128_); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_128_ ? _zz_129_ : dataCache_1__io_mem_cmd_payload_wr); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_128_ ? _zz_130_ : dataCache_1__io_mem_cmd_payload_address); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_128_ ? _zz_131_ : dataCache_1__io_mem_cmd_payload_data); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_128_ ? _zz_132_ : dataCache_1__io_mem_cmd_payload_mask); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_128_ ? _zz_133_ : dataCache_1__io_mem_cmd_payload_length); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_128_ ? _zz_134_ : dataCache_1__io_mem_cmd_payload_last); + assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_135_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_136_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_137_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_138_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_139_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_140_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_141_; + assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_230_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_231_ = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_143_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_143_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_143_ = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_238_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_90_ = _zz_231_[1 : 0]; + assign _zz_232_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_233_ = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + always @ (*) begin + _zz_234_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin + _zz_234_ = 1'b1; + end + end + + assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; + assign _zz_235_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_236_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_237_ = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_259_)begin + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_259_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); + if(_zz_259_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_289_}; + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_290_}; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_144_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_145_[31] = _zz_144_; + _zz_145_[30] = _zz_144_; + _zz_145_[29] = _zz_144_; + _zz_145_[28] = _zz_144_; + _zz_145_[27] = _zz_144_; + _zz_145_[26] = _zz_144_; + _zz_145_[25] = _zz_144_; + _zz_145_[24] = _zz_144_; + _zz_145_[23] = _zz_144_; + _zz_145_[22] = _zz_144_; + _zz_145_[21] = _zz_144_; + _zz_145_[20] = _zz_144_; + _zz_145_[19] = _zz_144_; + _zz_145_[18] = _zz_144_; + _zz_145_[17] = _zz_144_; + _zz_145_[16] = _zz_144_; + _zz_145_[15] = _zz_144_; + _zz_145_[14] = _zz_144_; + _zz_145_[13] = _zz_144_; + _zz_145_[12] = _zz_144_; + _zz_145_[11] = _zz_144_; + _zz_145_[10] = _zz_144_; + _zz_145_[9] = _zz_144_; + _zz_145_[8] = _zz_144_; + _zz_145_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_146_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_147_[31] = _zz_146_; + _zz_147_[30] = _zz_146_; + _zz_147_[29] = _zz_146_; + _zz_147_[28] = _zz_146_; + _zz_147_[27] = _zz_146_; + _zz_147_[26] = _zz_146_; + _zz_147_[25] = _zz_146_; + _zz_147_[24] = _zz_146_; + _zz_147_[23] = _zz_146_; + _zz_147_[22] = _zz_146_; + _zz_147_[21] = _zz_146_; + _zz_147_[20] = _zz_146_; + _zz_147_[19] = _zz_146_; + _zz_147_[18] = _zz_146_; + _zz_147_[17] = _zz_146_; + _zz_147_[16] = _zz_146_; + _zz_147_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_275_) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_145_; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_147_; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_149_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_150_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_151_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_152_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_148_ = {(((decode_INSTRUCTION & _zz_376_) == (32'b00000000000000000000000001010000)) != (1'b0)),{((_zz_377_ == _zz_378_) != (1'b0)),{({_zz_379_,_zz_380_} != (4'b0000)),{(_zz_381_ != _zz_382_),{_zz_383_,{_zz_384_,_zz_385_}}}}}}; + assign _zz_88_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_527_) == (32'b00000000000000000001000001110011)),{(_zz_528_ == _zz_529_),{_zz_530_,{_zz_531_,_zz_532_}}}}}}} != (21'b000000000000000000000)); + assign _zz_87_ = _zz_291_[0]; + assign _zz_153_ = _zz_148_[2 : 1]; + assign _zz_86_ = _zz_153_; + assign _zz_85_ = _zz_292_[0]; + assign _zz_154_ = _zz_148_[5 : 4]; + assign _zz_84_ = _zz_154_; + assign _zz_83_ = _zz_293_[0]; + assign _zz_82_ = _zz_294_[0]; + assign _zz_81_ = _zz_295_[0]; + assign _zz_80_ = _zz_296_[0]; + assign _zz_79_ = _zz_297_[0]; + assign _zz_78_ = _zz_298_[0]; + assign _zz_155_ = _zz_148_[14 : 13]; + assign _zz_77_ = _zz_155_; + assign _zz_156_ = _zz_148_[16 : 15]; + assign _zz_76_ = _zz_156_; + assign _zz_75_ = _zz_299_[0]; + assign _zz_157_ = _zz_148_[19 : 18]; + assign _zz_74_ = _zz_157_; + assign _zz_73_ = _zz_300_[0]; + assign _zz_72_ = _zz_301_[0]; + assign _zz_71_ = _zz_302_[0]; + assign _zz_158_ = _zz_148_[24 : 23]; + assign _zz_70_ = _zz_158_; + assign _zz_69_ = _zz_303_[0]; + assign _zz_68_ = _zz_304_[0]; + assign _zz_67_ = _zz_305_[0]; + assign _zz_66_ = _zz_306_[0]; + assign _zz_65_ = _zz_307_[0]; + assign _zz_159_ = _zz_148_[31 : 30]; + assign _zz_64_ = _zz_159_; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_240_; + assign decode_RegFilePlugin_rs2Data = _zz_241_; + assign _zz_63_ = decode_RegFilePlugin_rs1Data; + assign _zz_62_ = decode_RegFilePlugin_rs2Data; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_60_ && writeBack_arbitration_isFiring); + if(_zz_160_)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + assign lastStageRegFileWrite_payload_address = _zz_59_[11 : 7]; + assign lastStageRegFileWrite_payload_data = _zz_89_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_161_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_161_ = {31'd0, _zz_308_}; + end + default : begin + _zz_161_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_57_ = _zz_161_; + assign _zz_55_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_162_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_162_ = {29'd0, _zz_309_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_162_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_162_ = {27'd0, _zz_310_}; + end + endcase + end + + assign _zz_54_ = _zz_162_; + assign _zz_163_ = _zz_311_[11]; + always @ (*) begin + _zz_164_[19] = _zz_163_; + _zz_164_[18] = _zz_163_; + _zz_164_[17] = _zz_163_; + _zz_164_[16] = _zz_163_; + _zz_164_[15] = _zz_163_; + _zz_164_[14] = _zz_163_; + _zz_164_[13] = _zz_163_; + _zz_164_[12] = _zz_163_; + _zz_164_[11] = _zz_163_; + _zz_164_[10] = _zz_163_; + _zz_164_[9] = _zz_163_; + _zz_164_[8] = _zz_163_; + _zz_164_[7] = _zz_163_; + _zz_164_[6] = _zz_163_; + _zz_164_[5] = _zz_163_; + _zz_164_[4] = _zz_163_; + _zz_164_[3] = _zz_163_; + _zz_164_[2] = _zz_163_; + _zz_164_[1] = _zz_163_; + _zz_164_[0] = _zz_163_; + end + + assign _zz_165_ = _zz_312_[11]; + always @ (*) begin + _zz_166_[19] = _zz_165_; + _zz_166_[18] = _zz_165_; + _zz_166_[17] = _zz_165_; + _zz_166_[16] = _zz_165_; + _zz_166_[15] = _zz_165_; + _zz_166_[14] = _zz_165_; + _zz_166_[13] = _zz_165_; + _zz_166_[12] = _zz_165_; + _zz_166_[11] = _zz_165_; + _zz_166_[10] = _zz_165_; + _zz_166_[9] = _zz_165_; + _zz_166_[8] = _zz_165_; + _zz_166_[7] = _zz_165_; + _zz_166_[6] = _zz_165_; + _zz_166_[5] = _zz_165_; + _zz_166_[4] = _zz_165_; + _zz_166_[3] = _zz_165_; + _zz_166_[2] = _zz_165_; + _zz_166_[1] = _zz_165_; + _zz_166_[0] = _zz_165_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_167_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_167_ = {_zz_164_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_167_ = {_zz_166_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_167_ = _zz_50_; + end + endcase + end + + assign _zz_52_ = _zz_167_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_313_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_49_ = execute_SrcPlugin_addSub; + assign _zz_48_ = execute_SrcPlugin_addSub; + assign _zz_47_ = execute_SrcPlugin_less; + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_168_[0] = execute_SRC1[31]; + _zz_168_[1] = execute_SRC1[30]; + _zz_168_[2] = execute_SRC1[29]; + _zz_168_[3] = execute_SRC1[28]; + _zz_168_[4] = execute_SRC1[27]; + _zz_168_[5] = execute_SRC1[26]; + _zz_168_[6] = execute_SRC1[25]; + _zz_168_[7] = execute_SRC1[24]; + _zz_168_[8] = execute_SRC1[23]; + _zz_168_[9] = execute_SRC1[22]; + _zz_168_[10] = execute_SRC1[21]; + _zz_168_[11] = execute_SRC1[20]; + _zz_168_[12] = execute_SRC1[19]; + _zz_168_[13] = execute_SRC1[18]; + _zz_168_[14] = execute_SRC1[17]; + _zz_168_[15] = execute_SRC1[16]; + _zz_168_[16] = execute_SRC1[15]; + _zz_168_[17] = execute_SRC1[14]; + _zz_168_[18] = execute_SRC1[13]; + _zz_168_[19] = execute_SRC1[12]; + _zz_168_[20] = execute_SRC1[11]; + _zz_168_[21] = execute_SRC1[10]; + _zz_168_[22] = execute_SRC1[9]; + _zz_168_[23] = execute_SRC1[8]; + _zz_168_[24] = execute_SRC1[7]; + _zz_168_[25] = execute_SRC1[6]; + _zz_168_[26] = execute_SRC1[5]; + _zz_168_[27] = execute_SRC1[4]; + _zz_168_[28] = execute_SRC1[3]; + _zz_168_[29] = execute_SRC1[2]; + _zz_168_[30] = execute_SRC1[1]; + _zz_168_[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_168_ : execute_SRC1); + assign _zz_45_ = _zz_321_; + always @ (*) begin + _zz_169_[0] = memory_SHIFT_RIGHT[31]; + _zz_169_[1] = memory_SHIFT_RIGHT[30]; + _zz_169_[2] = memory_SHIFT_RIGHT[29]; + _zz_169_[3] = memory_SHIFT_RIGHT[28]; + _zz_169_[4] = memory_SHIFT_RIGHT[27]; + _zz_169_[5] = memory_SHIFT_RIGHT[26]; + _zz_169_[6] = memory_SHIFT_RIGHT[25]; + _zz_169_[7] = memory_SHIFT_RIGHT[24]; + _zz_169_[8] = memory_SHIFT_RIGHT[23]; + _zz_169_[9] = memory_SHIFT_RIGHT[22]; + _zz_169_[10] = memory_SHIFT_RIGHT[21]; + _zz_169_[11] = memory_SHIFT_RIGHT[20]; + _zz_169_[12] = memory_SHIFT_RIGHT[19]; + _zz_169_[13] = memory_SHIFT_RIGHT[18]; + _zz_169_[14] = memory_SHIFT_RIGHT[17]; + _zz_169_[15] = memory_SHIFT_RIGHT[16]; + _zz_169_[16] = memory_SHIFT_RIGHT[15]; + _zz_169_[17] = memory_SHIFT_RIGHT[14]; + _zz_169_[18] = memory_SHIFT_RIGHT[13]; + _zz_169_[19] = memory_SHIFT_RIGHT[12]; + _zz_169_[20] = memory_SHIFT_RIGHT[11]; + _zz_169_[21] = memory_SHIFT_RIGHT[10]; + _zz_169_[22] = memory_SHIFT_RIGHT[9]; + _zz_169_[23] = memory_SHIFT_RIGHT[8]; + _zz_169_[24] = memory_SHIFT_RIGHT[7]; + _zz_169_[25] = memory_SHIFT_RIGHT[6]; + _zz_169_[26] = memory_SHIFT_RIGHT[5]; + _zz_169_[27] = memory_SHIFT_RIGHT[4]; + _zz_169_[28] = memory_SHIFT_RIGHT[3]; + _zz_169_[29] = memory_SHIFT_RIGHT[2]; + _zz_169_[30] = memory_SHIFT_RIGHT[1]; + _zz_169_[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_170_ = 1'b0; + if(_zz_260_)begin + if(_zz_261_)begin + if(_zz_176_)begin + _zz_170_ = 1'b1; + end + end + end + if(_zz_262_)begin + if(_zz_263_)begin + if(_zz_178_)begin + _zz_170_ = 1'b1; + end + end + end + if(_zz_264_)begin + if(_zz_265_)begin + if(_zz_180_)begin + _zz_170_ = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_170_ = 1'b0; + end + end + + always @ (*) begin + _zz_171_ = 1'b0; + if(_zz_260_)begin + if(_zz_261_)begin + if(_zz_177_)begin + _zz_171_ = 1'b1; + end + end + end + if(_zz_262_)begin + if(_zz_263_)begin + if(_zz_179_)begin + _zz_171_ = 1'b1; + end + end + end + if(_zz_264_)begin + if(_zz_265_)begin + if(_zz_181_)begin + _zz_171_ = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_171_ = 1'b0; + end + end + + assign _zz_172_ = (_zz_60_ && writeBack_arbitration_isFiring); + assign _zz_176_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_177_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_178_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_179_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_180_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_181_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_41_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_182_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_182_ == (3'b000))) begin + _zz_183_ = execute_BranchPlugin_eq; + end else if((_zz_182_ == (3'b001))) begin + _zz_183_ = (! execute_BranchPlugin_eq); + end else if((((_zz_182_ & (3'b101)) == (3'b101)))) begin + _zz_183_ = (! execute_SRC_LESS); + end else begin + _zz_183_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_184_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_184_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_184_ = 1'b1; + end + default : begin + _zz_184_ = _zz_183_; + end + endcase + end + + assign _zz_40_ = _zz_184_; + assign _zz_185_ = _zz_323_[11]; + always @ (*) begin + _zz_186_[19] = _zz_185_; + _zz_186_[18] = _zz_185_; + _zz_186_[17] = _zz_185_; + _zz_186_[16] = _zz_185_; + _zz_186_[15] = _zz_185_; + _zz_186_[14] = _zz_185_; + _zz_186_[13] = _zz_185_; + _zz_186_[12] = _zz_185_; + _zz_186_[11] = _zz_185_; + _zz_186_[10] = _zz_185_; + _zz_186_[9] = _zz_185_; + _zz_186_[8] = _zz_185_; + _zz_186_[7] = _zz_185_; + _zz_186_[6] = _zz_185_; + _zz_186_[5] = _zz_185_; + _zz_186_[4] = _zz_185_; + _zz_186_[3] = _zz_185_; + _zz_186_[2] = _zz_185_; + _zz_186_[1] = _zz_185_; + _zz_186_[0] = _zz_185_; + end + + assign _zz_187_ = _zz_324_[19]; + always @ (*) begin + _zz_188_[10] = _zz_187_; + _zz_188_[9] = _zz_187_; + _zz_188_[8] = _zz_187_; + _zz_188_[7] = _zz_187_; + _zz_188_[6] = _zz_187_; + _zz_188_[5] = _zz_187_; + _zz_188_[4] = _zz_187_; + _zz_188_[3] = _zz_187_; + _zz_188_[2] = _zz_187_; + _zz_188_[1] = _zz_187_; + _zz_188_[0] = _zz_187_; + end + + assign _zz_189_ = _zz_325_[11]; + always @ (*) begin + _zz_190_[18] = _zz_189_; + _zz_190_[17] = _zz_189_; + _zz_190_[16] = _zz_189_; + _zz_190_[15] = _zz_189_; + _zz_190_[14] = _zz_189_; + _zz_190_[13] = _zz_189_; + _zz_190_[12] = _zz_189_; + _zz_190_[11] = _zz_189_; + _zz_190_[10] = _zz_189_; + _zz_190_[9] = _zz_189_; + _zz_190_[8] = _zz_189_; + _zz_190_[7] = _zz_189_; + _zz_190_[6] = _zz_189_; + _zz_190_[5] = _zz_189_; + _zz_190_[4] = _zz_189_; + _zz_190_[3] = _zz_189_; + _zz_190_[2] = _zz_189_; + _zz_190_[1] = _zz_189_; + _zz_190_[0] = _zz_189_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_191_ = (_zz_326_[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_191_ = _zz_327_[1]; + end + default : begin + _zz_191_ = _zz_328_[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_191_); + assign _zz_38_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_192_ = _zz_329_[11]; + always @ (*) begin + _zz_193_[19] = _zz_192_; + _zz_193_[18] = _zz_192_; + _zz_193_[17] = _zz_192_; + _zz_193_[16] = _zz_192_; + _zz_193_[15] = _zz_192_; + _zz_193_[14] = _zz_192_; + _zz_193_[13] = _zz_192_; + _zz_193_[12] = _zz_192_; + _zz_193_[11] = _zz_192_; + _zz_193_[10] = _zz_192_; + _zz_193_[9] = _zz_192_; + _zz_193_[8] = _zz_192_; + _zz_193_[7] = _zz_192_; + _zz_193_[6] = _zz_192_; + _zz_193_[5] = _zz_192_; + _zz_193_[4] = _zz_192_; + _zz_193_[3] = _zz_192_; + _zz_193_[2] = _zz_192_; + _zz_193_[1] = _zz_192_; + _zz_193_[0] = _zz_192_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_193_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_195_,{{{_zz_545_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_197_,{{{_zz_546_,_zz_547_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_332_}; + end + end + endcase + end + + assign _zz_194_ = _zz_330_[19]; + always @ (*) begin + _zz_195_[10] = _zz_194_; + _zz_195_[9] = _zz_194_; + _zz_195_[8] = _zz_194_; + _zz_195_[7] = _zz_194_; + _zz_195_[6] = _zz_194_; + _zz_195_[5] = _zz_194_; + _zz_195_[4] = _zz_194_; + _zz_195_[3] = _zz_194_; + _zz_195_[2] = _zz_194_; + _zz_195_[1] = _zz_194_; + _zz_195_[0] = _zz_194_; + end + + assign _zz_196_ = _zz_331_[11]; + always @ (*) begin + _zz_197_[18] = _zz_196_; + _zz_197_[17] = _zz_196_; + _zz_197_[16] = _zz_196_; + _zz_197_[15] = _zz_196_; + _zz_197_[14] = _zz_196_; + _zz_197_[13] = _zz_196_; + _zz_197_[12] = _zz_196_; + _zz_197_[11] = _zz_196_; + _zz_197_[10] = _zz_196_; + _zz_197_[9] = _zz_196_; + _zz_197_[8] = _zz_196_; + _zz_197_[7] = _zz_196_; + _zz_197_[6] = _zz_196_; + _zz_197_[5] = _zz_196_; + _zz_197_[4] = _zz_196_; + _zz_197_[3] = _zz_196_; + _zz_197_[2] = _zz_196_; + _zz_197_[1] = _zz_196_; + _zz_197_[0] = _zz_196_; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_37_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); + assign _zz_198_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_199_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_200_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_201_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_202_ = _zz_333_[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_253_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_35_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_34_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b110011000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_266_)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = (4'bxxxx); + if(_zz_266_)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = (4'b1000); + end + default : begin + CsrPlugin_selfException_payload_code = (4'b1011); + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_210_; + end + 12'b001100000000 : begin + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b110011000000 : begin + execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); + execute_CsrPlugin_readData[25 : 20] = (6'b100000); + end + 12'b001101000011 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_211_; + end + 12'b001100000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_276_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_MulPlugin_a = execute_SRC1; + assign execute_MulPlugin_b = execute_SRC2; + always @ (*) begin + case(_zz_267_) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_267_) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign _zz_31_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign _zz_30_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign _zz_28_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign _zz_27_ = ($signed(_zz_335_) + $signed(_zz_343_)); + assign writeBack_MulPlugin_result = ($signed(_zz_344_) + $signed(_zz_345_)); + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_248_)begin + if(_zz_254_)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_268_)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = (6'b000000); + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_349_); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = (6'b000000); + end + end + + assign _zz_203_ = memory_DivPlugin_rs1[31 : 0]; + assign _zz_204_ = {memory_DivPlugin_accumulator[31 : 0],_zz_203_[31]}; + assign _zz_205_ = (_zz_204_ - _zz_350_); + assign _zz_206_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_207_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_208_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_209_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_209_[31 : 0] = execute_RS1; + end + + assign _zz_211_ = (_zz_210_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_211_ != (32'b00000000000000000000000000000000)); + assign _zz_26_ = decode_ALU_BITWISE_CTRL; + assign _zz_24_ = _zz_70_; + assign _zz_58_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_23_ = decode_SHIFT_CTRL; + assign _zz_20_ = execute_SHIFT_CTRL; + assign _zz_21_ = _zz_86_; + assign _zz_46_ = decode_to_execute_SHIFT_CTRL; + assign _zz_44_ = execute_to_memory_SHIFT_CTRL; + assign _zz_18_ = decode_SRC1_CTRL; + assign _zz_16_ = _zz_84_; + assign _zz_53_ = decode_to_execute_SRC1_CTRL; + assign _zz_15_ = decode_SRC2_CTRL; + assign _zz_13_ = _zz_76_; + assign _zz_51_ = decode_to_execute_SRC2_CTRL; + assign _zz_12_ = decode_BRANCH_CTRL; + assign _zz_95_ = _zz_77_; + assign _zz_39_ = decode_to_execute_BRANCH_CTRL; + assign _zz_10_ = decode_ALU_CTRL; + assign _zz_8_ = _zz_74_; + assign _zz_56_ = decode_to_execute_ALU_CTRL; + assign _zz_7_ = decode_ENV_CTRL; + assign _zz_4_ = execute_ENV_CTRL; + assign _zz_2_ = memory_ENV_CTRL; + assign _zz_5_ = _zz_64_; + assign _zz_33_ = decode_to_execute_ENV_CTRL; + assign _zz_32_ = execute_to_memory_ENV_CTRL; + assign _zz_36_ = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_369_,_zz_212_}; + assign iBusWishbone_CTI = ((_zz_212_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_269_)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_269_)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_213_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_219_ = (dBus_cmd_payload_length != (3'b000)); + assign _zz_215_ = dBus_cmd_valid; + assign _zz_217_ = dBus_cmd_payload_wr; + assign _zz_218_ = (_zz_214_ == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_216_ && (_zz_217_ || _zz_218_)); + assign dBusWishbone_ADR = ((_zz_219_ ? {{dBus_cmd_payload_address[31 : 5],_zz_214_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); + assign dBusWishbone_CTI = (_zz_219_ ? (_zz_218_ ? (3'b111) : (3'b010)) : (3'b000)); + assign dBusWishbone_BTE = (2'b00); + assign dBusWishbone_SEL = (_zz_217_ ? dBus_cmd_payload_mask : (4'b1111)); + assign dBusWishbone_WE = _zz_217_; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_216_ = (_zz_215_ && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_215_; + assign dBusWishbone_STB = _zz_215_; + assign dBus_rsp_valid = _zz_220_; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_112_ <= 1'b0; + _zz_114_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_127_; + IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); + _zz_128_ <= 1'b0; + _zz_135_ <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_142_; + DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); + _zz_160_ <= 1'b1; + _zz_173_ <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= (6'b000000); + _zz_210_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); + memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); + _zz_212_ <= (3'b000); + _zz_213_ <= 1'b0; + _zz_214_ <= (3'b000); + _zz_220_ <= 1'b0; + end else begin + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_fetcherflushIt)begin + _zz_112_ <= 1'b0; + end + if(_zz_110_)begin + _zz_112_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + end + if(IBusCachedPlugin_fetcherflushIt)begin + _zz_114_ <= 1'b0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + end + if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin + _zz_128_ <= 1'b0; + end + if(_zz_270_)begin + _zz_128_ <= dataCache_1__io_mem_cmd_valid; + end + if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin + _zz_135_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + end + _zz_160_ <= 1'b0; + _zz_173_ <= _zz_172_; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_271_)begin + if(_zz_272_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_273_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_274_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_255_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_256_)begin + case(_zz_257_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= ({_zz_200_,{_zz_199_,_zz_198_}} != (3'b000)); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_43_; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_210_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_363_[0]; + CsrPlugin_mstatus_MIE <= _zz_364_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + end + 12'b110011000000 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_366_[0]; + CsrPlugin_mie_MTIE <= _zz_367_[0]; + CsrPlugin_mie_MSIE <= _zz_368_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_269_)begin + if(iBusWishbone_ACK)begin + _zz_212_ <= (_zz_212_ + (3'b001)); + end + end + _zz_213_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_215_ && _zz_216_))begin + _zz_214_ <= (_zz_214_ + (3'b001)); + if(_zz_218_)begin + _zz_214_ <= (3'b000); + end + end + _zz_220_ <= ((_zz_215_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_270_)begin + _zz_129_ <= dataCache_1__io_mem_cmd_payload_wr; + _zz_130_ <= dataCache_1__io_mem_cmd_payload_address; + _zz_131_ <= dataCache_1__io_mem_cmd_payload_data; + _zz_132_ <= dataCache_1__io_mem_cmd_payload_mask; + _zz_133_ <= dataCache_1__io_mem_cmd_payload_length; + _zz_134_ <= dataCache_1__io_mem_cmd_payload_last; + end + if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin + _zz_136_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; + _zz_137_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; + _zz_138_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; + _zz_139_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; + _zz_140_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; + _zz_141_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; + end + if(_zz_172_)begin + _zz_174_ <= _zz_59_[11 : 7]; + _zz_175_ <= _zz_89_; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(_zz_253_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_271_)begin + if(_zz_272_)begin + CsrPlugin_interrupt_code <= (4'b0111); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_273_)begin + CsrPlugin_interrupt_code <= (4'b0011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_274_)begin + CsrPlugin_interrupt_code <= (4'b1011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + end + if(_zz_255_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((memory_DivPlugin_div_counter_value == (6'b100000)))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_248_)begin + if(_zz_254_)begin + memory_DivPlugin_rs1[31 : 0] <= _zz_351_[31:0]; + memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_205_[32]) ? _zz_352_ : _zz_353_); + if((memory_DivPlugin_div_counter_value == (6'b100000)))begin + memory_DivPlugin_div_result <= _zz_354_[31:0]; + end + end + end + if(_zz_268_)begin + memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); + memory_DivPlugin_rs1 <= ((_zz_208_ ? (~ _zz_209_) : _zz_209_) + _zz_360_); + memory_DivPlugin_rs2 <= ((_zz_207_ ? (~ execute_RS2) : execute_RS2) + _zz_362_); + memory_DivPlugin_div_needRevert <= ((_zz_208_ ^ (_zz_207_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_25_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_22_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_19_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_50_; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_14_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_9_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_42_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_97_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_96_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_365_[0]; + end + end + 12'b110011000000 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + +endmodule + diff --git a/xc7/litex_sata_demo/litesata.v b/xc7/litex_sata_demo/litesata.v new file mode 100644 index 0000000..efc38d7 --- /dev/null +++ b/xc7/litex_sata_demo/litesata.v @@ -0,0 +1,17870 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (c50ecde) & LiteX (95b310ee) on 2021-11-22 10:12:20 +//-------------------------------------------------------------------------------- +module top( + output reg serial_tx, + input wire serial_rx, + input wire cpu_reset, + (* dont_touch = "true" *) input wire clk100, + output wire [14:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire [1:0] ddram_dm, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + input wire fmc2sata_clk_p, + input wire fmc2sata_clk_n, + output wire fmc2sata_tx_p, + output wire fmc2sata_tx_n, + input wire fmc2sata_rx_p, + input wire fmc2sata_rx_n, + output reg user_led0, + output reg user_led1, + output reg user_led2, + output reg user_led3, + output reg user_led4, + output reg user_led5, + output reg user_led6, + output reg user_led7, + output wire [1:0] vadj +); + +// VADJ adjust the output voltage and 3.3V is required for the FMC2SATA adapter board to properly work +// A value of 2'b11 provides the necessary 3.3V +assign vadj = 2'b11; + +reg soccontroller_reset_storage = 1'd0; +reg soccontroller_reset_re = 1'd0; +reg [31:0] soccontroller_scratch_storage = 32'd305419896; +reg soccontroller_scratch_re = 1'd0; +wire [31:0] soccontroller_bus_errors_status; +wire soccontroller_bus_errors_we; +reg soccontroller_bus_errors_re = 1'd0; +wire soccontroller_reset; +wire soccontroller_bus_error; +reg [31:0] soccontroller_bus_errors = 32'd0; +wire cpu_reset_1; +reg [31:0] cpu_interrupt = 32'd0; +wire [29:0] cpu_ibus_adr; +wire [31:0] cpu_ibus_dat_w; +wire [31:0] cpu_ibus_dat_r; +wire [3:0] cpu_ibus_sel; +wire cpu_ibus_cyc; +wire cpu_ibus_stb; +wire cpu_ibus_ack; +wire cpu_ibus_we; +wire [2:0] cpu_ibus_cti; +wire [1:0] cpu_ibus_bte; +wire cpu_ibus_err; +wire [29:0] cpu_dbus_adr; +wire [31:0] cpu_dbus_dat_w; +wire [31:0] cpu_dbus_dat_r; +wire [3:0] cpu_dbus_sel; +wire cpu_dbus_cyc; +wire cpu_dbus_stb; +wire cpu_dbus_ack; +wire cpu_dbus_we; +wire [2:0] cpu_dbus_cti; +wire [1:0] cpu_dbus_bte; +wire cpu_dbus_err; +reg [31:0] vexriscv = 32'd0; +wire [29:0] basesoc_ram_bus_adr; +wire [31:0] basesoc_ram_bus_dat_w; +wire [31:0] basesoc_ram_bus_dat_r; +wire [3:0] basesoc_ram_bus_sel; +wire basesoc_ram_bus_cyc; +wire basesoc_ram_bus_stb; +reg basesoc_ram_bus_ack = 1'd0; +wire basesoc_ram_bus_we; +wire [2:0] basesoc_ram_bus_cti; +wire [1:0] basesoc_ram_bus_bte; +reg basesoc_ram_bus_err = 1'd0; +wire [13:0] basesoc_adr; +wire [31:0] basesoc_dat_r; +wire [29:0] ram_bus_ram_bus_adr; +wire [31:0] ram_bus_ram_bus_dat_w; +wire [31:0] ram_bus_ram_bus_dat_r; +wire [3:0] ram_bus_ram_bus_sel; +wire ram_bus_ram_bus_cyc; +wire ram_bus_ram_bus_stb; +reg ram_bus_ram_bus_ack = 1'd0; +wire ram_bus_ram_bus_we; +wire [2:0] ram_bus_ram_bus_cti; +wire [1:0] ram_bus_ram_bus_bte; +reg ram_bus_ram_bus_err = 1'd0; +wire [10:0] ram_adr; +wire [31:0] ram_dat_r; +reg [3:0] ram_we = 4'd0; +wire [31:0] ram_dat_w; +reg [31:0] uart_phy_storage = 32'd6184752; +reg uart_phy_re = 1'd0; +wire uart_phy_sink_valid; +reg uart_phy_sink_ready = 1'd0; +wire uart_phy_sink_first; +wire uart_phy_sink_last; +wire [7:0] uart_phy_sink_payload_data; +reg uart_phy_tx_clken = 1'd0; +reg [31:0] uart_phy_tx_clkphase = 32'd0; +reg [7:0] uart_phy_tx_reg = 8'd0; +reg [3:0] uart_phy_tx_bitcount = 4'd0; +reg uart_phy_tx_busy = 1'd0; +reg uart_phy_source_valid = 1'd0; +wire uart_phy_source_ready; +reg uart_phy_source_first = 1'd0; +reg uart_phy_source_last = 1'd0; +reg [7:0] uart_phy_source_payload_data = 8'd0; +reg uart_phy_rx_clken = 1'd0; +reg [31:0] uart_phy_rx_clkphase = 32'd0; +wire uart_phy_rx; +reg uart_phy_rx_r = 1'd0; +reg [7:0] uart_phy_rx_reg = 8'd0; +reg [3:0] uart_phy_rx_bitcount = 4'd0; +reg uart_phy_rx_busy = 1'd0; +wire uart_rxtx_re; +wire [7:0] uart_rxtx_r; +wire uart_rxtx_we; +wire [7:0] uart_rxtx_w; +wire uart_txfull_status; +wire uart_txfull_we; +reg uart_txfull_re = 1'd0; +wire uart_rxempty_status; +wire uart_rxempty_we; +reg uart_rxempty_re = 1'd0; +wire uart_irq; +wire uart_tx_status; +reg uart_tx_pending = 1'd0; +wire uart_tx_trigger; +reg uart_tx_clear = 1'd0; +reg uart_tx_old_trigger = 1'd0; +wire uart_rx_status; +reg uart_rx_pending = 1'd0; +wire uart_rx_trigger; +reg uart_rx_clear = 1'd0; +reg uart_rx_old_trigger = 1'd0; +wire uart_tx0; +wire uart_rx0; +reg [1:0] uart_status_status = 2'd0; +wire uart_status_we; +reg uart_status_re = 1'd0; +wire uart_tx1; +wire uart_rx1; +reg [1:0] uart_pending_status = 2'd0; +wire uart_pending_we; +reg uart_pending_re = 1'd0; +reg [1:0] uart_pending_r = 2'd0; +wire uart_tx2; +wire uart_rx2; +reg [1:0] uart_enable_storage = 2'd0; +reg uart_enable_re = 1'd0; +wire uart_txempty_status; +wire uart_txempty_we; +reg uart_txempty_re = 1'd0; +wire uart_rxfull_status; +wire uart_rxfull_we; +reg uart_rxfull_re = 1'd0; +wire uart_uart_sink_valid; +wire uart_uart_sink_ready; +wire uart_uart_sink_first; +wire uart_uart_sink_last; +wire [7:0] uart_uart_sink_payload_data; +wire uart_uart_source_valid; +wire uart_uart_source_ready; +wire uart_uart_source_first; +wire uart_uart_source_last; +wire [7:0] uart_uart_source_payload_data; +wire uart_tx_fifo_sink_valid; +wire uart_tx_fifo_sink_ready; +reg uart_tx_fifo_sink_first = 1'd0; +reg uart_tx_fifo_sink_last = 1'd0; +wire [7:0] uart_tx_fifo_sink_payload_data; +wire uart_tx_fifo_source_valid; +wire uart_tx_fifo_source_ready; +wire uart_tx_fifo_source_first; +wire uart_tx_fifo_source_last; +wire [7:0] uart_tx_fifo_source_payload_data; +wire uart_tx_fifo_re; +reg uart_tx_fifo_readable = 1'd0; +wire uart_tx_fifo_syncfifo_we; +wire uart_tx_fifo_syncfifo_writable; +wire uart_tx_fifo_syncfifo_re; +wire uart_tx_fifo_syncfifo_readable; +wire [9:0] uart_tx_fifo_syncfifo_din; +wire [9:0] uart_tx_fifo_syncfifo_dout; +reg [4:0] uart_tx_fifo_level0 = 5'd0; +reg uart_tx_fifo_replace = 1'd0; +reg [3:0] uart_tx_fifo_produce = 4'd0; +reg [3:0] uart_tx_fifo_consume = 4'd0; +reg [3:0] uart_tx_fifo_wrport_adr = 4'd0; +wire [9:0] uart_tx_fifo_wrport_dat_r; +wire uart_tx_fifo_wrport_we; +wire [9:0] uart_tx_fifo_wrport_dat_w; +wire uart_tx_fifo_do_read; +wire [3:0] uart_tx_fifo_rdport_adr; +wire [9:0] uart_tx_fifo_rdport_dat_r; +wire uart_tx_fifo_rdport_re; +wire [4:0] uart_tx_fifo_level1; +wire [7:0] uart_tx_fifo_fifo_in_payload_data; +wire uart_tx_fifo_fifo_in_first; +wire uart_tx_fifo_fifo_in_last; +wire [7:0] uart_tx_fifo_fifo_out_payload_data; +wire uart_tx_fifo_fifo_out_first; +wire uart_tx_fifo_fifo_out_last; +wire uart_rx_fifo_sink_valid; +wire uart_rx_fifo_sink_ready; +wire uart_rx_fifo_sink_first; +wire uart_rx_fifo_sink_last; +wire [7:0] uart_rx_fifo_sink_payload_data; +wire uart_rx_fifo_source_valid; +wire uart_rx_fifo_source_ready; +wire uart_rx_fifo_source_first; +wire uart_rx_fifo_source_last; +wire [7:0] uart_rx_fifo_source_payload_data; +wire uart_rx_fifo_re; +reg uart_rx_fifo_readable = 1'd0; +wire uart_rx_fifo_syncfifo_we; +wire uart_rx_fifo_syncfifo_writable; +wire uart_rx_fifo_syncfifo_re; +wire uart_rx_fifo_syncfifo_readable; +wire [9:0] uart_rx_fifo_syncfifo_din; +wire [9:0] uart_rx_fifo_syncfifo_dout; +reg [4:0] uart_rx_fifo_level0 = 5'd0; +reg uart_rx_fifo_replace = 1'd0; +reg [3:0] uart_rx_fifo_produce = 4'd0; +reg [3:0] uart_rx_fifo_consume = 4'd0; +reg [3:0] uart_rx_fifo_wrport_adr = 4'd0; +wire [9:0] uart_rx_fifo_wrport_dat_r; +wire uart_rx_fifo_wrport_we; +wire [9:0] uart_rx_fifo_wrport_dat_w; +wire uart_rx_fifo_do_read; +wire [3:0] uart_rx_fifo_rdport_adr; +wire [9:0] uart_rx_fifo_rdport_dat_r; +wire uart_rx_fifo_rdport_re; +wire [4:0] uart_rx_fifo_level1; +wire [7:0] uart_rx_fifo_fifo_in_payload_data; +wire uart_rx_fifo_fifo_in_first; +wire uart_rx_fifo_fifo_in_last; +wire [7:0] uart_rx_fifo_fifo_out_payload_data; +wire uart_rx_fifo_fifo_out_first; +wire uart_rx_fifo_fifo_out_last; +reg [31:0] timer_load_storage = 32'd0; +reg timer_load_re = 1'd0; +reg [31:0] timer_reload_storage = 32'd0; +reg timer_reload_re = 1'd0; +reg timer_en_storage = 1'd0; +reg timer_en_re = 1'd0; +reg timer_update_value_storage = 1'd0; +reg timer_update_value_re = 1'd0; +reg [31:0] timer_value_status = 32'd0; +wire timer_value_we; +reg timer_value_re = 1'd0; +wire timer_irq; +wire timer_zero_status; +reg timer_zero_pending = 1'd0; +wire timer_zero_trigger; +reg timer_zero_clear = 1'd0; +reg timer_zero_old_trigger = 1'd0; +wire timer_zero0; +wire timer_status_status; +wire timer_status_we; +reg timer_status_re = 1'd0; +wire timer_zero1; +wire timer_pending_status; +wire timer_pending_we; +reg timer_pending_re = 1'd0; +reg timer_pending_r = 1'd0; +wire timer_zero2; +reg timer_enable_storage = 1'd0; +reg timer_enable_re = 1'd0; +reg [31:0] timer_value = 32'd0; +wire crg_rst; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire idelay_clk; +wire idelay_rst; +wire clk100_clk; +wire clk100_rst; +wire crg_reset; +wire crg_locked; +wire crg_clkin; +wire crg_clkout0; +wire crg_clkout_buf0; +wire crg_clkout1; +wire crg_clkout_buf1; +wire crg_clkout2; +wire crg_clkout_buf2; +wire crg_clkout3; +wire crg_clkout_buf3; +wire crg_clkout4; +wire crg_clkout_buf4; +reg [3:0] crg_reset_counter = 4'd15; +reg crg_ic_reset = 1'd1; +reg a7ddrphy_rst_storage = 1'd0; +reg a7ddrphy_rst_re = 1'd0; +reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd10; +reg a7ddrphy_half_sys8x_taps_re = 1'd0; +reg a7ddrphy_wlevel_en_storage = 1'd0; +reg a7ddrphy_wlevel_en_re = 1'd0; +wire a7ddrphy_wlevel_strobe_re; +wire a7ddrphy_wlevel_strobe_r; +wire a7ddrphy_wlevel_strobe_we; +reg a7ddrphy_wlevel_strobe_w = 1'd0; +reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; +reg a7ddrphy_dly_sel_re = 1'd0; +wire a7ddrphy_rdly_dq_rst_re; +wire a7ddrphy_rdly_dq_rst_r; +wire a7ddrphy_rdly_dq_rst_we; +reg a7ddrphy_rdly_dq_rst_w = 1'd0; +wire a7ddrphy_rdly_dq_inc_re; +wire a7ddrphy_rdly_dq_inc_r; +wire a7ddrphy_rdly_dq_inc_we; +reg a7ddrphy_rdly_dq_inc_w = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_rst_re; +wire a7ddrphy_rdly_dq_bitslip_rst_r; +wire a7ddrphy_rdly_dq_bitslip_rst_we; +reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_re; +wire a7ddrphy_rdly_dq_bitslip_r; +wire a7ddrphy_rdly_dq_bitslip_we; +reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_rst_re; +wire a7ddrphy_wdly_dq_bitslip_rst_r; +wire a7ddrphy_wdly_dq_bitslip_rst_we; +reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_re; +wire a7ddrphy_wdly_dq_bitslip_r; +wire a7ddrphy_wdly_dq_bitslip_we; +reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] a7ddrphy_rdphase_storage = 2'd2; +reg a7ddrphy_rdphase_re = 1'd0; +reg [1:0] a7ddrphy_wrphase_storage = 2'd3; +reg a7ddrphy_wrphase_re = 1'd0; +wire [14:0] a7ddrphy_dfi_p0_address; +wire [2:0] a7ddrphy_dfi_p0_bank; +wire a7ddrphy_dfi_p0_cas_n; +wire a7ddrphy_dfi_p0_cs_n; +wire a7ddrphy_dfi_p0_ras_n; +wire a7ddrphy_dfi_p0_we_n; +wire a7ddrphy_dfi_p0_cke; +wire a7ddrphy_dfi_p0_odt; +wire a7ddrphy_dfi_p0_reset_n; +wire a7ddrphy_dfi_p0_act_n; +wire [31:0] a7ddrphy_dfi_p0_wrdata; +wire a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; +wire a7ddrphy_dfi_p0_rddata_en; +reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; +wire a7ddrphy_dfi_p0_rddata_valid; +wire [14:0] a7ddrphy_dfi_p1_address; +wire [2:0] a7ddrphy_dfi_p1_bank; +wire a7ddrphy_dfi_p1_cas_n; +wire a7ddrphy_dfi_p1_cs_n; +wire a7ddrphy_dfi_p1_ras_n; +wire a7ddrphy_dfi_p1_we_n; +wire a7ddrphy_dfi_p1_cke; +wire a7ddrphy_dfi_p1_odt; +wire a7ddrphy_dfi_p1_reset_n; +wire a7ddrphy_dfi_p1_act_n; +wire [31:0] a7ddrphy_dfi_p1_wrdata; +wire a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; +wire a7ddrphy_dfi_p1_rddata_en; +reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; +wire a7ddrphy_dfi_p1_rddata_valid; +wire [14:0] a7ddrphy_dfi_p2_address; +wire [2:0] a7ddrphy_dfi_p2_bank; +wire a7ddrphy_dfi_p2_cas_n; +wire a7ddrphy_dfi_p2_cs_n; +wire a7ddrphy_dfi_p2_ras_n; +wire a7ddrphy_dfi_p2_we_n; +wire a7ddrphy_dfi_p2_cke; +wire a7ddrphy_dfi_p2_odt; +wire a7ddrphy_dfi_p2_reset_n; +wire a7ddrphy_dfi_p2_act_n; +wire [31:0] a7ddrphy_dfi_p2_wrdata; +wire a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; +wire a7ddrphy_dfi_p2_rddata_en; +reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; +wire a7ddrphy_dfi_p2_rddata_valid; +wire [14:0] a7ddrphy_dfi_p3_address; +wire [2:0] a7ddrphy_dfi_p3_bank; +wire a7ddrphy_dfi_p3_cas_n; +wire a7ddrphy_dfi_p3_cs_n; +wire a7ddrphy_dfi_p3_ras_n; +wire a7ddrphy_dfi_p3_we_n; +wire a7ddrphy_dfi_p3_cke; +wire a7ddrphy_dfi_p3_odt; +wire a7ddrphy_dfi_p3_reset_n; +wire a7ddrphy_dfi_p3_act_n; +wire [31:0] a7ddrphy_dfi_p3_wrdata; +wire a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; +wire a7ddrphy_dfi_p3_rddata_en; +reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; +wire a7ddrphy_dfi_p3_rddata_valid; +wire a7ddrphy_sd_clk_se_nodelay; +reg a7ddrphy_dqs_oe = 1'd0; +wire a7ddrphy_dqs_preamble; +wire a7ddrphy_dqs_postamble; +wire a7ddrphy_dqs_oe_delay_tappeddelayline; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg a7ddrphy_dqspattern0 = 1'd0; +reg a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; +wire a7ddrphy_dqs_o_no_delay0; +wire a7ddrphy_dqs_t0; +reg [7:0] a7ddrphy_bitslip00 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; +wire a7ddrphy0; +wire a7ddrphy_dqs_o_no_delay1; +wire a7ddrphy_dqs_t1; +reg [7:0] a7ddrphy_bitslip10 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; +wire a7ddrphy1; +reg [7:0] a7ddrphy_bitslip01 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] a7ddrphy_bitslip11 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; +wire a7ddrphy_dq_oe; +wire a7ddrphy_dq_oe_delay_tappeddelayline; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire a7ddrphy_dq_o_nodelay0; +wire a7ddrphy_dq_i_nodelay0; +wire a7ddrphy_dq_i_delayed0; +wire a7ddrphy_dq_t0; +reg [7:0] a7ddrphy_bitslip02 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip03; +reg [7:0] a7ddrphy_bitslip04 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay1; +wire a7ddrphy_dq_i_nodelay1; +wire a7ddrphy_dq_i_delayed1; +wire a7ddrphy_dq_t1; +reg [7:0] a7ddrphy_bitslip12 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip13; +reg [7:0] a7ddrphy_bitslip14 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay2; +wire a7ddrphy_dq_i_nodelay2; +wire a7ddrphy_dq_i_delayed2; +wire a7ddrphy_dq_t2; +reg [7:0] a7ddrphy_bitslip20 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip21; +reg [7:0] a7ddrphy_bitslip22 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay3; +wire a7ddrphy_dq_i_nodelay3; +wire a7ddrphy_dq_i_delayed3; +wire a7ddrphy_dq_t3; +reg [7:0] a7ddrphy_bitslip30 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip31; +reg [7:0] a7ddrphy_bitslip32 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay4; +wire a7ddrphy_dq_i_nodelay4; +wire a7ddrphy_dq_i_delayed4; +wire a7ddrphy_dq_t4; +reg [7:0] a7ddrphy_bitslip40 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip41; +reg [7:0] a7ddrphy_bitslip42 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay5; +wire a7ddrphy_dq_i_nodelay5; +wire a7ddrphy_dq_i_delayed5; +wire a7ddrphy_dq_t5; +reg [7:0] a7ddrphy_bitslip50 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip51; +reg [7:0] a7ddrphy_bitslip52 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay6; +wire a7ddrphy_dq_i_nodelay6; +wire a7ddrphy_dq_i_delayed6; +wire a7ddrphy_dq_t6; +reg [7:0] a7ddrphy_bitslip60 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip61; +reg [7:0] a7ddrphy_bitslip62 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay7; +wire a7ddrphy_dq_i_nodelay7; +wire a7ddrphy_dq_i_delayed7; +wire a7ddrphy_dq_t7; +reg [7:0] a7ddrphy_bitslip70 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip71; +reg [7:0] a7ddrphy_bitslip72 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay8; +wire a7ddrphy_dq_i_nodelay8; +wire a7ddrphy_dq_i_delayed8; +wire a7ddrphy_dq_t8; +reg [7:0] a7ddrphy_bitslip80 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip81; +reg [7:0] a7ddrphy_bitslip82 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay9; +wire a7ddrphy_dq_i_nodelay9; +wire a7ddrphy_dq_i_delayed9; +wire a7ddrphy_dq_t9; +reg [7:0] a7ddrphy_bitslip90 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip91; +reg [7:0] a7ddrphy_bitslip92 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay10; +wire a7ddrphy_dq_i_nodelay10; +wire a7ddrphy_dq_i_delayed10; +wire a7ddrphy_dq_t10; +reg [7:0] a7ddrphy_bitslip100 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip101; +reg [7:0] a7ddrphy_bitslip102 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay11; +wire a7ddrphy_dq_i_nodelay11; +wire a7ddrphy_dq_i_delayed11; +wire a7ddrphy_dq_t11; +reg [7:0] a7ddrphy_bitslip110 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip111; +reg [7:0] a7ddrphy_bitslip112 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay12; +wire a7ddrphy_dq_i_nodelay12; +wire a7ddrphy_dq_i_delayed12; +wire a7ddrphy_dq_t12; +reg [7:0] a7ddrphy_bitslip120 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip121; +reg [7:0] a7ddrphy_bitslip122 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay13; +wire a7ddrphy_dq_i_nodelay13; +wire a7ddrphy_dq_i_delayed13; +wire a7ddrphy_dq_t13; +reg [7:0] a7ddrphy_bitslip130 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip131; +reg [7:0] a7ddrphy_bitslip132 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay14; +wire a7ddrphy_dq_i_nodelay14; +wire a7ddrphy_dq_i_delayed14; +wire a7ddrphy_dq_t14; +reg [7:0] a7ddrphy_bitslip140 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip141; +reg [7:0] a7ddrphy_bitslip142 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay15; +wire a7ddrphy_dq_i_nodelay15; +wire a7ddrphy_dq_i_delayed15; +wire a7ddrphy_dq_t15; +reg [7:0] a7ddrphy_bitslip150 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip151; +reg [7:0] a7ddrphy_bitslip152 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; +reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [13:0] sdram_inti_p0_address; +wire [2:0] sdram_inti_p0_bank; +reg sdram_inti_p0_cas_n = 1'd1; +reg sdram_inti_p0_cs_n = 1'd1; +reg sdram_inti_p0_ras_n = 1'd1; +reg sdram_inti_p0_we_n = 1'd1; +wire sdram_inti_p0_cke; +wire sdram_inti_p0_odt; +wire sdram_inti_p0_reset_n; +reg sdram_inti_p0_act_n = 1'd1; +wire [31:0] sdram_inti_p0_wrdata; +wire sdram_inti_p0_wrdata_en; +wire [3:0] sdram_inti_p0_wrdata_mask; +wire sdram_inti_p0_rddata_en; +reg [31:0] sdram_inti_p0_rddata = 32'd0; +reg sdram_inti_p0_rddata_valid = 1'd0; +wire [13:0] sdram_inti_p1_address; +wire [2:0] sdram_inti_p1_bank; +reg sdram_inti_p1_cas_n = 1'd1; +reg sdram_inti_p1_cs_n = 1'd1; +reg sdram_inti_p1_ras_n = 1'd1; +reg sdram_inti_p1_we_n = 1'd1; +wire sdram_inti_p1_cke; +wire sdram_inti_p1_odt; +wire sdram_inti_p1_reset_n; +reg sdram_inti_p1_act_n = 1'd1; +wire [31:0] sdram_inti_p1_wrdata; +wire sdram_inti_p1_wrdata_en; +wire [3:0] sdram_inti_p1_wrdata_mask; +wire sdram_inti_p1_rddata_en; +reg [31:0] sdram_inti_p1_rddata = 32'd0; +reg sdram_inti_p1_rddata_valid = 1'd0; +wire [13:0] sdram_inti_p2_address; +wire [2:0] sdram_inti_p2_bank; +reg sdram_inti_p2_cas_n = 1'd1; +reg sdram_inti_p2_cs_n = 1'd1; +reg sdram_inti_p2_ras_n = 1'd1; +reg sdram_inti_p2_we_n = 1'd1; +wire sdram_inti_p2_cke; +wire sdram_inti_p2_odt; +wire sdram_inti_p2_reset_n; +reg sdram_inti_p2_act_n = 1'd1; +wire [31:0] sdram_inti_p2_wrdata; +wire sdram_inti_p2_wrdata_en; +wire [3:0] sdram_inti_p2_wrdata_mask; +wire sdram_inti_p2_rddata_en; +reg [31:0] sdram_inti_p2_rddata = 32'd0; +reg sdram_inti_p2_rddata_valid = 1'd0; +wire [13:0] sdram_inti_p3_address; +wire [2:0] sdram_inti_p3_bank; +reg sdram_inti_p3_cas_n = 1'd1; +reg sdram_inti_p3_cs_n = 1'd1; +reg sdram_inti_p3_ras_n = 1'd1; +reg sdram_inti_p3_we_n = 1'd1; +wire sdram_inti_p3_cke; +wire sdram_inti_p3_odt; +wire sdram_inti_p3_reset_n; +reg sdram_inti_p3_act_n = 1'd1; +wire [31:0] sdram_inti_p3_wrdata; +wire sdram_inti_p3_wrdata_en; +wire [3:0] sdram_inti_p3_wrdata_mask; +wire sdram_inti_p3_rddata_en; +reg [31:0] sdram_inti_p3_rddata = 32'd0; +reg sdram_inti_p3_rddata_valid = 1'd0; +wire [13:0] sdram_slave_p0_address; +wire [2:0] sdram_slave_p0_bank; +wire sdram_slave_p0_cas_n; +wire sdram_slave_p0_cs_n; +wire sdram_slave_p0_ras_n; +wire sdram_slave_p0_we_n; +wire sdram_slave_p0_cke; +wire sdram_slave_p0_odt; +wire sdram_slave_p0_reset_n; +wire sdram_slave_p0_act_n; +wire [31:0] sdram_slave_p0_wrdata; +wire sdram_slave_p0_wrdata_en; +wire [3:0] sdram_slave_p0_wrdata_mask; +wire sdram_slave_p0_rddata_en; +reg [31:0] sdram_slave_p0_rddata = 32'd0; +reg sdram_slave_p0_rddata_valid = 1'd0; +wire [13:0] sdram_slave_p1_address; +wire [2:0] sdram_slave_p1_bank; +wire sdram_slave_p1_cas_n; +wire sdram_slave_p1_cs_n; +wire sdram_slave_p1_ras_n; +wire sdram_slave_p1_we_n; +wire sdram_slave_p1_cke; +wire sdram_slave_p1_odt; +wire sdram_slave_p1_reset_n; +wire sdram_slave_p1_act_n; +wire [31:0] sdram_slave_p1_wrdata; +wire sdram_slave_p1_wrdata_en; +wire [3:0] sdram_slave_p1_wrdata_mask; +wire sdram_slave_p1_rddata_en; +reg [31:0] sdram_slave_p1_rddata = 32'd0; +reg sdram_slave_p1_rddata_valid = 1'd0; +wire [13:0] sdram_slave_p2_address; +wire [2:0] sdram_slave_p2_bank; +wire sdram_slave_p2_cas_n; +wire sdram_slave_p2_cs_n; +wire sdram_slave_p2_ras_n; +wire sdram_slave_p2_we_n; +wire sdram_slave_p2_cke; +wire sdram_slave_p2_odt; +wire sdram_slave_p2_reset_n; +wire sdram_slave_p2_act_n; +wire [31:0] sdram_slave_p2_wrdata; +wire sdram_slave_p2_wrdata_en; +wire [3:0] sdram_slave_p2_wrdata_mask; +wire sdram_slave_p2_rddata_en; +reg [31:0] sdram_slave_p2_rddata = 32'd0; +reg sdram_slave_p2_rddata_valid = 1'd0; +wire [13:0] sdram_slave_p3_address; +wire [2:0] sdram_slave_p3_bank; +wire sdram_slave_p3_cas_n; +wire sdram_slave_p3_cs_n; +wire sdram_slave_p3_ras_n; +wire sdram_slave_p3_we_n; +wire sdram_slave_p3_cke; +wire sdram_slave_p3_odt; +wire sdram_slave_p3_reset_n; +wire sdram_slave_p3_act_n; +wire [31:0] sdram_slave_p3_wrdata; +wire sdram_slave_p3_wrdata_en; +wire [3:0] sdram_slave_p3_wrdata_mask; +wire sdram_slave_p3_rddata_en; +reg [31:0] sdram_slave_p3_rddata = 32'd0; +reg sdram_slave_p3_rddata_valid = 1'd0; +reg [13:0] sdram_master_p0_address = 14'd0; +reg [2:0] sdram_master_p0_bank = 3'd0; +reg sdram_master_p0_cas_n = 1'd1; +reg sdram_master_p0_cs_n = 1'd1; +reg sdram_master_p0_ras_n = 1'd1; +reg sdram_master_p0_we_n = 1'd1; +reg sdram_master_p0_cke = 1'd0; +reg sdram_master_p0_odt = 1'd0; +reg sdram_master_p0_reset_n = 1'd0; +reg sdram_master_p0_act_n = 1'd1; +reg [31:0] sdram_master_p0_wrdata = 32'd0; +reg sdram_master_p0_wrdata_en = 1'd0; +reg [3:0] sdram_master_p0_wrdata_mask = 4'd0; +reg sdram_master_p0_rddata_en = 1'd0; +wire [31:0] sdram_master_p0_rddata; +wire sdram_master_p0_rddata_valid; +reg [13:0] sdram_master_p1_address = 14'd0; +reg [2:0] sdram_master_p1_bank = 3'd0; +reg sdram_master_p1_cas_n = 1'd1; +reg sdram_master_p1_cs_n = 1'd1; +reg sdram_master_p1_ras_n = 1'd1; +reg sdram_master_p1_we_n = 1'd1; +reg sdram_master_p1_cke = 1'd0; +reg sdram_master_p1_odt = 1'd0; +reg sdram_master_p1_reset_n = 1'd0; +reg sdram_master_p1_act_n = 1'd1; +reg [31:0] sdram_master_p1_wrdata = 32'd0; +reg sdram_master_p1_wrdata_en = 1'd0; +reg [3:0] sdram_master_p1_wrdata_mask = 4'd0; +reg sdram_master_p1_rddata_en = 1'd0; +wire [31:0] sdram_master_p1_rddata; +wire sdram_master_p1_rddata_valid; +reg [13:0] sdram_master_p2_address = 14'd0; +reg [2:0] sdram_master_p2_bank = 3'd0; +reg sdram_master_p2_cas_n = 1'd1; +reg sdram_master_p2_cs_n = 1'd1; +reg sdram_master_p2_ras_n = 1'd1; +reg sdram_master_p2_we_n = 1'd1; +reg sdram_master_p2_cke = 1'd0; +reg sdram_master_p2_odt = 1'd0; +reg sdram_master_p2_reset_n = 1'd0; +reg sdram_master_p2_act_n = 1'd1; +reg [31:0] sdram_master_p2_wrdata = 32'd0; +reg sdram_master_p2_wrdata_en = 1'd0; +reg [3:0] sdram_master_p2_wrdata_mask = 4'd0; +reg sdram_master_p2_rddata_en = 1'd0; +wire [31:0] sdram_master_p2_rddata; +wire sdram_master_p2_rddata_valid; +reg [13:0] sdram_master_p3_address = 14'd0; +reg [2:0] sdram_master_p3_bank = 3'd0; +reg sdram_master_p3_cas_n = 1'd1; +reg sdram_master_p3_cs_n = 1'd1; +reg sdram_master_p3_ras_n = 1'd1; +reg sdram_master_p3_we_n = 1'd1; +reg sdram_master_p3_cke = 1'd0; +reg sdram_master_p3_odt = 1'd0; +reg sdram_master_p3_reset_n = 1'd0; +reg sdram_master_p3_act_n = 1'd1; +reg [31:0] sdram_master_p3_wrdata = 32'd0; +reg sdram_master_p3_wrdata_en = 1'd0; +reg [3:0] sdram_master_p3_wrdata_mask = 4'd0; +reg sdram_master_p3_rddata_en = 1'd0; +wire [31:0] sdram_master_p3_rddata; +wire sdram_master_p3_rddata_valid; +wire sdram_sel; +wire sdram_cke; +wire sdram_odt; +wire sdram_reset_n; +reg [3:0] sdram_storage = 4'd1; +reg sdram_re = 1'd0; +reg [5:0] sdram_phaseinjector0_command_storage = 6'd0; +reg sdram_phaseinjector0_command_re = 1'd0; +wire sdram_phaseinjector0_command_issue_re; +wire sdram_phaseinjector0_command_issue_r; +wire sdram_phaseinjector0_command_issue_we; +reg sdram_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] sdram_phaseinjector0_address_storage = 14'd0; +reg sdram_phaseinjector0_address_re = 1'd0; +reg [2:0] sdram_phaseinjector0_baddress_storage = 3'd0; +reg sdram_phaseinjector0_baddress_re = 1'd0; +reg [31:0] sdram_phaseinjector0_wrdata_storage = 32'd0; +reg sdram_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] sdram_phaseinjector0_rddata_status = 32'd0; +wire sdram_phaseinjector0_rddata_we; +reg sdram_phaseinjector0_rddata_re = 1'd0; +reg [5:0] sdram_phaseinjector1_command_storage = 6'd0; +reg sdram_phaseinjector1_command_re = 1'd0; +wire sdram_phaseinjector1_command_issue_re; +wire sdram_phaseinjector1_command_issue_r; +wire sdram_phaseinjector1_command_issue_we; +reg sdram_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] sdram_phaseinjector1_address_storage = 14'd0; +reg sdram_phaseinjector1_address_re = 1'd0; +reg [2:0] sdram_phaseinjector1_baddress_storage = 3'd0; +reg sdram_phaseinjector1_baddress_re = 1'd0; +reg [31:0] sdram_phaseinjector1_wrdata_storage = 32'd0; +reg sdram_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] sdram_phaseinjector1_rddata_status = 32'd0; +wire sdram_phaseinjector1_rddata_we; +reg sdram_phaseinjector1_rddata_re = 1'd0; +reg [5:0] sdram_phaseinjector2_command_storage = 6'd0; +reg sdram_phaseinjector2_command_re = 1'd0; +wire sdram_phaseinjector2_command_issue_re; +wire sdram_phaseinjector2_command_issue_r; +wire sdram_phaseinjector2_command_issue_we; +reg sdram_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] sdram_phaseinjector2_address_storage = 14'd0; +reg sdram_phaseinjector2_address_re = 1'd0; +reg [2:0] sdram_phaseinjector2_baddress_storage = 3'd0; +reg sdram_phaseinjector2_baddress_re = 1'd0; +reg [31:0] sdram_phaseinjector2_wrdata_storage = 32'd0; +reg sdram_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] sdram_phaseinjector2_rddata_status = 32'd0; +wire sdram_phaseinjector2_rddata_we; +reg sdram_phaseinjector2_rddata_re = 1'd0; +reg [5:0] sdram_phaseinjector3_command_storage = 6'd0; +reg sdram_phaseinjector3_command_re = 1'd0; +wire sdram_phaseinjector3_command_issue_re; +wire sdram_phaseinjector3_command_issue_r; +wire sdram_phaseinjector3_command_issue_we; +reg sdram_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] sdram_phaseinjector3_address_storage = 14'd0; +reg sdram_phaseinjector3_address_re = 1'd0; +reg [2:0] sdram_phaseinjector3_baddress_storage = 3'd0; +reg sdram_phaseinjector3_baddress_re = 1'd0; +reg [31:0] sdram_phaseinjector3_wrdata_storage = 32'd0; +reg sdram_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] sdram_phaseinjector3_rddata_status = 32'd0; +wire sdram_phaseinjector3_rddata_we; +reg sdram_phaseinjector3_rddata_re = 1'd0; +wire sdram_interface_bank0_valid; +wire sdram_interface_bank0_ready; +wire sdram_interface_bank0_we; +wire [20:0] sdram_interface_bank0_addr; +wire sdram_interface_bank0_lock; +wire sdram_interface_bank0_wdata_ready; +wire sdram_interface_bank0_rdata_valid; +wire sdram_interface_bank1_valid; +wire sdram_interface_bank1_ready; +wire sdram_interface_bank1_we; +wire [20:0] sdram_interface_bank1_addr; +wire sdram_interface_bank1_lock; +wire sdram_interface_bank1_wdata_ready; +wire sdram_interface_bank1_rdata_valid; +wire sdram_interface_bank2_valid; +wire sdram_interface_bank2_ready; +wire sdram_interface_bank2_we; +wire [20:0] sdram_interface_bank2_addr; +wire sdram_interface_bank2_lock; +wire sdram_interface_bank2_wdata_ready; +wire sdram_interface_bank2_rdata_valid; +wire sdram_interface_bank3_valid; +wire sdram_interface_bank3_ready; +wire sdram_interface_bank3_we; +wire [20:0] sdram_interface_bank3_addr; +wire sdram_interface_bank3_lock; +wire sdram_interface_bank3_wdata_ready; +wire sdram_interface_bank3_rdata_valid; +wire sdram_interface_bank4_valid; +wire sdram_interface_bank4_ready; +wire sdram_interface_bank4_we; +wire [20:0] sdram_interface_bank4_addr; +wire sdram_interface_bank4_lock; +wire sdram_interface_bank4_wdata_ready; +wire sdram_interface_bank4_rdata_valid; +wire sdram_interface_bank5_valid; +wire sdram_interface_bank5_ready; +wire sdram_interface_bank5_we; +wire [20:0] sdram_interface_bank5_addr; +wire sdram_interface_bank5_lock; +wire sdram_interface_bank5_wdata_ready; +wire sdram_interface_bank5_rdata_valid; +wire sdram_interface_bank6_valid; +wire sdram_interface_bank6_ready; +wire sdram_interface_bank6_we; +wire [20:0] sdram_interface_bank6_addr; +wire sdram_interface_bank6_lock; +wire sdram_interface_bank6_wdata_ready; +wire sdram_interface_bank6_rdata_valid; +wire sdram_interface_bank7_valid; +wire sdram_interface_bank7_ready; +wire sdram_interface_bank7_we; +wire [20:0] sdram_interface_bank7_addr; +wire sdram_interface_bank7_lock; +wire sdram_interface_bank7_wdata_ready; +wire sdram_interface_bank7_rdata_valid; +reg [127:0] sdram_interface_wdata = 128'd0; +reg [15:0] sdram_interface_wdata_we = 16'd0; +wire [127:0] sdram_interface_rdata; +reg [13:0] sdram_dfi_p0_address = 14'd0; +reg [2:0] sdram_dfi_p0_bank = 3'd0; +reg sdram_dfi_p0_cas_n = 1'd1; +reg sdram_dfi_p0_cs_n = 1'd1; +reg sdram_dfi_p0_ras_n = 1'd1; +reg sdram_dfi_p0_we_n = 1'd1; +wire sdram_dfi_p0_cke; +wire sdram_dfi_p0_odt; +wire sdram_dfi_p0_reset_n; +reg sdram_dfi_p0_act_n = 1'd1; +wire [31:0] sdram_dfi_p0_wrdata; +reg sdram_dfi_p0_wrdata_en = 1'd0; +wire [3:0] sdram_dfi_p0_wrdata_mask; +reg sdram_dfi_p0_rddata_en = 1'd0; +wire [31:0] sdram_dfi_p0_rddata; +wire sdram_dfi_p0_rddata_valid; +reg [13:0] sdram_dfi_p1_address = 14'd0; +reg [2:0] sdram_dfi_p1_bank = 3'd0; +reg sdram_dfi_p1_cas_n = 1'd1; +reg sdram_dfi_p1_cs_n = 1'd1; +reg sdram_dfi_p1_ras_n = 1'd1; +reg sdram_dfi_p1_we_n = 1'd1; +wire sdram_dfi_p1_cke; +wire sdram_dfi_p1_odt; +wire sdram_dfi_p1_reset_n; +reg sdram_dfi_p1_act_n = 1'd1; +wire [31:0] sdram_dfi_p1_wrdata; +reg sdram_dfi_p1_wrdata_en = 1'd0; +wire [3:0] sdram_dfi_p1_wrdata_mask; +reg sdram_dfi_p1_rddata_en = 1'd0; +wire [31:0] sdram_dfi_p1_rddata; +wire sdram_dfi_p1_rddata_valid; +reg [13:0] sdram_dfi_p2_address = 14'd0; +reg [2:0] sdram_dfi_p2_bank = 3'd0; +reg sdram_dfi_p2_cas_n = 1'd1; +reg sdram_dfi_p2_cs_n = 1'd1; +reg sdram_dfi_p2_ras_n = 1'd1; +reg sdram_dfi_p2_we_n = 1'd1; +wire sdram_dfi_p2_cke; +wire sdram_dfi_p2_odt; +wire sdram_dfi_p2_reset_n; +reg sdram_dfi_p2_act_n = 1'd1; +wire [31:0] sdram_dfi_p2_wrdata; +reg sdram_dfi_p2_wrdata_en = 1'd0; +wire [3:0] sdram_dfi_p2_wrdata_mask; +reg sdram_dfi_p2_rddata_en = 1'd0; +wire [31:0] sdram_dfi_p2_rddata; +wire sdram_dfi_p2_rddata_valid; +reg [13:0] sdram_dfi_p3_address = 14'd0; +reg [2:0] sdram_dfi_p3_bank = 3'd0; +reg sdram_dfi_p3_cas_n = 1'd1; +reg sdram_dfi_p3_cs_n = 1'd1; +reg sdram_dfi_p3_ras_n = 1'd1; +reg sdram_dfi_p3_we_n = 1'd1; +wire sdram_dfi_p3_cke; +wire sdram_dfi_p3_odt; +wire sdram_dfi_p3_reset_n; +reg sdram_dfi_p3_act_n = 1'd1; +wire [31:0] sdram_dfi_p3_wrdata; +reg sdram_dfi_p3_wrdata_en = 1'd0; +wire [3:0] sdram_dfi_p3_wrdata_mask; +reg sdram_dfi_p3_rddata_en = 1'd0; +wire [31:0] sdram_dfi_p3_rddata; +wire sdram_dfi_p3_rddata_valid; +reg sdram_cmd_valid = 1'd0; +reg sdram_cmd_ready = 1'd0; +reg sdram_cmd_last = 1'd0; +reg [13:0] sdram_cmd_payload_a = 14'd0; +reg [2:0] sdram_cmd_payload_ba = 3'd0; +reg sdram_cmd_payload_cas = 1'd0; +reg sdram_cmd_payload_ras = 1'd0; +reg sdram_cmd_payload_we = 1'd0; +reg sdram_cmd_payload_is_read = 1'd0; +reg sdram_cmd_payload_is_write = 1'd0; +wire sdram_wants_refresh; +wire sdram_wants_zqcs; +wire sdram_timer_wait; +wire sdram_timer_done0; +wire [9:0] sdram_timer_count0; +wire sdram_timer_done1; +reg [9:0] sdram_timer_count1 = 10'd624; +wire sdram_postponer_req_i; +reg sdram_postponer_req_o = 1'd0; +reg sdram_postponer_count = 1'd0; +reg sdram_sequencer_start0 = 1'd0; +wire sdram_sequencer_done0; +wire sdram_sequencer_start1; +reg sdram_sequencer_done1 = 1'd0; +reg [5:0] sdram_sequencer_counter = 6'd0; +reg sdram_sequencer_count = 1'd0; +wire sdram_zqcs_timer_wait; +wire sdram_zqcs_timer_done0; +wire [26:0] sdram_zqcs_timer_count0; +wire sdram_zqcs_timer_done1; +reg [26:0] sdram_zqcs_timer_count1 = 27'd79999999; +reg sdram_zqcs_executer_start = 1'd0; +reg sdram_zqcs_executer_done = 1'd0; +reg [4:0] sdram_zqcs_executer_counter = 5'd0; +wire sdram_bankmachine0_req_valid; +wire sdram_bankmachine0_req_ready; +wire sdram_bankmachine0_req_we; +wire [20:0] sdram_bankmachine0_req_addr; +wire sdram_bankmachine0_req_lock; +reg sdram_bankmachine0_req_wdata_ready = 1'd0; +reg sdram_bankmachine0_req_rdata_valid = 1'd0; +wire sdram_bankmachine0_refresh_req; +reg sdram_bankmachine0_refresh_gnt = 1'd0; +reg sdram_bankmachine0_cmd_valid = 1'd0; +reg sdram_bankmachine0_cmd_ready = 1'd0; +reg [13:0] sdram_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] sdram_bankmachine0_cmd_payload_ba; +reg sdram_bankmachine0_cmd_payload_cas = 1'd0; +reg sdram_bankmachine0_cmd_payload_ras = 1'd0; +reg sdram_bankmachine0_cmd_payload_we = 1'd0; +reg sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine0_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine0_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine0_auto_precharge = 1'd0; +wire sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [20:0] sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine0_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine0_cmd_buffer_sink_valid; +wire sdram_bankmachine0_cmd_buffer_sink_ready; +wire sdram_bankmachine0_cmd_buffer_sink_first; +wire sdram_bankmachine0_cmd_buffer_sink_last; +wire sdram_bankmachine0_cmd_buffer_sink_payload_we; +wire [20:0] sdram_bankmachine0_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine0_cmd_buffer_source_ready; +reg sdram_bankmachine0_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine0_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] sdram_bankmachine0_row = 14'd0; +reg sdram_bankmachine0_row_opened = 1'd0; +wire sdram_bankmachine0_row_hit; +reg sdram_bankmachine0_row_open = 1'd0; +reg sdram_bankmachine0_row_close = 1'd0; +reg sdram_bankmachine0_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine0_twtpcon_count = 3'd0; +wire sdram_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine0_trccon_ready = 1'd0; +reg [2:0] sdram_bankmachine0_trccon_count = 3'd0; +wire sdram_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine0_trascon_ready = 1'd0; +reg [1:0] sdram_bankmachine0_trascon_count = 2'd0; +wire sdram_bankmachine1_req_valid; +wire sdram_bankmachine1_req_ready; +wire sdram_bankmachine1_req_we; +wire [20:0] sdram_bankmachine1_req_addr; +wire sdram_bankmachine1_req_lock; +reg sdram_bankmachine1_req_wdata_ready = 1'd0; +reg sdram_bankmachine1_req_rdata_valid = 1'd0; +wire sdram_bankmachine1_refresh_req; +reg sdram_bankmachine1_refresh_gnt = 1'd0; +reg sdram_bankmachine1_cmd_valid = 1'd0; +reg sdram_bankmachine1_cmd_ready = 1'd0; +reg [13:0] sdram_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] sdram_bankmachine1_cmd_payload_ba; +reg sdram_bankmachine1_cmd_payload_cas = 1'd0; +reg sdram_bankmachine1_cmd_payload_ras = 1'd0; +reg sdram_bankmachine1_cmd_payload_we = 1'd0; +reg sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine1_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine1_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine1_auto_precharge = 1'd0; +wire sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [20:0] sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [3:0] sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine1_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine1_cmd_buffer_sink_valid; +wire sdram_bankmachine1_cmd_buffer_sink_ready; +wire sdram_bankmachine1_cmd_buffer_sink_first; +wire sdram_bankmachine1_cmd_buffer_sink_last; +wire sdram_bankmachine1_cmd_buffer_sink_payload_we; +wire [20:0] sdram_bankmachine1_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine1_cmd_buffer_source_ready; +reg sdram_bankmachine1_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine1_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] sdram_bankmachine1_row = 14'd0; +reg sdram_bankmachine1_row_opened = 1'd0; +wire sdram_bankmachine1_row_hit; +reg sdram_bankmachine1_row_open = 1'd0; +reg sdram_bankmachine1_row_close = 1'd0; +reg sdram_bankmachine1_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine1_twtpcon_count = 3'd0; +wire sdram_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine1_trccon_ready = 1'd0; +reg [2:0] sdram_bankmachine1_trccon_count = 3'd0; +wire sdram_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine1_trascon_ready = 1'd0; +reg [1:0] sdram_bankmachine1_trascon_count = 2'd0; +wire sdram_bankmachine2_req_valid; +wire sdram_bankmachine2_req_ready; +wire sdram_bankmachine2_req_we; +wire [20:0] sdram_bankmachine2_req_addr; +wire sdram_bankmachine2_req_lock; +reg sdram_bankmachine2_req_wdata_ready = 1'd0; +reg sdram_bankmachine2_req_rdata_valid = 1'd0; +wire sdram_bankmachine2_refresh_req; +reg sdram_bankmachine2_refresh_gnt = 1'd0; +reg sdram_bankmachine2_cmd_valid = 1'd0; +reg sdram_bankmachine2_cmd_ready = 1'd0; +reg [13:0] sdram_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] sdram_bankmachine2_cmd_payload_ba; +reg sdram_bankmachine2_cmd_payload_cas = 1'd0; +reg sdram_bankmachine2_cmd_payload_ras = 1'd0; +reg sdram_bankmachine2_cmd_payload_we = 1'd0; +reg sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine2_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine2_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine2_auto_precharge = 1'd0; +wire sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [20:0] sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [3:0] sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine2_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine2_cmd_buffer_sink_valid; +wire sdram_bankmachine2_cmd_buffer_sink_ready; +wire sdram_bankmachine2_cmd_buffer_sink_first; +wire sdram_bankmachine2_cmd_buffer_sink_last; +wire sdram_bankmachine2_cmd_buffer_sink_payload_we; +wire [20:0] sdram_bankmachine2_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine2_cmd_buffer_source_ready; +reg sdram_bankmachine2_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine2_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] sdram_bankmachine2_row = 14'd0; +reg sdram_bankmachine2_row_opened = 1'd0; +wire sdram_bankmachine2_row_hit; +reg sdram_bankmachine2_row_open = 1'd0; +reg sdram_bankmachine2_row_close = 1'd0; +reg sdram_bankmachine2_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine2_twtpcon_count = 3'd0; +wire sdram_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine2_trccon_ready = 1'd0; +reg [2:0] sdram_bankmachine2_trccon_count = 3'd0; +wire sdram_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine2_trascon_ready = 1'd0; +reg [1:0] sdram_bankmachine2_trascon_count = 2'd0; +wire sdram_bankmachine3_req_valid; +wire sdram_bankmachine3_req_ready; +wire sdram_bankmachine3_req_we; +wire [20:0] sdram_bankmachine3_req_addr; +wire sdram_bankmachine3_req_lock; +reg sdram_bankmachine3_req_wdata_ready = 1'd0; +reg sdram_bankmachine3_req_rdata_valid = 1'd0; +wire sdram_bankmachine3_refresh_req; +reg sdram_bankmachine3_refresh_gnt = 1'd0; +reg sdram_bankmachine3_cmd_valid = 1'd0; +reg sdram_bankmachine3_cmd_ready = 1'd0; +reg [13:0] sdram_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] sdram_bankmachine3_cmd_payload_ba; +reg sdram_bankmachine3_cmd_payload_cas = 1'd0; +reg sdram_bankmachine3_cmd_payload_ras = 1'd0; +reg sdram_bankmachine3_cmd_payload_we = 1'd0; +reg sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine3_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine3_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine3_auto_precharge = 1'd0; +wire sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [20:0] sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [3:0] sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine3_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine3_cmd_buffer_sink_valid; +wire sdram_bankmachine3_cmd_buffer_sink_ready; +wire sdram_bankmachine3_cmd_buffer_sink_first; +wire sdram_bankmachine3_cmd_buffer_sink_last; +wire sdram_bankmachine3_cmd_buffer_sink_payload_we; +wire [20:0] sdram_bankmachine3_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine3_cmd_buffer_source_ready; +reg sdram_bankmachine3_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine3_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] sdram_bankmachine3_row = 14'd0; +reg sdram_bankmachine3_row_opened = 1'd0; +wire sdram_bankmachine3_row_hit; +reg sdram_bankmachine3_row_open = 1'd0; +reg sdram_bankmachine3_row_close = 1'd0; +reg sdram_bankmachine3_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine3_twtpcon_count = 3'd0; +wire sdram_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine3_trccon_ready = 1'd0; +reg [2:0] sdram_bankmachine3_trccon_count = 3'd0; +wire sdram_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine3_trascon_ready = 1'd0; +reg [1:0] sdram_bankmachine3_trascon_count = 2'd0; +wire sdram_bankmachine4_req_valid; +wire sdram_bankmachine4_req_ready; +wire sdram_bankmachine4_req_we; +wire [20:0] sdram_bankmachine4_req_addr; +wire sdram_bankmachine4_req_lock; +reg sdram_bankmachine4_req_wdata_ready = 1'd0; +reg sdram_bankmachine4_req_rdata_valid = 1'd0; +wire sdram_bankmachine4_refresh_req; +reg sdram_bankmachine4_refresh_gnt = 1'd0; +reg sdram_bankmachine4_cmd_valid = 1'd0; +reg sdram_bankmachine4_cmd_ready = 1'd0; +reg [13:0] sdram_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] sdram_bankmachine4_cmd_payload_ba; +reg sdram_bankmachine4_cmd_payload_cas = 1'd0; +reg sdram_bankmachine4_cmd_payload_ras = 1'd0; +reg sdram_bankmachine4_cmd_payload_we = 1'd0; +reg sdram_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine4_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine4_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine4_auto_precharge = 1'd0; +wire sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine4_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine4_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine4_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [20:0] sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [3:0] sdram_bankmachine4_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine4_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine4_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine4_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine4_cmd_buffer_sink_valid; +wire sdram_bankmachine4_cmd_buffer_sink_ready; +wire sdram_bankmachine4_cmd_buffer_sink_first; +wire sdram_bankmachine4_cmd_buffer_sink_last; +wire sdram_bankmachine4_cmd_buffer_sink_payload_we; +wire [20:0] sdram_bankmachine4_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine4_cmd_buffer_source_ready; +reg sdram_bankmachine4_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine4_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] sdram_bankmachine4_row = 14'd0; +reg sdram_bankmachine4_row_opened = 1'd0; +wire sdram_bankmachine4_row_hit; +reg sdram_bankmachine4_row_open = 1'd0; +reg sdram_bankmachine4_row_close = 1'd0; +reg sdram_bankmachine4_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine4_twtpcon_count = 3'd0; +wire sdram_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine4_trccon_ready = 1'd0; +reg [2:0] sdram_bankmachine4_trccon_count = 3'd0; +wire sdram_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine4_trascon_ready = 1'd0; +reg [1:0] sdram_bankmachine4_trascon_count = 2'd0; +wire sdram_bankmachine5_req_valid; +wire sdram_bankmachine5_req_ready; +wire sdram_bankmachine5_req_we; +wire [20:0] sdram_bankmachine5_req_addr; +wire sdram_bankmachine5_req_lock; +reg sdram_bankmachine5_req_wdata_ready = 1'd0; +reg sdram_bankmachine5_req_rdata_valid = 1'd0; +wire sdram_bankmachine5_refresh_req; +reg sdram_bankmachine5_refresh_gnt = 1'd0; +reg sdram_bankmachine5_cmd_valid = 1'd0; +reg sdram_bankmachine5_cmd_ready = 1'd0; +reg [13:0] sdram_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] sdram_bankmachine5_cmd_payload_ba; +reg sdram_bankmachine5_cmd_payload_cas = 1'd0; +reg sdram_bankmachine5_cmd_payload_ras = 1'd0; +reg sdram_bankmachine5_cmd_payload_we = 1'd0; +reg sdram_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine5_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine5_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine5_auto_precharge = 1'd0; +wire sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine5_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine5_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine5_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [20:0] sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [3:0] sdram_bankmachine5_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine5_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine5_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine5_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine5_cmd_buffer_sink_valid; +wire sdram_bankmachine5_cmd_buffer_sink_ready; +wire sdram_bankmachine5_cmd_buffer_sink_first; +wire sdram_bankmachine5_cmd_buffer_sink_last; +wire sdram_bankmachine5_cmd_buffer_sink_payload_we; +wire [20:0] sdram_bankmachine5_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine5_cmd_buffer_source_ready; +reg sdram_bankmachine5_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine5_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] sdram_bankmachine5_row = 14'd0; +reg sdram_bankmachine5_row_opened = 1'd0; +wire sdram_bankmachine5_row_hit; +reg sdram_bankmachine5_row_open = 1'd0; +reg sdram_bankmachine5_row_close = 1'd0; +reg sdram_bankmachine5_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine5_twtpcon_count = 3'd0; +wire sdram_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine5_trccon_ready = 1'd0; +reg [2:0] sdram_bankmachine5_trccon_count = 3'd0; +wire sdram_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine5_trascon_ready = 1'd0; +reg [1:0] sdram_bankmachine5_trascon_count = 2'd0; +wire sdram_bankmachine6_req_valid; +wire sdram_bankmachine6_req_ready; +wire sdram_bankmachine6_req_we; +wire [20:0] sdram_bankmachine6_req_addr; +wire sdram_bankmachine6_req_lock; +reg sdram_bankmachine6_req_wdata_ready = 1'd0; +reg sdram_bankmachine6_req_rdata_valid = 1'd0; +wire sdram_bankmachine6_refresh_req; +reg sdram_bankmachine6_refresh_gnt = 1'd0; +reg sdram_bankmachine6_cmd_valid = 1'd0; +reg sdram_bankmachine6_cmd_ready = 1'd0; +reg [13:0] sdram_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] sdram_bankmachine6_cmd_payload_ba; +reg sdram_bankmachine6_cmd_payload_cas = 1'd0; +reg sdram_bankmachine6_cmd_payload_ras = 1'd0; +reg sdram_bankmachine6_cmd_payload_we = 1'd0; +reg sdram_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine6_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine6_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine6_auto_precharge = 1'd0; +wire sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine6_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine6_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine6_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [20:0] sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [3:0] sdram_bankmachine6_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine6_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine6_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine6_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine6_cmd_buffer_sink_valid; +wire sdram_bankmachine6_cmd_buffer_sink_ready; +wire sdram_bankmachine6_cmd_buffer_sink_first; +wire sdram_bankmachine6_cmd_buffer_sink_last; +wire sdram_bankmachine6_cmd_buffer_sink_payload_we; +wire [20:0] sdram_bankmachine6_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine6_cmd_buffer_source_ready; +reg sdram_bankmachine6_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine6_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] sdram_bankmachine6_row = 14'd0; +reg sdram_bankmachine6_row_opened = 1'd0; +wire sdram_bankmachine6_row_hit; +reg sdram_bankmachine6_row_open = 1'd0; +reg sdram_bankmachine6_row_close = 1'd0; +reg sdram_bankmachine6_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine6_twtpcon_count = 3'd0; +wire sdram_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine6_trccon_ready = 1'd0; +reg [2:0] sdram_bankmachine6_trccon_count = 3'd0; +wire sdram_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine6_trascon_ready = 1'd0; +reg [1:0] sdram_bankmachine6_trascon_count = 2'd0; +wire sdram_bankmachine7_req_valid; +wire sdram_bankmachine7_req_ready; +wire sdram_bankmachine7_req_we; +wire [20:0] sdram_bankmachine7_req_addr; +wire sdram_bankmachine7_req_lock; +reg sdram_bankmachine7_req_wdata_ready = 1'd0; +reg sdram_bankmachine7_req_rdata_valid = 1'd0; +wire sdram_bankmachine7_refresh_req; +reg sdram_bankmachine7_refresh_gnt = 1'd0; +reg sdram_bankmachine7_cmd_valid = 1'd0; +reg sdram_bankmachine7_cmd_ready = 1'd0; +reg [13:0] sdram_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] sdram_bankmachine7_cmd_payload_ba; +reg sdram_bankmachine7_cmd_payload_cas = 1'd0; +reg sdram_bankmachine7_cmd_payload_ras = 1'd0; +reg sdram_bankmachine7_cmd_payload_we = 1'd0; +reg sdram_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine7_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine7_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine7_auto_precharge = 1'd0; +wire sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine7_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine7_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine7_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [20:0] sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [3:0] sdram_bankmachine7_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine7_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine7_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine7_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine7_cmd_buffer_sink_valid; +wire sdram_bankmachine7_cmd_buffer_sink_ready; +wire sdram_bankmachine7_cmd_buffer_sink_first; +wire sdram_bankmachine7_cmd_buffer_sink_last; +wire sdram_bankmachine7_cmd_buffer_sink_payload_we; +wire [20:0] sdram_bankmachine7_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine7_cmd_buffer_source_ready; +reg sdram_bankmachine7_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine7_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] sdram_bankmachine7_row = 14'd0; +reg sdram_bankmachine7_row_opened = 1'd0; +wire sdram_bankmachine7_row_hit; +reg sdram_bankmachine7_row_open = 1'd0; +reg sdram_bankmachine7_row_close = 1'd0; +reg sdram_bankmachine7_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine7_twtpcon_count = 3'd0; +wire sdram_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine7_trccon_ready = 1'd0; +reg [2:0] sdram_bankmachine7_trccon_count = 3'd0; +wire sdram_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg sdram_bankmachine7_trascon_ready = 1'd0; +reg [1:0] sdram_bankmachine7_trascon_count = 2'd0; +wire sdram_ras_allowed; +wire sdram_cas_allowed; +wire [1:0] sdram_rdcmdphase; +wire [1:0] sdram_wrcmdphase; +reg sdram_choose_cmd_want_reads = 1'd0; +reg sdram_choose_cmd_want_writes = 1'd0; +reg sdram_choose_cmd_want_cmds = 1'd0; +reg sdram_choose_cmd_want_activates = 1'd0; +wire sdram_choose_cmd_cmd_valid; +reg sdram_choose_cmd_cmd_ready = 1'd0; +wire [13:0] sdram_choose_cmd_cmd_payload_a; +wire [2:0] sdram_choose_cmd_cmd_payload_ba; +reg sdram_choose_cmd_cmd_payload_cas = 1'd0; +reg sdram_choose_cmd_cmd_payload_ras = 1'd0; +reg sdram_choose_cmd_cmd_payload_we = 1'd0; +wire sdram_choose_cmd_cmd_payload_is_cmd; +wire sdram_choose_cmd_cmd_payload_is_read; +wire sdram_choose_cmd_cmd_payload_is_write; +reg [7:0] sdram_choose_cmd_valids = 8'd0; +wire [7:0] sdram_choose_cmd_request; +reg [2:0] sdram_choose_cmd_grant = 3'd0; +wire sdram_choose_cmd_ce; +reg sdram_choose_req_want_reads = 1'd0; +reg sdram_choose_req_want_writes = 1'd0; +reg sdram_choose_req_want_cmds = 1'd0; +reg sdram_choose_req_want_activates = 1'd0; +wire sdram_choose_req_cmd_valid; +reg sdram_choose_req_cmd_ready = 1'd0; +wire [13:0] sdram_choose_req_cmd_payload_a; +wire [2:0] sdram_choose_req_cmd_payload_ba; +reg sdram_choose_req_cmd_payload_cas = 1'd0; +reg sdram_choose_req_cmd_payload_ras = 1'd0; +reg sdram_choose_req_cmd_payload_we = 1'd0; +wire sdram_choose_req_cmd_payload_is_cmd; +wire sdram_choose_req_cmd_payload_is_read; +wire sdram_choose_req_cmd_payload_is_write; +reg [7:0] sdram_choose_req_valids = 8'd0; +wire [7:0] sdram_choose_req_request; +reg [2:0] sdram_choose_req_grant = 3'd0; +wire sdram_choose_req_ce; +reg [13:0] sdram_nop_a = 14'd0; +reg [2:0] sdram_nop_ba = 3'd0; +reg [1:0] sdram_steerer_sel0 = 2'd0; +reg [1:0] sdram_steerer_sel1 = 2'd0; +reg [1:0] sdram_steerer_sel2 = 2'd0; +reg [1:0] sdram_steerer_sel3 = 2'd0; +reg sdram_steerer0 = 1'd1; +reg sdram_steerer1 = 1'd1; +reg sdram_steerer2 = 1'd1; +reg sdram_steerer3 = 1'd1; +reg sdram_steerer4 = 1'd1; +reg sdram_steerer5 = 1'd1; +reg sdram_steerer6 = 1'd1; +reg sdram_steerer7 = 1'd1; +wire sdram_trrdcon_valid; +(* dont_touch = "true" *) reg sdram_trrdcon_ready = 1'd0; +reg sdram_trrdcon_count = 1'd0; +wire sdram_tfawcon_valid; +(* dont_touch = "true" *) reg sdram_tfawcon_ready = 1'd1; +wire [1:0] sdram_tfawcon_count; +reg [3:0] sdram_tfawcon_window = 4'd0; +wire sdram_tccdcon_valid; +(* dont_touch = "true" *) reg sdram_tccdcon_ready = 1'd0; +reg sdram_tccdcon_count = 1'd0; +wire sdram_twtrcon_valid; +(* dont_touch = "true" *) reg sdram_twtrcon_ready = 1'd0; +reg [2:0] sdram_twtrcon_count = 3'd0; +wire sdram_read_available; +wire sdram_write_available; +reg sdram_en0 = 1'd0; +wire sdram_max_time0; +reg [4:0] sdram_time0 = 5'd0; +reg sdram_en1 = 1'd0; +wire sdram_max_time1; +reg [3:0] sdram_time1 = 4'd0; +wire sdram_go_to_refresh; +wire port_flush; +wire port_cmd_valid; +wire port_cmd_ready; +wire port_cmd_last; +wire port_cmd_payload_we; +wire [23:0] port_cmd_payload_addr; +wire port_wdata_valid; +wire port_wdata_ready; +wire [127:0] port_wdata_payload_data; +wire [15:0] port_wdata_payload_we; +wire port_rdata_valid; +wire port_rdata_ready; +wire [127:0] port_rdata_payload_data; +wire [29:0] wb_sdram_adr; +wire [31:0] wb_sdram_dat_w; +reg [31:0] wb_sdram_dat_r = 32'd0; +wire [3:0] wb_sdram_sel; +wire wb_sdram_cyc; +wire wb_sdram_stb; +reg wb_sdram_ack = 1'd0; +wire wb_sdram_we; +wire [2:0] wb_sdram_cti; +wire [1:0] wb_sdram_bte; +reg wb_sdram_err = 1'd0; +wire [29:0] interface_adr; +wire [127:0] interface_dat_w; +wire [127:0] interface_dat_r; +wire [15:0] interface_sel; +reg interface_cyc = 1'd0; +reg interface_stb = 1'd0; +wire interface_ack; +reg interface_we = 1'd0; +wire [8:0] data_port_adr; +wire [127:0] data_port_dat_r; +reg [15:0] data_port_we = 16'd0; +reg [127:0] data_port_dat_w = 128'd0; +reg write_from_slave = 1'd0; +reg [1:0] adr_offset_r = 2'd0; +wire [8:0] tag_port_adr; +wire [23:0] tag_port_dat_r; +reg tag_port_we = 1'd0; +wire [23:0] tag_port_dat_w; +wire [22:0] tag_do_tag; +wire tag_do_dirty; +wire [22:0] tag_di_tag; +reg tag_di_dirty = 1'd0; +reg word_clr = 1'd0; +reg word_inc = 1'd0; +reg cmd_consumed = 1'd0; +reg wdata_consumed = 1'd0; +wire ack_cmd; +wire ack_wdata; +wire ack_rdata; +wire enable; +wire ready; +wire a7litesataphy_ready; +reg a7litesataphy_tx_idle = 1'd0; +reg a7litesataphy_tx_polarity = 1'd0; +reg a7litesataphy_tx_cominit_stb = 1'd0; +wire a7litesataphy_tx_cominit_ack; +reg a7litesataphy_tx_comwake_stb = 1'd0; +wire a7litesataphy_tx_comwake_ack; +reg a7litesataphy_rx_idle = 1'd0; +reg a7litesataphy_rx_cdrhold = 1'd0; +reg a7litesataphy_rx_polarity = 1'd0; +wire a7litesataphy_rx_cominit_stb; +wire a7litesataphy_rx_comwake_stb; +wire [1:0] a7litesataphy_rxdisperr0; +wire [1:0] a7litesataphy_rxnotintable0; +wire a7litesataphy_sink_valid; +reg a7litesataphy_sink_ready = 1'd0; +wire a7litesataphy_sink_first; +wire a7litesataphy_sink_last; +wire [15:0] a7litesataphy_sink_payload_data; +wire [1:0] a7litesataphy_sink_payload_charisk; +reg a7litesataphy_source_valid = 1'd0; +wire a7litesataphy_source_ready; +reg a7litesataphy_source_first = 1'd0; +reg a7litesataphy_source_last = 1'd0; +reg [15:0] a7litesataphy_source_payload_data = 16'd0; +reg [1:0] a7litesataphy_source_payload_charisk = 2'd0; +wire a7litesataphy_gtrefclk0; +wire a7litesataphy_qplllock; +wire [1:0] a7litesataphy_rxcharisk; +wire [15:0] a7litesataphy_rxdata; +wire a7litesataphy_rxoutclk; +wire a7litesataphy_rxusrclk; +wire a7litesataphy_rxusrclk2; +wire a7litesataphy_rxcominitdet0; +wire a7litesataphy_rxcomwakedet0; +reg [1:0] a7litesataphy_txcharisk = 2'd0; +reg [15:0] a7litesataphy_txdata = 16'd0; +wire a7litesataphy_txoutclk; +wire a7litesataphy_txusrclk; +wire a7litesataphy_txusrclk2; +wire a7litesataphy_txelecidle0; +wire a7litesataphy_txcomfinish0; +wire a7litesataphy_txcominit0; +wire a7litesataphy_txcomwake0; +reg a7litesataphy_rxpd = 1'd0; +reg a7litesataphy_txpd0 = 1'd0; +reg a7litesataphy_tx_init_done = 1'd0; +wire a7litesataphy_tx_init_restart; +wire a7litesataphy_tx_init_plllock0; +reg a7litesataphy_tx_init_pllreset = 1'd0; +reg a7litesataphy_tx_init_gttxreset0 = 1'd0; +reg a7litesataphy_tx_init_gttxpd0 = 1'd0; +wire a7litesataphy_tx_init_txresetdone0; +reg a7litesataphy_tx_init_txdlysreset0 = 1'd0; +wire a7litesataphy_tx_init_txdlysresetdone0; +reg a7litesataphy_tx_init_txphinit0 = 1'd0; +wire a7litesataphy_tx_init_txphinitdone0; +reg a7litesataphy_tx_init_txphalign0 = 1'd0; +wire a7litesataphy_tx_init_txphaligndone0; +reg a7litesataphy_tx_init_txdlyen0 = 1'd0; +reg a7litesataphy_tx_init_txuserrdy0 = 1'd0; +reg a7litesataphy_tx_init_drp_start = 1'd0; +reg a7litesataphy_tx_init_drp_done = 1'd1; +wire a7litesataphy_tx_init_plllock1; +wire a7litesataphy_tx_init_txresetdone1; +wire a7litesataphy_tx_init_txdlysresetdone1; +wire a7litesataphy_tx_init_txphinitdone1; +wire a7litesataphy_tx_init_txphaligndone1; +reg a7litesataphy_tx_init_gttxreset1 = 1'd0; +reg a7litesataphy_tx_init_gttxpd1 = 1'd0; +reg a7litesataphy_tx_init_txdlysreset1 = 1'd0; +reg a7litesataphy_tx_init_txphinit1 = 1'd0; +reg a7litesataphy_tx_init_txphalign1 = 1'd0; +reg a7litesataphy_tx_init_txdlyen1 = 1'd0; +reg a7litesataphy_tx_init_txuserrdy1 = 1'd0; +reg a7litesataphy_tx_init_txphaligndone_r = 1'd1; +wire a7litesataphy_tx_init_txphaligndone_rising; +wire a7litesataphy_tx_init_reset; +wire a7litesataphy_tx_init_init_delay_wait; +wire a7litesataphy_tx_init_init_delay_done; +reg [5:0] a7litesataphy_tx_init_init_delay_count = 6'd40; +wire a7litesataphy_tx_init_watchdog_wait; +wire a7litesataphy_tx_init_watchdog_done; +reg [16:0] a7litesataphy_tx_init_watchdog_count = 17'd80000; +reg a7litesataphy_rx_init_done = 1'd0; +wire a7litesataphy_rx_init_restart; +wire a7litesataphy_rx_init_plllock0; +reg a7litesataphy_rx_init_gtrxreset0 = 1'd0; +reg a7litesataphy_rx_init_gtrxpd0 = 1'd0; +wire a7litesataphy_rx_init_rxresetdone0; +reg a7litesataphy_rx_init_rxdlysreset0 = 1'd0; +wire a7litesataphy_rx_init_rxdlysresetdone0; +reg a7litesataphy_rx_init_rxphalign0 = 1'd0; +reg a7litesataphy_rx_init_rxuserrdy0 = 1'd0; +wire a7litesataphy_rx_init_rxsyncdone0; +wire a7litesataphy_rx_init_rxpmaresetdone0; +wire a7litesataphy_rx_init_drp_clk; +reg a7litesataphy_rx_init_drp_en = 1'd0; +reg a7litesataphy_rx_init_drp_we = 1'd0; +wire a7litesataphy_rx_init_drp_rdy; +wire [8:0] a7litesataphy_rx_init_drp_addr; +reg [15:0] a7litesataphy_rx_init_drp_di = 16'd0; +wire [15:0] a7litesataphy_rx_init_drp_do; +reg [15:0] a7litesataphy_rx_init_drpvalue = 16'd0; +reg a7litesataphy_rx_init_drpmask = 1'd0; +wire a7litesataphy_rx_init_rxpmaresetdone1; +reg a7litesataphy_rx_init_rxpmaresetdone_r = 1'd0; +wire a7litesataphy_rx_init_plllock1; +wire a7litesataphy_rx_init_rxresetdone1; +wire a7litesataphy_rx_init_rxdlysresetdone1; +wire a7litesataphy_rx_init_rxsyncdone1; +reg a7litesataphy_rx_init_gtrxreset1 = 1'd0; +reg a7litesataphy_rx_init_gtrxpd1 = 1'd0; +reg a7litesataphy_rx_init_rxdlysreset1 = 1'd0; +reg a7litesataphy_rx_init_rxphalign1 = 1'd0; +reg a7litesataphy_rx_init_rxuserrdy1 = 1'd0; +wire a7litesataphy_rx_init_reset; +wire a7litesataphy_rx_init_init_delay_wait; +wire a7litesataphy_rx_init_init_delay_done; +reg [5:0] a7litesataphy_rx_init_init_delay_count = 6'd40; +wire a7litesataphy_rx_init_watchdog_wait; +wire a7litesataphy_rx_init_watchdog_done; +reg [18:0] a7litesataphy_rx_init_watchdog_count = 19'd320000; +reg a7litesataphy_i_d0 = 1'd0; +reg a7litesataphy_i_d1 = 1'd0; +wire a7litesataphy_txpd1; +wire a7litesataphy_txelecidle1; +wire a7litesataphy_txcominit1; +wire a7litesataphy_txcomwake1; +wire a7litesataphy_pulsesynchronizer0_i; +wire a7litesataphy_pulsesynchronizer0_o; +reg a7litesataphy_pulsesynchronizer0_toggle_i = 1'd0; +wire a7litesataphy_pulsesynchronizer0_toggle_o; +reg a7litesataphy_pulsesynchronizer0_toggle_o_r = 1'd0; +wire a7litesataphy_pulsesynchronizer1_i; +wire a7litesataphy_pulsesynchronizer1_o; +reg a7litesataphy_pulsesynchronizer1_toggle_i = 1'd0; +wire a7litesataphy_pulsesynchronizer1_toggle_o; +reg a7litesataphy_pulsesynchronizer1_toggle_o_r = 1'd0; +wire a7litesataphy_txcomfinish1; +wire a7litesataphy_pulsesynchronizer2_i; +wire a7litesataphy_pulsesynchronizer2_o; +reg a7litesataphy_pulsesynchronizer2_toggle_i = 1'd0; +wire a7litesataphy_pulsesynchronizer2_toggle_o; +reg a7litesataphy_pulsesynchronizer2_toggle_o_r = 1'd0; +wire a7litesataphy_rxcominitdet1; +wire a7litesataphy_rxcomwakedet1; +wire [1:0] a7litesataphy_rxdisperr1; +wire [1:0] a7litesataphy_rxnotintable1; +wire a7litesataphy_qpll_clk; +wire a7litesataphy_qpll_refclk; +wire a7litesataphy_qpll_reset; +wire a7litesataphy_qpll_lock; +reg a7litesataphy_qpll_drp_clk = 1'd0; +reg a7litesataphy_qpll_drp_en = 1'd0; +reg a7litesataphy_qpll_drp_we = 1'd0; +wire a7litesataphy_qpll_drp_rdy; +reg [8:0] a7litesataphy_qpll_drp_addr = 9'd0; +reg [15:0] a7litesataphy_qpll_drp_di = 16'd0; +wire [15:0] a7litesataphy_qpll_drp_do; +wire a7litesataphy_oobclk; +wire a7litesataphy_rxphaligndone; +wire a7litesataphy0; +wire a7litesataphy1; +wire a7litesataphy2; +wire a7litesataphy3; +wire a7litesataphy4; +wire a7litesataphy5; +wire a7litesataphy6; +wire a7litesataphy7; +wire a7litesataphy8; +wire a7litesataphy9; +wire a7litesataphy10; +wire a7litesataphy11; +wire a7litesataphy12; +wire a7litesataphy13; +wire a7litesataphy14; +wire a7litesataphy15; +wire a7litesataphy16; +wire a7litesataphy17; +wire a7litesataphy18; +wire a7litesataphy19; +wire a7litesataphy20; +wire a7litesataphy21; +wire a7litesataphy22; +wire a7litesataphy23; +wire a7litesataphy24; +wire a7litesataphy25; +wire a7litesataphy26; +wire a7litesataphy27; +wire a7litesataphy28; +wire a7litesataphy29; +wire a7litesataphy30; +wire a7litesataphy31; +wire a7litesataphy32; +wire a7litesataphy33; +wire a7litesataphy34; +wire a7litesataphy35; +wire a7litesataphy36; +wire a7litesataphy37; +wire a7litesataphy38; +wire a7litesataphy39; +wire a7litesataphy40; +wire a7litesataphy41; +wire a7litesataphy42; +reg crg_tx_reset = 1'd0; +reg crg_rx_reset = 1'd0; +(* dont_touch = "true" *) wire sata_tx_clk; +wire sata_tx_rst; +(* dont_touch = "true" *) wire sata_rx_clk; +wire sata_rx_rst; +wire crg_refclk; +reg ctrl_ready = 1'd0; +wire ctrl_sink_valid; +wire ctrl_sink_ready; +wire ctrl_sink_first; +wire ctrl_sink_last; +wire [31:0] ctrl_sink_payload_data; +wire [3:0] ctrl_sink_payload_charisk; +wire ctrl_source_valid; +wire ctrl_source_ready; +reg ctrl_source_first = 1'd0; +reg ctrl_source_last = 1'd0; +reg [31:0] ctrl_source_payload_data = 32'd0; +reg [3:0] ctrl_source_payload_charisk = 4'd0; +wire ctrl_misalign; +reg ctrl_tx_idle = 1'd0; +reg ctrl_rx_reset = 1'd0; +reg ctrl_tx_reset = 1'd0; +wire ctrl_rx_idle; +reg ctrl_retry_timer_wait = 1'd0; +wire ctrl_retry_timer_done; +reg [19:0] ctrl_retry_timer_count = 20'd800000; +reg ctrl_align_timer_wait = 1'd0; +wire ctrl_align_timer_done; +reg [16:0] ctrl_align_timer_count = 17'd69840; +reg [3:0] ctrl_align_count = 4'd0; +wire ctrl_reset; +reg ctrl_stability_timer_wait = 1'd0; +wire ctrl_stability_timer_done; +reg [18:0] ctrl_stability_timer_count = 19'd400000; +wire datapath_sink_sink_valid; +wire datapath_sink_sink_ready; +wire datapath_sink_sink_first; +wire datapath_sink_sink_last; +wire [31:0] datapath_sink_sink_payload_data; +wire [3:0] datapath_sink_sink_payload_charisk; +wire datapath_source_source_valid; +wire datapath_source_source_ready; +wire datapath_source_source_first; +wire datapath_source_source_last; +wire [31:0] datapath_source_source_payload_data; +wire [3:0] datapath_source_source_payload_charisk; +wire datapath_misalign; +wire datapath_rx_idle; +reg datapath_mux_source_valid = 1'd0; +wire datapath_mux_source_ready; +reg datapath_mux_source_first = 1'd0; +reg datapath_mux_source_last = 1'd0; +reg [31:0] datapath_mux_source_payload_data = 32'd0; +reg [3:0] datapath_mux_source_payload_charisk = 4'd0; +wire datapath_mux_endpoint0_sink_valid; +reg datapath_mux_endpoint0_sink_ready = 1'd0; +wire datapath_mux_endpoint0_sink_first; +wire datapath_mux_endpoint0_sink_last; +wire [31:0] datapath_mux_endpoint0_sink_payload_data; +wire [3:0] datapath_mux_endpoint0_sink_payload_charisk; +wire datapath_mux_endpoint1_sink_valid; +reg datapath_mux_endpoint1_sink_ready = 1'd0; +wire datapath_mux_endpoint1_sink_first; +wire datapath_mux_endpoint1_sink_last; +wire [31:0] datapath_mux_endpoint1_sink_payload_data; +wire [3:0] datapath_mux_endpoint1_sink_payload_charisk; +wire datapath_mux_sel; +wire datapath_tx_sink_sink_valid; +wire datapath_tx_sink_sink_ready; +wire datapath_tx_sink_sink_first; +wire datapath_tx_sink_sink_last; +wire [31:0] datapath_tx_sink_sink_payload_data; +wire [3:0] datapath_tx_sink_sink_payload_charisk; +wire datapath_tx_source_source_valid; +wire datapath_tx_source_source_ready; +wire datapath_tx_source_source_first; +wire datapath_tx_source_source_last; +wire [15:0] datapath_tx_source_source_payload_data; +wire [1:0] datapath_tx_source_source_payload_charisk; +wire datapath_tx_fifo_sink_valid; +wire datapath_tx_fifo_sink_ready; +wire datapath_tx_fifo_sink_first; +wire datapath_tx_fifo_sink_last; +wire [31:0] datapath_tx_fifo_sink_payload_data; +wire [3:0] datapath_tx_fifo_sink_payload_charisk; +wire datapath_tx_fifo_source_valid; +wire datapath_tx_fifo_source_ready; +wire datapath_tx_fifo_source_first; +wire datapath_tx_fifo_source_last; +wire [31:0] datapath_tx_fifo_source_payload_data; +wire [3:0] datapath_tx_fifo_source_payload_charisk; +wire datapath_tx_fifo_asyncfifo_we; +wire datapath_tx_fifo_asyncfifo_writable; +wire datapath_tx_fifo_asyncfifo_re; +wire datapath_tx_fifo_asyncfifo_readable; +wire [37:0] datapath_tx_fifo_asyncfifo_din; +wire [37:0] datapath_tx_fifo_asyncfifo_dout; +wire datapath_tx_fifo_graycounter0_ce; +(* dont_touch = "true" *) reg [3:0] datapath_tx_fifo_graycounter0_q = 4'd0; +wire [3:0] datapath_tx_fifo_graycounter0_q_next; +reg [3:0] datapath_tx_fifo_graycounter0_q_binary = 4'd0; +reg [3:0] datapath_tx_fifo_graycounter0_q_next_binary = 4'd0; +wire datapath_tx_fifo_graycounter1_ce; +(* dont_touch = "true" *) reg [3:0] datapath_tx_fifo_graycounter1_q = 4'd0; +wire [3:0] datapath_tx_fifo_graycounter1_q_next; +reg [3:0] datapath_tx_fifo_graycounter1_q_binary = 4'd0; +reg [3:0] datapath_tx_fifo_graycounter1_q_next_binary = 4'd0; +wire [3:0] datapath_tx_fifo_produce_rdomain; +wire [3:0] datapath_tx_fifo_consume_wdomain; +wire [2:0] datapath_tx_fifo_wrport_adr; +wire [37:0] datapath_tx_fifo_wrport_dat_r; +wire datapath_tx_fifo_wrport_we; +wire [37:0] datapath_tx_fifo_wrport_dat_w; +wire [2:0] datapath_tx_fifo_rdport_adr; +wire [37:0] datapath_tx_fifo_rdport_dat_r; +wire [31:0] datapath_tx_fifo_fifo_in_payload_data; +wire [3:0] datapath_tx_fifo_fifo_in_payload_charisk; +wire datapath_tx_fifo_fifo_in_first; +wire datapath_tx_fifo_fifo_in_last; +wire [31:0] datapath_tx_fifo_fifo_out_payload_data; +wire [3:0] datapath_tx_fifo_fifo_out_payload_charisk; +wire datapath_tx_fifo_fifo_out_first; +wire datapath_tx_fifo_fifo_out_last; +wire datapath_tx_converter_sink_valid; +wire datapath_tx_converter_sink_ready; +wire datapath_tx_converter_sink_first; +wire datapath_tx_converter_sink_last; +wire [31:0] datapath_tx_converter_sink_payload_data; +wire [3:0] datapath_tx_converter_sink_payload_charisk; +wire datapath_tx_converter_source_valid; +wire datapath_tx_converter_source_ready; +wire datapath_tx_converter_source_first; +wire datapath_tx_converter_source_last; +wire [15:0] datapath_tx_converter_source_payload_data; +wire [1:0] datapath_tx_converter_source_payload_charisk; +wire datapath_tx_converter_converter_sink_valid; +wire datapath_tx_converter_converter_sink_ready; +wire datapath_tx_converter_converter_sink_first; +wire datapath_tx_converter_converter_sink_last; +reg [35:0] datapath_tx_converter_converter_sink_payload_data = 36'd0; +wire datapath_tx_converter_converter_source_valid; +wire datapath_tx_converter_converter_source_ready; +wire datapath_tx_converter_converter_source_first; +wire datapath_tx_converter_converter_source_last; +reg [17:0] datapath_tx_converter_converter_source_payload_data = 18'd0; +wire datapath_tx_converter_converter_source_payload_valid_token_count; +reg datapath_tx_converter_converter_mux = 1'd0; +wire datapath_tx_converter_converter_first; +wire datapath_tx_converter_converter_last; +wire datapath_tx_converter_source_source_valid; +wire datapath_tx_converter_source_source_ready; +wire datapath_tx_converter_source_source_first; +wire datapath_tx_converter_source_source_last; +wire [17:0] datapath_tx_converter_source_source_payload_data; +wire datapath_rx_sink_sink_valid; +wire datapath_rx_sink_sink_ready; +wire datapath_rx_sink_sink_first; +wire datapath_rx_sink_sink_last; +wire [15:0] datapath_rx_sink_sink_payload_data; +wire [1:0] datapath_rx_sink_sink_payload_charisk; +wire datapath_rx_source_source_valid; +wire datapath_rx_source_source_ready; +wire datapath_rx_source_source_first; +wire datapath_rx_source_source_last; +wire [31:0] datapath_rx_source_source_payload_data; +wire [3:0] datapath_rx_source_source_payload_charisk; +reg [1:0] datapath_rx_byte_alignment = 2'd0; +reg [1:0] datapath_rx_last_charisk = 2'd0; +reg [15:0] datapath_rx_last_data = 16'd0; +wire [3:0] datapath_rx_sr_charisk; +wire [31:0] datapath_rx_sr_data; +wire datapath_rx_converter_sink_valid; +wire datapath_rx_converter_sink_ready; +reg datapath_rx_converter_sink_first = 1'd0; +reg datapath_rx_converter_sink_last = 1'd0; +reg [15:0] datapath_rx_converter_sink_payload_data = 16'd0; +reg [1:0] datapath_rx_converter_sink_payload_charisk = 2'd0; +wire datapath_rx_converter_source_valid; +wire datapath_rx_converter_source_ready; +wire datapath_rx_converter_source_first; +wire datapath_rx_converter_source_last; +reg [31:0] datapath_rx_converter_source_payload_data = 32'd0; +reg [3:0] datapath_rx_converter_source_payload_charisk = 4'd0; +wire datapath_rx_converter_converter_sink_valid; +wire datapath_rx_converter_converter_sink_ready; +wire datapath_rx_converter_converter_sink_first; +wire datapath_rx_converter_converter_sink_last; +wire [17:0] datapath_rx_converter_converter_sink_payload_data; +wire datapath_rx_converter_converter_source_valid; +wire datapath_rx_converter_converter_source_ready; +reg datapath_rx_converter_converter_source_first = 1'd0; +reg datapath_rx_converter_converter_source_last = 1'd0; +reg [35:0] datapath_rx_converter_converter_source_payload_data = 36'd0; +reg [1:0] datapath_rx_converter_converter_source_payload_valid_token_count = 2'd0; +reg datapath_rx_converter_converter_demux = 1'd0; +wire datapath_rx_converter_converter_load_part; +reg datapath_rx_converter_converter_strobe_all = 1'd0; +wire datapath_rx_converter_source_source_valid; +wire datapath_rx_converter_source_source_ready; +wire datapath_rx_converter_source_source_first; +wire datapath_rx_converter_source_source_last; +wire [35:0] datapath_rx_converter_source_source_payload_data; +wire datapath_rx_converter_reset; +wire datapath_rx_fifo_sink_valid; +wire datapath_rx_fifo_sink_ready; +wire datapath_rx_fifo_sink_first; +wire datapath_rx_fifo_sink_last; +wire [31:0] datapath_rx_fifo_sink_payload_data; +wire [3:0] datapath_rx_fifo_sink_payload_charisk; +wire datapath_rx_fifo_source_valid; +wire datapath_rx_fifo_source_ready; +wire datapath_rx_fifo_source_first; +wire datapath_rx_fifo_source_last; +wire [31:0] datapath_rx_fifo_source_payload_data; +wire [3:0] datapath_rx_fifo_source_payload_charisk; +wire datapath_rx_fifo_asyncfifo_we; +wire datapath_rx_fifo_asyncfifo_writable; +wire datapath_rx_fifo_asyncfifo_re; +wire datapath_rx_fifo_asyncfifo_readable; +wire [37:0] datapath_rx_fifo_asyncfifo_din; +wire [37:0] datapath_rx_fifo_asyncfifo_dout; +wire datapath_rx_fifo_graycounter0_ce; +(* dont_touch = "true" *) reg [3:0] datapath_rx_fifo_graycounter0_q = 4'd0; +wire [3:0] datapath_rx_fifo_graycounter0_q_next; +reg [3:0] datapath_rx_fifo_graycounter0_q_binary = 4'd0; +reg [3:0] datapath_rx_fifo_graycounter0_q_next_binary = 4'd0; +wire datapath_rx_fifo_graycounter1_ce; +(* dont_touch = "true" *) reg [3:0] datapath_rx_fifo_graycounter1_q = 4'd0; +wire [3:0] datapath_rx_fifo_graycounter1_q_next; +reg [3:0] datapath_rx_fifo_graycounter1_q_binary = 4'd0; +reg [3:0] datapath_rx_fifo_graycounter1_q_next_binary = 4'd0; +wire [3:0] datapath_rx_fifo_produce_rdomain; +wire [3:0] datapath_rx_fifo_consume_wdomain; +wire [2:0] datapath_rx_fifo_wrport_adr; +wire [37:0] datapath_rx_fifo_wrport_dat_r; +wire datapath_rx_fifo_wrport_we; +wire [37:0] datapath_rx_fifo_wrport_dat_w; +wire [2:0] datapath_rx_fifo_rdport_adr; +wire [37:0] datapath_rx_fifo_rdport_dat_r; +wire [31:0] datapath_rx_fifo_fifo_in_payload_data; +wire [3:0] datapath_rx_fifo_fifo_in_payload_charisk; +wire datapath_rx_fifo_fifo_in_first; +wire datapath_rx_fifo_fifo_in_last; +wire [31:0] datapath_rx_fifo_fifo_out_payload_data; +wire [3:0] datapath_rx_fifo_fifo_out_payload_charisk; +wire datapath_rx_fifo_fifo_out_first; +wire datapath_rx_fifo_fifo_out_last; +wire datapath_demux_sink_valid; +reg datapath_demux_sink_ready = 1'd0; +wire datapath_demux_sink_first; +wire datapath_demux_sink_last; +wire [31:0] datapath_demux_sink_payload_data; +wire [3:0] datapath_demux_sink_payload_charisk; +reg datapath_demux_endpoint0_source_valid = 1'd0; +wire datapath_demux_endpoint0_source_ready; +reg datapath_demux_endpoint0_source_first = 1'd0; +reg datapath_demux_endpoint0_source_last = 1'd0; +reg [31:0] datapath_demux_endpoint0_source_payload_data = 32'd0; +reg [3:0] datapath_demux_endpoint0_source_payload_charisk = 4'd0; +reg datapath_demux_endpoint1_source_valid = 1'd0; +wire datapath_demux_endpoint1_source_ready; +reg datapath_demux_endpoint1_source_first = 1'd0; +reg datapath_demux_endpoint1_source_last = 1'd0; +reg [31:0] datapath_demux_endpoint1_source_payload_data = 32'd0; +reg [3:0] datapath_demux_endpoint1_source_payload_charisk = 4'd0; +wire datapath_demux_sel; +wire datapath_align_timer_sink_valid; +wire datapath_align_timer_sink_first; +wire datapath_align_timer_sink_last; +wire [31:0] datapath_align_timer_sink_payload_data; +wire [3:0] datapath_align_timer_sink_payload_charisk; +reg datapath_align_timer_wait = 1'd0; +wire datapath_align_timer_done; +reg [12:0] datapath_align_timer_count = 13'd4096; +reg litesataphy_enable_storage = 1'd1; +reg litesataphy_enable_re = 1'd0; +wire litesataphy_ready; +wire litesataphy_tx_ready; +wire litesataphy_rx_ready; +wire litesataphy_ctrl_ready; +reg [3:0] litesataphy_status_status = 4'd0; +wire litesataphy_status_we; +reg litesataphy_status_re = 1'd0; +reg link_litesatalinktx_sink_sink_valid = 1'd0; +wire link_litesatalinktx_sink_sink_ready; +reg link_litesatalinktx_sink_sink_first = 1'd0; +reg link_litesatalinktx_sink_sink_last = 1'd0; +reg [31:0] link_litesatalinktx_sink_sink_payload_data = 32'd0; +reg link_litesatalinktx_sink_sink_payload_error = 1'd0; +reg link_litesatalinktx_source_source_valid = 1'd0; +wire link_litesatalinktx_source_source_ready; +reg link_litesatalinktx_source_source_first = 1'd0; +reg link_litesatalinktx_source_source_last = 1'd0; +reg [31:0] link_litesatalinktx_source_source_payload_data = 32'd0; +reg [3:0] link_litesatalinktx_source_source_payload_charisk = 4'd0; +wire link_litesatalinktx_from_rx_valid; +reg link_litesatalinktx_from_rx_ready = 1'd0; +wire link_litesatalinktx_from_rx_first; +wire link_litesatalinktx_from_rx_last; +wire link_litesatalinktx_from_rx_payload_idle; +wire [31:0] link_litesatalinktx_from_rx_payload_insert; +wire link_litesatalinktx_from_rx_payload_primitive_valid; +wire [31:0] link_litesatalinktx_from_rx_payload_primitive; +reg link_litesatalinktx_error = 1'd0; +wire link_litesatalinktx_crc_sink_valid; +reg link_litesatalinktx_crc_sink_ready = 1'd0; +wire link_litesatalinktx_crc_sink_first; +wire link_litesatalinktx_crc_sink_last; +wire [31:0] link_litesatalinktx_crc_sink_payload_data; +wire link_litesatalinktx_crc_sink_payload_error; +reg link_litesatalinktx_crc_source_valid = 1'd0; +wire link_litesatalinktx_crc_source_ready; +reg link_litesatalinktx_crc_source_first = 1'd0; +reg link_litesatalinktx_crc_source_last = 1'd0; +reg [31:0] link_litesatalinktx_crc_source_payload_data = 32'd0; +reg link_litesatalinktx_crc_source_payload_error = 1'd0; +wire link_litesatalinktx_crc_busy; +reg [31:0] link_litesatalinktx_crc_data0 = 32'd0; +wire [31:0] link_litesatalinktx_crc_value; +wire link_litesatalinktx_crc_error; +wire [31:0] link_litesatalinktx_crc_data1; +wire [31:0] link_litesatalinktx_crc_last; +reg [31:0] link_litesatalinktx_crc_next = 32'd0; +wire [31:0] link_litesatalinktx_crc_new; +reg [31:0] link_litesatalinktx_crc_reg_i = 32'd1379029042; +reg link_litesatalinktx_crc_ce = 1'd0; +reg link_litesatalinktx_crc_reset = 1'd0; +reg link_litesatalinktx_crc_is_ongoing = 1'd0; +wire link_litesatalinktx_scrambler_sink_valid; +wire link_litesatalinktx_scrambler_sink_ready; +wire link_litesatalinktx_scrambler_sink_first; +wire link_litesatalinktx_scrambler_sink_last; +wire [31:0] link_litesatalinktx_scrambler_sink_payload_data; +wire link_litesatalinktx_scrambler_sink_payload_error; +wire link_litesatalinktx_scrambler_source_valid; +reg link_litesatalinktx_scrambler_source_ready = 1'd0; +wire link_litesatalinktx_scrambler_source_first; +wire link_litesatalinktx_scrambler_source_last; +reg [31:0] link_litesatalinktx_scrambler_source_payload_data = 32'd0; +wire link_litesatalinktx_scrambler_source_payload_error; +wire [31:0] link_litesatalinktx_scrambler_value; +reg [15:0] link_litesatalinktx_scrambler_context = 16'd61686; +reg [31:0] link_litesatalinktx_scrambler_next_value = 32'd0; +wire link_litesatalinktx_scrambler_ce; +reg link_litesatalinktx_scrambler_reset = 1'd0; +reg [31:0] link_litesatalinktx_insert = 32'd0; +reg link_litesatalinktx_copy = 1'd0; +reg link_litesatalinktx_fsm_is_ongoing0 = 1'd0; +reg link_litesatalinktx_fsm_is_ongoing1 = 1'd0; +wire link_tx_sink_valid; +wire link_tx_sink_ready; +wire link_tx_sink_first; +wire link_tx_sink_last; +wire [31:0] link_tx_sink_payload_data; +wire [3:0] link_tx_sink_payload_charisk; +reg link_tx_source_valid = 1'd0; +wire link_tx_source_ready; +reg link_tx_source_first = 1'd0; +reg link_tx_source_last = 1'd0; +reg [31:0] link_tx_source_payload_data = 32'd0; +reg [3:0] link_tx_source_payload_charisk = 4'd0; +wire link_tx_align_sink_valid; +reg link_tx_align_sink_ready = 1'd0; +wire link_tx_align_sink_first; +wire link_tx_align_sink_last; +wire [31:0] link_tx_align_sink_payload_data; +wire [3:0] link_tx_align_sink_payload_charisk; +reg link_tx_align_source_valid = 1'd0; +wire link_tx_align_source_ready; +reg link_tx_align_source_first = 1'd0; +reg link_tx_align_source_last = 1'd0; +reg [31:0] link_tx_align_source_payload_data = 32'd0; +reg [3:0] link_tx_align_source_payload_charisk = 4'd0; +reg [7:0] link_tx_align_cnt = 8'd0; +wire link_tx_align_send; +wire link_rx_align_sink_valid; +reg link_rx_align_sink_ready = 1'd0; +wire link_rx_align_sink_first; +wire link_rx_align_sink_last; +wire [31:0] link_rx_align_sink_payload_data; +wire [3:0] link_rx_align_sink_payload_charisk; +reg link_rx_align_source_valid = 1'd0; +wire link_rx_align_source_ready; +reg link_rx_align_source_first = 1'd0; +reg link_rx_align_source_last = 1'd0; +reg [31:0] link_rx_align_source_payload_data = 32'd0; +reg [3:0] link_rx_align_source_payload_charisk = 4'd0; +wire link_rx_cont_sink_valid; +wire link_rx_cont_sink_ready; +wire link_rx_cont_sink_first; +wire link_rx_cont_sink_last; +wire [31:0] link_rx_cont_sink_payload_data; +wire [3:0] link_rx_cont_sink_payload_charisk; +wire link_rx_cont_source_valid; +wire link_rx_cont_source_ready; +wire link_rx_cont_source_first; +wire link_rx_cont_source_last; +reg [31:0] link_rx_cont_source_payload_data = 32'd0; +reg [3:0] link_rx_cont_source_payload_charisk = 4'd0; +wire link_rx_cont_is_data; +wire link_rx_cont_is_cont; +reg link_rx_cont_in_cont = 1'd0; +wire link_rx_cont_cont_ongoing; +reg [31:0] link_rx_cont_last_primitive = 32'd0; +wire link_litesatalinkrx_sink_sink_valid; +wire link_litesatalinkrx_sink_sink_ready; +wire link_litesatalinkrx_sink_sink_first; +wire link_litesatalinkrx_sink_sink_last; +wire [31:0] link_litesatalinkrx_sink_sink_payload_data; +wire [3:0] link_litesatalinkrx_sink_sink_payload_charisk; +wire link_litesatalinkrx_source_source_valid; +wire link_litesatalinkrx_source_source_ready; +wire link_litesatalinkrx_source_source_first; +wire link_litesatalinkrx_source_source_last; +wire [31:0] link_litesatalinkrx_source_source_payload_data; +wire link_litesatalinkrx_source_source_payload_error; +wire link_litesatalinkrx_hold; +reg link_litesatalinkrx_to_tx_valid = 1'd0; +wire link_litesatalinkrx_to_tx_ready; +reg link_litesatalinkrx_to_tx_first = 1'd0; +reg link_litesatalinkrx_to_tx_last = 1'd0; +wire link_litesatalinkrx_to_tx_payload_idle; +wire [31:0] link_litesatalinkrx_to_tx_payload_insert; +wire link_litesatalinkrx_to_tx_payload_primitive_valid; +wire [31:0] link_litesatalinkrx_to_tx_payload_primitive; +reg [31:0] link_litesatalinkrx_insert = 32'd0; +reg link_litesatalinkrx_data_valid = 1'd0; +reg link_litesatalinkrx_primitive_valid = 1'd0; +wire [31:0] link_litesatalinkrx_primitive; +reg link_litesatalinkrx_descrambler_sink_valid = 1'd0; +wire link_litesatalinkrx_descrambler_sink_ready; +reg link_litesatalinkrx_descrambler_sink_first = 1'd0; +reg link_litesatalinkrx_descrambler_sink_last = 1'd0; +reg [31:0] link_litesatalinkrx_descrambler_sink_payload_data = 32'd0; +reg link_litesatalinkrx_descrambler_sink_payload_error = 1'd0; +wire link_litesatalinkrx_descrambler_source_valid; +wire link_litesatalinkrx_descrambler_source_ready; +wire link_litesatalinkrx_descrambler_source_first; +wire link_litesatalinkrx_descrambler_source_last; +reg [31:0] link_litesatalinkrx_descrambler_source_payload_data = 32'd0; +wire link_litesatalinkrx_descrambler_source_payload_error; +wire [31:0] link_litesatalinkrx_descrambler_value; +reg [15:0] link_litesatalinkrx_descrambler_context = 16'd61686; +reg [31:0] link_litesatalinkrx_descrambler_next_value = 32'd0; +wire link_litesatalinkrx_descrambler_ce; +reg link_litesatalinkrx_descrambler_reset = 1'd0; +wire link_litesatalinkrx_crc_sink_sink_valid; +reg link_litesatalinkrx_crc_sink_sink_ready = 1'd0; +wire link_litesatalinkrx_crc_sink_sink_first; +wire link_litesatalinkrx_crc_sink_sink_last; +wire [31:0] link_litesatalinkrx_crc_sink_sink_payload_data; +wire link_litesatalinkrx_crc_sink_sink_payload_error; +wire link_litesatalinkrx_crc_source_source_valid; +wire link_litesatalinkrx_crc_source_source_ready; +reg link_litesatalinkrx_crc_source_source_first = 1'd0; +wire link_litesatalinkrx_crc_source_source_last; +wire [31:0] link_litesatalinkrx_crc_source_source_payload_data; +reg link_litesatalinkrx_crc_source_source_payload_error = 1'd0; +wire link_litesatalinkrx_crc_busy; +reg [31:0] link_litesatalinkrx_crc_crc_data0 = 32'd0; +wire [31:0] link_litesatalinkrx_crc_crc_value; +wire link_litesatalinkrx_crc_crc_error; +wire [31:0] link_litesatalinkrx_crc_crc_data1; +wire [31:0] link_litesatalinkrx_crc_crc_last; +reg [31:0] link_litesatalinkrx_crc_crc_next = 32'd0; +wire [31:0] link_litesatalinkrx_crc_crc_new; +reg [31:0] link_litesatalinkrx_crc_crc_reg_i = 32'd1379029042; +reg link_litesatalinkrx_crc_crc_ce = 1'd0; +reg link_litesatalinkrx_crc_crc_reset = 1'd0; +reg link_litesatalinkrx_crc_syncfifo_sink_valid = 1'd0; +wire link_litesatalinkrx_crc_syncfifo_sink_ready; +wire link_litesatalinkrx_crc_syncfifo_sink_first; +wire link_litesatalinkrx_crc_syncfifo_sink_last; +wire [31:0] link_litesatalinkrx_crc_syncfifo_sink_payload_data; +wire link_litesatalinkrx_crc_syncfifo_sink_payload_error; +wire link_litesatalinkrx_crc_syncfifo_source_valid; +wire link_litesatalinkrx_crc_syncfifo_source_ready; +wire link_litesatalinkrx_crc_syncfifo_source_first; +wire link_litesatalinkrx_crc_syncfifo_source_last; +wire [31:0] link_litesatalinkrx_crc_syncfifo_source_payload_data; +wire link_litesatalinkrx_crc_syncfifo_source_payload_error; +wire link_litesatalinkrx_crc_syncfifo_syncfifo_we; +wire link_litesatalinkrx_crc_syncfifo_syncfifo_writable; +wire link_litesatalinkrx_crc_syncfifo_syncfifo_re; +wire link_litesatalinkrx_crc_syncfifo_syncfifo_readable; +wire [34:0] link_litesatalinkrx_crc_syncfifo_syncfifo_din; +wire [34:0] link_litesatalinkrx_crc_syncfifo_syncfifo_dout; +reg [1:0] link_litesatalinkrx_crc_syncfifo_level = 2'd0; +reg link_litesatalinkrx_crc_syncfifo_replace = 1'd0; +reg link_litesatalinkrx_crc_syncfifo_produce = 1'd0; +reg link_litesatalinkrx_crc_syncfifo_consume = 1'd0; +reg link_litesatalinkrx_crc_syncfifo_wrport_adr = 1'd0; +wire [34:0] link_litesatalinkrx_crc_syncfifo_wrport_dat_r; +wire link_litesatalinkrx_crc_syncfifo_wrport_we; +wire [34:0] link_litesatalinkrx_crc_syncfifo_wrport_dat_w; +wire link_litesatalinkrx_crc_syncfifo_do_read; +wire link_litesatalinkrx_crc_syncfifo_rdport_adr; +wire [34:0] link_litesatalinkrx_crc_syncfifo_rdport_dat_r; +wire [31:0] link_litesatalinkrx_crc_syncfifo_fifo_in_payload_data; +wire link_litesatalinkrx_crc_syncfifo_fifo_in_payload_error; +wire link_litesatalinkrx_crc_syncfifo_fifo_in_first; +wire link_litesatalinkrx_crc_syncfifo_fifo_in_last; +wire [31:0] link_litesatalinkrx_crc_syncfifo_fifo_out_payload_data; +wire link_litesatalinkrx_crc_syncfifo_fifo_out_payload_error; +wire link_litesatalinkrx_crc_syncfifo_fifo_out_first; +wire link_litesatalinkrx_crc_syncfifo_fifo_out_last; +reg link_litesatalinkrx_crc_fifo_reset = 1'd0; +wire link_litesatalinkrx_crc_fifo_in; +wire link_litesatalinkrx_crc_fifo_out; +wire link_litesatalinkrx_crc_fifo_full; +reg link_litesatalinkrx_crc_is_ongoing = 1'd0; +reg link_litesatalinkrx_crc_error = 1'd0; +reg link_litesatalinkrx_fsm_is_ongoing = 1'd0; +wire link_rx_sink_valid; +wire link_rx_sink_ready; +wire link_rx_sink_first; +wire link_rx_sink_last; +wire [31:0] link_rx_sink_payload_data; +wire [3:0] link_rx_sink_payload_charisk; +reg link_rx_source_valid = 1'd0; +wire link_rx_source_ready; +reg link_rx_source_first = 1'd0; +reg link_rx_source_last = 1'd0; +reg [31:0] link_rx_source_payload_data = 32'd0; +reg [3:0] link_rx_source_payload_charisk = 4'd0; +wire link_rx_buffer_sink_valid; +wire link_rx_buffer_sink_ready; +wire link_rx_buffer_sink_first; +wire link_rx_buffer_sink_last; +wire [31:0] link_rx_buffer_sink_payload_data; +wire link_rx_buffer_sink_payload_error; +wire link_rx_buffer_source_valid; +reg link_rx_buffer_source_ready = 1'd0; +wire link_rx_buffer_source_first; +wire link_rx_buffer_source_last; +wire [31:0] link_rx_buffer_source_payload_data; +wire link_rx_buffer_source_payload_error; +wire link_rx_buffer_syncfifo_we; +wire link_rx_buffer_syncfifo_writable; +wire link_rx_buffer_syncfifo_re; +wire link_rx_buffer_syncfifo_readable; +wire [34:0] link_rx_buffer_syncfifo_din; +wire [34:0] link_rx_buffer_syncfifo_dout; +reg [7:0] link_rx_buffer_level = 8'd0; +reg link_rx_buffer_replace = 1'd0; +reg [6:0] link_rx_buffer_produce = 7'd0; +reg [6:0] link_rx_buffer_consume = 7'd0; +reg [6:0] link_rx_buffer_wrport_adr = 7'd0; +wire [34:0] link_rx_buffer_wrport_dat_r; +wire link_rx_buffer_wrport_we; +wire [34:0] link_rx_buffer_wrport_dat_w; +wire link_rx_buffer_do_read; +wire [6:0] link_rx_buffer_rdport_adr; +wire [34:0] link_rx_buffer_rdport_dat_r; +wire [31:0] link_rx_buffer_fifo_in_payload_data; +wire link_rx_buffer_fifo_in_payload_error; +wire link_rx_buffer_fifo_in_first; +wire link_rx_buffer_fifo_in_last; +wire [31:0] link_rx_buffer_fifo_out_payload_data; +wire link_rx_buffer_fifo_out_payload_error; +wire link_rx_buffer_fifo_out_first; +wire link_rx_buffer_fifo_out_last; +reg transport_tx_sink_valid = 1'd0; +reg transport_tx_sink_ready = 1'd0; +reg transport_tx_sink_last = 1'd0; +wire [31:0] transport_tx_sink_payload_data; +reg [7:0] transport_tx_sink_param_type = 8'd0; +wire [3:0] transport_tx_sink_param_pm_port; +reg transport_tx_sink_param_c = 1'd0; +reg [7:0] transport_tx_sink_param_command = 8'd0; +wire [15:0] transport_tx_sink_param_features; +wire [47:0] transport_tx_sink_param_lba; +wire [7:0] transport_tx_sink_param_device; +wire [15:0] transport_tx_sink_param_count; +wire [7:0] transport_tx_sink_param_icc; +wire [7:0] transport_tx_sink_param_control; +reg [159:0] transport_tx_encoded_cmd = 160'd0; +reg [2:0] transport_tx_counter = 3'd0; +wire transport_tx_counter_ce; +reg transport_tx_counter_reset = 1'd0; +reg [2:0] transport_tx_cmd_len = 3'd0; +reg transport_tx_cmd_with_data = 1'd0; +reg transport_tx_cmd_send = 1'd0; +reg transport_tx_data_send = 1'd0; +wire transport_tx_cmd_done; +reg [7:0] transport_tx_fis_type = 8'd0; +reg transport_tx_update_fis_type = 1'd0; +reg transport_rx_source_valid = 1'd0; +reg transport_rx_source_ready = 1'd0; +reg transport_rx_source_last = 1'd0; +reg [31:0] transport_rx_source_payload_data = 32'd0; +reg [7:0] transport_rx_source_param_type = 8'd0; +reg [3:0] transport_rx_source_param_pm_port = 4'd0; +reg transport_rx_source_param_d = 1'd0; +reg transport_rx_source_param_i = 1'd0; +reg [7:0] transport_rx_source_param_status = 8'd0; +reg [7:0] transport_rx_source_param_errors = 8'd0; +reg [47:0] transport_rx_source_param_lba = 48'd0; +reg [7:0] transport_rx_source_param_device = 8'd0; +reg [15:0] transport_rx_source_param_count = 16'd0; +reg [15:0] transport_rx_source_param_transfer_count = 16'd0; +reg transport_rx_source_param_error = 1'd0; +reg [159:0] transport_rx_encoded_cmd = 160'd0; +reg [2:0] transport_rx_counter = 3'd0; +reg transport_rx_counter_ce = 1'd0; +reg transport_rx_counter_reset = 1'd0; +reg [2:0] transport_rx_cmd_len = 3'd0; +reg transport_rx_cmd_receive = 1'd0; +reg transport_rx_data_receive = 1'd0; +wire transport_rx_cmd_done; +reg [7:0] transport_rx_fis_type = 8'd0; +reg transport_rx_update_fis_type = 1'd0; +wire command_tx_sink_valid; +reg command_tx_sink_ready = 1'd0; +wire command_tx_sink_first; +wire command_tx_sink_last; +wire [31:0] command_tx_sink_payload_data; +wire command_tx_sink_param_write; +wire command_tx_sink_param_read; +wire command_tx_sink_param_identify; +wire [47:0] command_tx_sink_param_sector; +wire [15:0] command_tx_sink_param_count; +reg command_tx_to_rx_valid = 1'd0; +wire command_tx_to_rx_ready; +reg command_tx_to_rx_first = 1'd0; +reg command_tx_to_rx_last = 1'd0; +reg command_tx_to_rx_payload_write = 1'd0; +reg command_tx_to_rx_payload_read = 1'd0; +reg command_tx_to_rx_payload_identify = 1'd0; +reg [15:0] command_tx_to_rx_payload_count = 16'd0; +wire command_tx_from_rx_valid; +reg command_tx_from_rx_ready = 1'd0; +wire command_tx_from_rx_first; +wire command_tx_from_rx_last; +wire command_tx_from_rx_payload_dma_activate; +wire command_tx_from_rx_payload_d2h_error; +reg command_tx_is_write = 1'd0; +reg command_tx_is_read = 1'd0; +reg command_tx_is_identify = 1'd0; +reg [10:0] command_tx_dwords_counter = 11'd0; +reg command_tx_is_ongoing0 = 1'd0; +reg command_tx_is_ongoing1 = 1'd0; +reg command_rx_source_valid = 1'd0; +wire command_rx_source_ready; +reg command_rx_source_first = 1'd0; +reg command_rx_source_last = 1'd0; +reg [31:0] command_rx_source_payload_data = 32'd0; +reg command_rx_source_param_write = 1'd0; +reg command_rx_source_param_read = 1'd0; +reg command_rx_source_param_identify = 1'd0; +reg command_rx_source_param_end = 1'd0; +reg command_rx_source_param_failed = 1'd0; +reg command_rx_to_tx_valid = 1'd0; +wire command_rx_to_tx_ready; +reg command_rx_to_tx_first = 1'd0; +reg command_rx_to_tx_last = 1'd0; +wire command_rx_to_tx_payload_dma_activate; +wire command_rx_to_tx_payload_d2h_error; +wire command_rx_from_tx_valid; +reg command_rx_from_tx_ready = 1'd0; +wire command_rx_from_tx_first; +wire command_rx_from_tx_last; +wire command_rx_from_tx_payload_write; +wire command_rx_from_tx_payload_read; +wire command_rx_from_tx_payload_identify; +wire [15:0] command_rx_from_tx_payload_count; +reg [7:0] command_rx_d2h_status = 8'd0; +reg [7:0] command_rx_d2h_errors = 8'd0; +reg command_rx_is_identify = 1'd0; +reg command_rx_is_dma_activate = 1'd0; +reg [22:0] command_rx_read_ndwords = 23'd0; +reg [22:0] command_rx_dwords_counter = 23'd0; +wire command_rx_read_done; +reg command_rx_d2h_error = 1'd0; +reg command_rx_clr_d2h_error = 1'd0; +reg command_rx_set_d2h_error = 1'd0; +reg command_rx_read_error = 1'd0; +reg command_rx_clr_read_error = 1'd0; +reg command_rx_set_read_error = 1'd0; +reg command_rx_update_d2h = 1'd0; +reg command_rx_is_ongoing = 1'd0; +reg source_valid = 1'd0; +wire source_ready; +reg source_first = 1'd0; +reg source_last = 1'd0; +reg [31:0] source_payload_data = 32'd0; +reg source_param_write = 1'd0; +reg source_param_read = 1'd0; +reg source_param_identify = 1'd0; +reg [47:0] source_param_sector = 48'd0; +reg [15:0] source_param_count = 16'd0; +wire sink_valid; +reg sink_ready = 1'd0; +wire sink_first; +wire sink_last; +wire [31:0] sink_payload_data; +wire sink_param_write; +wire sink_param_read; +wire sink_param_identify; +wire sink_param_end; +wire sink_param_failed; +wire [31:0] interface0_bus_adr; +wire [31:0] interface0_bus_dat_w; +wire [31:0] interface0_bus_dat_r; +wire [3:0] interface0_bus_sel; +wire interface0_bus_cyc; +wire interface0_bus_stb; +wire interface0_bus_ack; +wire interface0_bus_we; +reg [2:0] interface0_bus_cti = 3'd0; +reg [1:0] interface0_bus_bte = 2'd0; +wire interface0_bus_err; +reg litesatauserport0_sink_valid = 1'd0; +reg litesatauserport0_sink_ready = 1'd0; +reg litesatauserport0_sink_first = 1'd0; +reg litesatauserport0_sink_last = 1'd0; +reg [31:0] litesatauserport0_sink_payload_data = 32'd0; +reg litesatauserport0_sink_param_write = 1'd0; +reg litesatauserport0_sink_param_read = 1'd0; +reg litesatauserport0_sink_param_identify = 1'd0; +reg [47:0] litesatauserport0_sink_param_sector = 48'd0; +reg [15:0] litesatauserport0_sink_param_count = 16'd0; +reg litesatauserport0_source_valid = 1'd0; +wire litesatauserport0_source_ready; +reg litesatauserport0_source_first = 1'd0; +reg litesatauserport0_source_last = 1'd0; +reg [31:0] litesatauserport0_source_payload_data = 32'd0; +reg litesatauserport0_source_param_write = 1'd0; +reg litesatauserport0_source_param_read = 1'd0; +reg litesatauserport0_source_param_identify = 1'd0; +reg litesatauserport0_source_param_end = 1'd0; +reg litesatauserport0_source_param_failed = 1'd0; +reg [47:0] sata_sector2mem_sector_storage = 48'd0; +reg sata_sector2mem_sector_re = 1'd0; +reg [63:0] sata_sector2mem_base_storage = 64'd0; +reg sata_sector2mem_base_re = 1'd0; +wire sata_sector2mem_start_re; +wire sata_sector2mem_start_r; +wire sata_sector2mem_start_we; +reg sata_sector2mem_start_w = 1'd0; +reg sata_sector2mem_done_status = 1'd0; +wire sata_sector2mem_done_we; +reg sata_sector2mem_done_re = 1'd0; +reg sata_sector2mem_error_status = 1'd0; +wire sata_sector2mem_error_we; +reg sata_sector2mem_error_re = 1'd0; +reg [6:0] sata_sector2mem_count = 7'd0; +wire sata_sector2mem_buf_sink_valid; +wire sata_sector2mem_buf_sink_ready; +reg sata_sector2mem_buf_sink_first = 1'd0; +wire sata_sector2mem_buf_sink_last; +wire [31:0] sata_sector2mem_buf_sink_payload_data; +wire sata_sector2mem_buf_source_valid; +wire sata_sector2mem_buf_source_ready; +wire sata_sector2mem_buf_source_first; +wire sata_sector2mem_buf_source_last; +wire [31:0] sata_sector2mem_buf_source_payload_data; +wire sata_sector2mem_buf_syncfifo_we; +wire sata_sector2mem_buf_syncfifo_writable; +wire sata_sector2mem_buf_syncfifo_re; +wire sata_sector2mem_buf_syncfifo_readable; +wire [33:0] sata_sector2mem_buf_syncfifo_din; +wire [33:0] sata_sector2mem_buf_syncfifo_dout; +reg [7:0] sata_sector2mem_buf_level = 8'd0; +reg sata_sector2mem_buf_replace = 1'd0; +reg [6:0] sata_sector2mem_buf_produce = 7'd0; +reg [6:0] sata_sector2mem_buf_consume = 7'd0; +reg [6:0] sata_sector2mem_buf_wrport_adr = 7'd0; +wire [33:0] sata_sector2mem_buf_wrport_dat_r; +wire sata_sector2mem_buf_wrport_we; +wire [33:0] sata_sector2mem_buf_wrport_dat_w; +wire sata_sector2mem_buf_do_read; +wire [6:0] sata_sector2mem_buf_rdport_adr; +wire [33:0] sata_sector2mem_buf_rdport_dat_r; +wire [31:0] sata_sector2mem_buf_fifo_in_payload_data; +wire sata_sector2mem_buf_fifo_in_first; +wire sata_sector2mem_buf_fifo_in_last; +wire [31:0] sata_sector2mem_buf_fifo_out_payload_data; +wire sata_sector2mem_buf_fifo_out_first; +wire sata_sector2mem_buf_fifo_out_last; +wire sata_sector2mem_converter_sink_valid; +wire sata_sector2mem_converter_sink_ready; +wire sata_sector2mem_converter_sink_first; +wire sata_sector2mem_converter_sink_last; +wire [31:0] sata_sector2mem_converter_sink_payload_data; +wire sata_sector2mem_converter_source_valid; +wire sata_sector2mem_converter_source_ready; +wire sata_sector2mem_converter_source_first; +wire sata_sector2mem_converter_source_last; +wire [31:0] sata_sector2mem_converter_source_payload_data; +wire sata_sector2mem_converter_source_payload_valid_token_count; +wire sata_sector2mem_source_source_valid; +reg sata_sector2mem_source_source_ready = 1'd0; +wire sata_sector2mem_source_source_first; +wire sata_sector2mem_source_source_last; +wire [31:0] sata_sector2mem_source_source_payload_data; +reg sata_sector2mem_dma_sink_valid = 1'd0; +wire sata_sector2mem_dma_sink_ready; +reg sata_sector2mem_dma_sink_last = 1'd0; +reg [31:0] sata_sector2mem_dma_sink_payload_address = 32'd0; +reg [31:0] sata_sector2mem_dma_sink_payload_data = 32'd0; +reg [31:0] interface1_bus_adr = 32'd0; +reg [31:0] interface1_bus_dat_w = 32'd0; +wire [31:0] interface1_bus_dat_r; +reg [3:0] interface1_bus_sel = 4'd0; +reg interface1_bus_cyc = 1'd0; +reg interface1_bus_stb = 1'd0; +wire interface1_bus_ack; +reg interface1_bus_we = 1'd0; +reg [2:0] interface1_bus_cti = 3'd0; +reg [1:0] interface1_bus_bte = 2'd0; +wire interface1_bus_err; +reg litesatauserport1_sink_valid = 1'd0; +reg litesatauserport1_sink_ready = 1'd0; +reg litesatauserport1_sink_first = 1'd0; +reg litesatauserport1_sink_last = 1'd0; +reg [31:0] litesatauserport1_sink_payload_data = 32'd0; +reg litesatauserport1_sink_param_write = 1'd0; +reg litesatauserport1_sink_param_read = 1'd0; +reg litesatauserport1_sink_param_identify = 1'd0; +reg [47:0] litesatauserport1_sink_param_sector = 48'd0; +reg [15:0] litesatauserport1_sink_param_count = 16'd0; +reg litesatauserport1_source_valid = 1'd0; +reg litesatauserport1_source_ready = 1'd0; +reg litesatauserport1_source_first = 1'd0; +reg litesatauserport1_source_last = 1'd0; +reg [31:0] litesatauserport1_source_payload_data = 32'd0; +reg litesatauserport1_source_param_write = 1'd0; +reg litesatauserport1_source_param_read = 1'd0; +reg litesatauserport1_source_param_identify = 1'd0; +reg litesatauserport1_source_param_end = 1'd0; +reg litesatauserport1_source_param_failed = 1'd0; +reg [47:0] sata_mem2sector_sector_storage = 48'd0; +reg sata_mem2sector_sector_re = 1'd0; +reg [63:0] sata_mem2sector_base_storage = 64'd0; +reg sata_mem2sector_base_re = 1'd0; +wire sata_mem2sector_start_re; +wire sata_mem2sector_start_r; +wire sata_mem2sector_start_we; +reg sata_mem2sector_start_w = 1'd0; +reg sata_mem2sector_done_status = 1'd0; +wire sata_mem2sector_done_we; +reg sata_mem2sector_done_re = 1'd0; +reg sata_mem2sector_error_status = 1'd0; +wire sata_mem2sector_error_we; +reg sata_mem2sector_error_re = 1'd0; +reg [6:0] sata_mem2sector_count = 7'd0; +reg sata_mem2sector_dma_sink_valid = 1'd0; +reg sata_mem2sector_dma_sink_ready = 1'd0; +reg sata_mem2sector_dma_sink_last = 1'd0; +reg [31:0] sata_mem2sector_dma_sink_payload_address = 32'd0; +reg sata_mem2sector_dma_source_valid = 1'd0; +wire sata_mem2sector_dma_source_ready; +reg sata_mem2sector_dma_source_first = 1'd0; +reg sata_mem2sector_dma_source_last = 1'd0; +reg [31:0] sata_mem2sector_dma_source_payload_data = 32'd0; +reg [31:0] sata_mem2sector_dma_data = 32'd0; +wire sata_mem2sector_buf_sink_valid; +wire sata_mem2sector_buf_sink_ready; +wire sata_mem2sector_buf_sink_first; +wire sata_mem2sector_buf_sink_last; +wire [31:0] sata_mem2sector_buf_sink_payload_data; +wire sata_mem2sector_buf_source_valid; +wire sata_mem2sector_buf_source_ready; +wire sata_mem2sector_buf_source_first; +wire sata_mem2sector_buf_source_last; +wire [31:0] sata_mem2sector_buf_source_payload_data; +wire sata_mem2sector_buf_syncfifo_we; +wire sata_mem2sector_buf_syncfifo_writable; +wire sata_mem2sector_buf_syncfifo_re; +wire sata_mem2sector_buf_syncfifo_readable; +wire [33:0] sata_mem2sector_buf_syncfifo_din; +wire [33:0] sata_mem2sector_buf_syncfifo_dout; +reg [7:0] sata_mem2sector_buf_level = 8'd0; +reg sata_mem2sector_buf_replace = 1'd0; +reg [6:0] sata_mem2sector_buf_produce = 7'd0; +reg [6:0] sata_mem2sector_buf_consume = 7'd0; +reg [6:0] sata_mem2sector_buf_wrport_adr = 7'd0; +wire [33:0] sata_mem2sector_buf_wrport_dat_r; +wire sata_mem2sector_buf_wrport_we; +wire [33:0] sata_mem2sector_buf_wrport_dat_w; +wire sata_mem2sector_buf_do_read; +wire [6:0] sata_mem2sector_buf_rdport_adr; +wire [33:0] sata_mem2sector_buf_rdport_dat_r; +wire [31:0] sata_mem2sector_buf_fifo_in_payload_data; +wire sata_mem2sector_buf_fifo_in_first; +wire sata_mem2sector_buf_fifo_in_last; +wire [31:0] sata_mem2sector_buf_fifo_out_payload_data; +wire sata_mem2sector_buf_fifo_out_first; +wire sata_mem2sector_buf_fifo_out_last; +wire sata_mem2sector_converter_sink_valid; +wire sata_mem2sector_converter_sink_ready; +wire sata_mem2sector_converter_sink_first; +wire sata_mem2sector_converter_sink_last; +wire [31:0] sata_mem2sector_converter_sink_payload_data; +wire sata_mem2sector_converter_source_valid; +wire sata_mem2sector_converter_source_ready; +wire sata_mem2sector_converter_source_first; +wire sata_mem2sector_converter_source_last; +wire [31:0] sata_mem2sector_converter_source_payload_data; +wire sata_mem2sector_converter_source_payload_valid_token_count; +wire sata_mem2sector_source_source_valid; +reg sata_mem2sector_source_source_ready = 1'd0; +wire sata_mem2sector_source_source_first; +wire sata_mem2sector_source_source_last; +wire [31:0] sata_mem2sector_source_source_payload_data; +reg [7:0] storage = 8'd0; +reg re = 1'd0; +reg [7:0] chaser = 8'd0; +reg mode = 1'd0; +wire wait_1; +wire done; +reg [22:0] count = 23'd5000000; +wire subfragments_reset0; +wire subfragments_reset1; +wire subfragments_reset2; +wire subfragments_reset3; +wire subfragments_reset4; +wire subfragments_reset5; +wire subfragments_reset6; +wire subfragments_reset7; +wire subfragments_pll_fb; +reg [1:0] subfragments_refresher_state = 2'd0; +reg [1:0] subfragments_refresher_next_state = 2'd0; +reg [2:0] subfragments_bankmachine0_state = 3'd0; +reg [2:0] subfragments_bankmachine0_next_state = 3'd0; +reg [2:0] subfragments_bankmachine1_state = 3'd0; +reg [2:0] subfragments_bankmachine1_next_state = 3'd0; +reg [2:0] subfragments_bankmachine2_state = 3'd0; +reg [2:0] subfragments_bankmachine2_next_state = 3'd0; +reg [2:0] subfragments_bankmachine3_state = 3'd0; +reg [2:0] subfragments_bankmachine3_next_state = 3'd0; +reg [2:0] subfragments_bankmachine4_state = 3'd0; +reg [2:0] subfragments_bankmachine4_next_state = 3'd0; +reg [2:0] subfragments_bankmachine5_state = 3'd0; +reg [2:0] subfragments_bankmachine5_next_state = 3'd0; +reg [2:0] subfragments_bankmachine6_state = 3'd0; +reg [2:0] subfragments_bankmachine6_next_state = 3'd0; +reg [2:0] subfragments_bankmachine7_state = 3'd0; +reg [2:0] subfragments_bankmachine7_next_state = 3'd0; +reg [3:0] subfragments_multiplexer_state = 4'd0; +reg [3:0] subfragments_multiplexer_next_state = 4'd0; +wire subfragments_roundrobin0_request; +wire subfragments_roundrobin0_grant; +wire subfragments_roundrobin0_ce; +wire subfragments_roundrobin1_request; +wire subfragments_roundrobin1_grant; +wire subfragments_roundrobin1_ce; +wire subfragments_roundrobin2_request; +wire subfragments_roundrobin2_grant; +wire subfragments_roundrobin2_ce; +wire subfragments_roundrobin3_request; +wire subfragments_roundrobin3_grant; +wire subfragments_roundrobin3_ce; +wire subfragments_roundrobin4_request; +wire subfragments_roundrobin4_grant; +wire subfragments_roundrobin4_ce; +wire subfragments_roundrobin5_request; +wire subfragments_roundrobin5_grant; +wire subfragments_roundrobin5_ce; +wire subfragments_roundrobin6_request; +wire subfragments_roundrobin6_grant; +wire subfragments_roundrobin6_ce; +wire subfragments_roundrobin7_request; +wire subfragments_roundrobin7_grant; +wire subfragments_roundrobin7_ce; +reg subfragments_locked0 = 1'd0; +reg subfragments_locked1 = 1'd0; +reg subfragments_locked2 = 1'd0; +reg subfragments_locked3 = 1'd0; +reg subfragments_locked4 = 1'd0; +reg subfragments_locked5 = 1'd0; +reg subfragments_locked6 = 1'd0; +reg subfragments_locked7 = 1'd0; +reg subfragments_new_master_wdata_ready0 = 1'd0; +reg subfragments_new_master_wdata_ready1 = 1'd0; +reg subfragments_new_master_rdata_valid0 = 1'd0; +reg subfragments_new_master_rdata_valid1 = 1'd0; +reg subfragments_new_master_rdata_valid2 = 1'd0; +reg subfragments_new_master_rdata_valid3 = 1'd0; +reg subfragments_new_master_rdata_valid4 = 1'd0; +reg subfragments_new_master_rdata_valid5 = 1'd0; +reg subfragments_new_master_rdata_valid6 = 1'd0; +reg subfragments_new_master_rdata_valid7 = 1'd0; +reg subfragments_new_master_rdata_valid8 = 1'd0; +reg [1:0] subfragments_fullmemorywe_state = 2'd0; +reg [1:0] subfragments_fullmemorywe_next_state = 2'd0; +reg [3:0] subfragments_litesataphy_gtptxinit_state = 4'd0; +reg [3:0] subfragments_litesataphy_gtptxinit_next_state = 4'd0; +reg [3:0] subfragments_litesataphy_gtprxinit_state = 4'd0; +reg [3:0] subfragments_litesataphy_gtprxinit_next_state = 4'd0; +reg [15:0] a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value = 16'd0; +reg a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value_ce = 1'd0; +reg [3:0] subfragments_litesataphy_state = 4'd0; +reg [3:0] subfragments_litesataphy_next_state = 4'd0; +reg [3:0] ctrl_align_count_subfragments_litesataphyctrl_next_value0 = 4'd0; +reg ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 = 1'd0; +reg a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 = 1'd0; +reg a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 = 1'd0; +reg a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value2 = 1'd0; +reg a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value_ce2 = 1'd0; +reg [1:0] subfragments_litesatalinktx_litesatacrcinserter_state = 2'd0; +reg [1:0] subfragments_litesatalinktx_litesatacrcinserter_next_state = 2'd0; +reg [2:0] subfragments_litesatalinktx_fsm_state = 3'd0; +reg [2:0] subfragments_litesatalinktx_fsm_next_state = 3'd0; +reg [1:0] subfragments_litesatalinkrx_litesatacrcchecker_state = 2'd0; +reg [1:0] subfragments_litesatalinkrx_litesatacrcchecker_next_state = 2'd0; +reg [2:0] subfragments_litesatalinkrx_fsm_state = 3'd0; +reg [2:0] subfragments_litesatalinkrx_fsm_next_state = 3'd0; +reg [1:0] subfragments_litesatatransporttx_state = 2'd0; +reg [1:0] subfragments_litesatatransporttx_next_state = 2'd0; +reg [2:0] subfragments_litesatatransportrx_state = 3'd0; +reg [2:0] subfragments_litesatatransportrx_next_state = 3'd0; +reg [1:0] subfragments_litesatacommandtx_state = 2'd0; +reg [1:0] subfragments_litesatacommandtx_next_state = 2'd0; +reg [10:0] command_tx_dwords_counter_subfragments_litesatacommandtx_next_value = 11'd0; +reg command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce = 1'd0; +reg [3:0] subfragments_litesatacommandrx_state = 4'd0; +reg [3:0] subfragments_litesatacommandrx_next_state = 4'd0; +reg [22:0] command_rx_dwords_counter_subfragments_litesatacommandrx_next_value = 23'd0; +reg command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce = 1'd0; +reg [1:0] subfragments_request = 2'd0; +reg subfragments_grant = 1'd0; +wire subfragments_done0; +reg subfragments_ongoing0 = 1'd0; +wire subfragments_done1; +reg subfragments_ongoing1 = 1'd0; +reg [1:0] subfragments_litesatasector2memdma_state = 2'd0; +reg [1:0] subfragments_litesatasector2memdma_next_state = 2'd0; +reg [6:0] sata_sector2mem_count_subfragments_next_value0 = 7'd0; +reg sata_sector2mem_count_subfragments_next_value_ce0 = 1'd0; +reg sata_sector2mem_error_status_subfragments_next_value1 = 1'd0; +reg sata_sector2mem_error_status_subfragments_next_value_ce1 = 1'd0; +reg subfragments_wishbonedmareader_state = 1'd0; +reg subfragments_wishbonedmareader_next_state = 1'd0; +reg [31:0] sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value = 32'd0; +reg sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value_ce = 1'd0; +reg [1:0] subfragments_fsm_state = 2'd0; +reg [1:0] subfragments_fsm_next_state = 2'd0; +reg [6:0] sata_mem2sector_count_subfragments_fsm_next_value0 = 7'd0; +reg sata_mem2sector_count_subfragments_fsm_next_value_ce0 = 1'd0; +reg sata_mem2sector_error_status_subfragments_fsm_next_value1 = 1'd0; +reg sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 = 1'd0; +reg [13:0] basesoc_basesoc_adr = 14'd0; +reg basesoc_basesoc_we = 1'd0; +reg [31:0] basesoc_basesoc_dat_w = 32'd0; +wire [31:0] basesoc_basesoc_dat_r; +wire [29:0] basesoc_basesoc_wishbone_adr; +wire [31:0] basesoc_basesoc_wishbone_dat_w; +reg [31:0] basesoc_basesoc_wishbone_dat_r = 32'd0; +wire [3:0] basesoc_basesoc_wishbone_sel; +wire basesoc_basesoc_wishbone_cyc; +wire basesoc_basesoc_wishbone_stb; +reg basesoc_basesoc_wishbone_ack = 1'd0; +wire basesoc_basesoc_wishbone_we; +wire [2:0] basesoc_basesoc_wishbone_cti; +wire [1:0] basesoc_basesoc_wishbone_bte; +reg basesoc_basesoc_wishbone_err = 1'd0; +wire [29:0] basesoc_shared_adr; +wire [31:0] basesoc_shared_dat_w; +reg [31:0] basesoc_shared_dat_r = 32'd0; +wire [3:0] basesoc_shared_sel; +wire basesoc_shared_cyc; +wire basesoc_shared_stb; +reg basesoc_shared_ack = 1'd0; +wire basesoc_shared_we; +wire [2:0] basesoc_shared_cti; +wire [1:0] basesoc_shared_bte; +wire basesoc_shared_err; +wire [3:0] basesoc_request; +reg [1:0] basesoc_grant = 2'd0; +reg [3:0] basesoc_slave_sel = 4'd0; +reg [3:0] basesoc_slave_sel_r = 4'd0; +reg basesoc_error = 1'd0; +wire basesoc_wait; +wire basesoc_done; +reg [19:0] basesoc_count = 20'd1000000; +wire [13:0] basesoc_csr_bankarray_interface0_bank_bus_adr; +wire basesoc_csr_bankarray_interface0_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank0_reset0_re; +wire basesoc_csr_bankarray_csrbank0_reset0_r; +wire basesoc_csr_bankarray_csrbank0_reset0_we; +wire basesoc_csr_bankarray_csrbank0_reset0_w; +wire basesoc_csr_bankarray_csrbank0_scratch0_re; +wire [31:0] basesoc_csr_bankarray_csrbank0_scratch0_r; +wire basesoc_csr_bankarray_csrbank0_scratch0_we; +wire [31:0] basesoc_csr_bankarray_csrbank0_scratch0_w; +wire basesoc_csr_bankarray_csrbank0_bus_errors_re; +wire [31:0] basesoc_csr_bankarray_csrbank0_bus_errors_r; +wire basesoc_csr_bankarray_csrbank0_bus_errors_we; +wire [31:0] basesoc_csr_bankarray_csrbank0_bus_errors_w; +wire basesoc_csr_bankarray_csrbank0_sel; +wire [13:0] basesoc_csr_bankarray_interface1_bank_bus_adr; +wire basesoc_csr_bankarray_interface1_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank1_rst0_re; +wire basesoc_csr_bankarray_csrbank1_rst0_r; +wire basesoc_csr_bankarray_csrbank1_rst0_we; +wire basesoc_csr_bankarray_csrbank1_rst0_w; +wire basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_re; +wire [4:0] basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_r; +wire basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_we; +wire [4:0] basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_w; +wire basesoc_csr_bankarray_csrbank1_wlevel_en0_re; +wire basesoc_csr_bankarray_csrbank1_wlevel_en0_r; +wire basesoc_csr_bankarray_csrbank1_wlevel_en0_we; +wire basesoc_csr_bankarray_csrbank1_wlevel_en0_w; +wire basesoc_csr_bankarray_csrbank1_dly_sel0_re; +wire [1:0] basesoc_csr_bankarray_csrbank1_dly_sel0_r; +wire basesoc_csr_bankarray_csrbank1_dly_sel0_we; +wire [1:0] basesoc_csr_bankarray_csrbank1_dly_sel0_w; +wire basesoc_csr_bankarray_csrbank1_rdphase0_re; +wire [1:0] basesoc_csr_bankarray_csrbank1_rdphase0_r; +wire basesoc_csr_bankarray_csrbank1_rdphase0_we; +wire [1:0] basesoc_csr_bankarray_csrbank1_rdphase0_w; +wire basesoc_csr_bankarray_csrbank1_wrphase0_re; +wire [1:0] basesoc_csr_bankarray_csrbank1_wrphase0_r; +wire basesoc_csr_bankarray_csrbank1_wrphase0_we; +wire [1:0] basesoc_csr_bankarray_csrbank1_wrphase0_w; +wire basesoc_csr_bankarray_csrbank1_sel; +wire [13:0] basesoc_csr_bankarray_sram_bus_adr; +wire basesoc_csr_bankarray_sram_bus_we; +wire [31:0] basesoc_csr_bankarray_sram_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_sram_bus_dat_r = 32'd0; +wire [5:0] basesoc_csr_bankarray_adr; +wire [7:0] basesoc_csr_bankarray_dat_r; +wire basesoc_csr_bankarray_sel; +reg basesoc_csr_bankarray_sel_r = 1'd0; +wire [13:0] basesoc_csr_bankarray_interface2_bank_bus_adr; +wire basesoc_csr_bankarray_interface2_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank2_out0_re; +wire [7:0] basesoc_csr_bankarray_csrbank2_out0_r; +wire basesoc_csr_bankarray_csrbank2_out0_we; +wire [7:0] basesoc_csr_bankarray_csrbank2_out0_w; +wire basesoc_csr_bankarray_csrbank2_sel; +wire [13:0] basesoc_csr_bankarray_interface3_bank_bus_adr; +wire basesoc_csr_bankarray_interface3_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank3_sector1_re; +wire [15:0] basesoc_csr_bankarray_csrbank3_sector1_r; +wire basesoc_csr_bankarray_csrbank3_sector1_we; +wire [15:0] basesoc_csr_bankarray_csrbank3_sector1_w; +wire basesoc_csr_bankarray_csrbank3_sector0_re; +wire [31:0] basesoc_csr_bankarray_csrbank3_sector0_r; +wire basesoc_csr_bankarray_csrbank3_sector0_we; +wire [31:0] basesoc_csr_bankarray_csrbank3_sector0_w; +wire basesoc_csr_bankarray_csrbank3_base1_re; +wire [31:0] basesoc_csr_bankarray_csrbank3_base1_r; +wire basesoc_csr_bankarray_csrbank3_base1_we; +wire [31:0] basesoc_csr_bankarray_csrbank3_base1_w; +wire basesoc_csr_bankarray_csrbank3_base0_re; +wire [31:0] basesoc_csr_bankarray_csrbank3_base0_r; +wire basesoc_csr_bankarray_csrbank3_base0_we; +wire [31:0] basesoc_csr_bankarray_csrbank3_base0_w; +wire basesoc_csr_bankarray_csrbank3_done_re; +wire basesoc_csr_bankarray_csrbank3_done_r; +wire basesoc_csr_bankarray_csrbank3_done_we; +wire basesoc_csr_bankarray_csrbank3_done_w; +wire basesoc_csr_bankarray_csrbank3_error_re; +wire basesoc_csr_bankarray_csrbank3_error_r; +wire basesoc_csr_bankarray_csrbank3_error_we; +wire basesoc_csr_bankarray_csrbank3_error_w; +wire basesoc_csr_bankarray_csrbank3_sel; +wire [13:0] basesoc_csr_bankarray_interface4_bank_bus_adr; +wire basesoc_csr_bankarray_interface4_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank4_enable0_re; +wire basesoc_csr_bankarray_csrbank4_enable0_r; +wire basesoc_csr_bankarray_csrbank4_enable0_we; +wire basesoc_csr_bankarray_csrbank4_enable0_w; +wire basesoc_csr_bankarray_csrbank4_status_re; +wire [3:0] basesoc_csr_bankarray_csrbank4_status_r; +wire basesoc_csr_bankarray_csrbank4_status_we; +wire [3:0] basesoc_csr_bankarray_csrbank4_status_w; +wire basesoc_csr_bankarray_csrbank4_sel; +wire [13:0] basesoc_csr_bankarray_interface5_bank_bus_adr; +wire basesoc_csr_bankarray_interface5_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank5_sector1_re; +wire [15:0] basesoc_csr_bankarray_csrbank5_sector1_r; +wire basesoc_csr_bankarray_csrbank5_sector1_we; +wire [15:0] basesoc_csr_bankarray_csrbank5_sector1_w; +wire basesoc_csr_bankarray_csrbank5_sector0_re; +wire [31:0] basesoc_csr_bankarray_csrbank5_sector0_r; +wire basesoc_csr_bankarray_csrbank5_sector0_we; +wire [31:0] basesoc_csr_bankarray_csrbank5_sector0_w; +wire basesoc_csr_bankarray_csrbank5_base1_re; +wire [31:0] basesoc_csr_bankarray_csrbank5_base1_r; +wire basesoc_csr_bankarray_csrbank5_base1_we; +wire [31:0] basesoc_csr_bankarray_csrbank5_base1_w; +wire basesoc_csr_bankarray_csrbank5_base0_re; +wire [31:0] basesoc_csr_bankarray_csrbank5_base0_r; +wire basesoc_csr_bankarray_csrbank5_base0_we; +wire [31:0] basesoc_csr_bankarray_csrbank5_base0_w; +wire basesoc_csr_bankarray_csrbank5_done_re; +wire basesoc_csr_bankarray_csrbank5_done_r; +wire basesoc_csr_bankarray_csrbank5_done_we; +wire basesoc_csr_bankarray_csrbank5_done_w; +wire basesoc_csr_bankarray_csrbank5_error_re; +wire basesoc_csr_bankarray_csrbank5_error_r; +wire basesoc_csr_bankarray_csrbank5_error_we; +wire basesoc_csr_bankarray_csrbank5_error_w; +wire basesoc_csr_bankarray_csrbank5_sel; +wire [13:0] basesoc_csr_bankarray_interface6_bank_bus_adr; +wire basesoc_csr_bankarray_interface6_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank6_dfii_control0_re; +wire [3:0] basesoc_csr_bankarray_csrbank6_dfii_control0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_control0_we; +wire [3:0] basesoc_csr_bankarray_csrbank6_dfii_control0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_re; +wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_we; +wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_re; +wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_we; +wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_re; +wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_we; +wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_re; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_we; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_re; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_we; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_re; +wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_we; +wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_re; +wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_we; +wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_re; +wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_we; +wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_re; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_we; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_re; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_we; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_re; +wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_we; +wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_re; +wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_we; +wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_re; +wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_we; +wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_re; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_we; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_re; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_we; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_re; +wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_we; +wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_re; +wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_we; +wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_re; +wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_we; +wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_re; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_we; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_w; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_re; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_r; +wire basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_we; +wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_w; +wire basesoc_csr_bankarray_csrbank6_sel; +wire [13:0] basesoc_csr_bankarray_interface7_bank_bus_adr; +wire basesoc_csr_bankarray_interface7_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank7_load0_re; +wire [31:0] basesoc_csr_bankarray_csrbank7_load0_r; +wire basesoc_csr_bankarray_csrbank7_load0_we; +wire [31:0] basesoc_csr_bankarray_csrbank7_load0_w; +wire basesoc_csr_bankarray_csrbank7_reload0_re; +wire [31:0] basesoc_csr_bankarray_csrbank7_reload0_r; +wire basesoc_csr_bankarray_csrbank7_reload0_we; +wire [31:0] basesoc_csr_bankarray_csrbank7_reload0_w; +wire basesoc_csr_bankarray_csrbank7_en0_re; +wire basesoc_csr_bankarray_csrbank7_en0_r; +wire basesoc_csr_bankarray_csrbank7_en0_we; +wire basesoc_csr_bankarray_csrbank7_en0_w; +wire basesoc_csr_bankarray_csrbank7_update_value0_re; +wire basesoc_csr_bankarray_csrbank7_update_value0_r; +wire basesoc_csr_bankarray_csrbank7_update_value0_we; +wire basesoc_csr_bankarray_csrbank7_update_value0_w; +wire basesoc_csr_bankarray_csrbank7_value_re; +wire [31:0] basesoc_csr_bankarray_csrbank7_value_r; +wire basesoc_csr_bankarray_csrbank7_value_we; +wire [31:0] basesoc_csr_bankarray_csrbank7_value_w; +wire basesoc_csr_bankarray_csrbank7_ev_status_re; +wire basesoc_csr_bankarray_csrbank7_ev_status_r; +wire basesoc_csr_bankarray_csrbank7_ev_status_we; +wire basesoc_csr_bankarray_csrbank7_ev_status_w; +wire basesoc_csr_bankarray_csrbank7_ev_pending_re; +wire basesoc_csr_bankarray_csrbank7_ev_pending_r; +wire basesoc_csr_bankarray_csrbank7_ev_pending_we; +wire basesoc_csr_bankarray_csrbank7_ev_pending_w; +wire basesoc_csr_bankarray_csrbank7_ev_enable0_re; +wire basesoc_csr_bankarray_csrbank7_ev_enable0_r; +wire basesoc_csr_bankarray_csrbank7_ev_enable0_we; +wire basesoc_csr_bankarray_csrbank7_ev_enable0_w; +wire basesoc_csr_bankarray_csrbank7_sel; +wire [13:0] basesoc_csr_bankarray_interface8_bank_bus_adr; +wire basesoc_csr_bankarray_interface8_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank8_txfull_re; +wire basesoc_csr_bankarray_csrbank8_txfull_r; +wire basesoc_csr_bankarray_csrbank8_txfull_we; +wire basesoc_csr_bankarray_csrbank8_txfull_w; +wire basesoc_csr_bankarray_csrbank8_rxempty_re; +wire basesoc_csr_bankarray_csrbank8_rxempty_r; +wire basesoc_csr_bankarray_csrbank8_rxempty_we; +wire basesoc_csr_bankarray_csrbank8_rxempty_w; +wire basesoc_csr_bankarray_csrbank8_ev_status_re; +wire [1:0] basesoc_csr_bankarray_csrbank8_ev_status_r; +wire basesoc_csr_bankarray_csrbank8_ev_status_we; +wire [1:0] basesoc_csr_bankarray_csrbank8_ev_status_w; +wire basesoc_csr_bankarray_csrbank8_ev_pending_re; +wire [1:0] basesoc_csr_bankarray_csrbank8_ev_pending_r; +wire basesoc_csr_bankarray_csrbank8_ev_pending_we; +wire [1:0] basesoc_csr_bankarray_csrbank8_ev_pending_w; +wire basesoc_csr_bankarray_csrbank8_ev_enable0_re; +wire [1:0] basesoc_csr_bankarray_csrbank8_ev_enable0_r; +wire basesoc_csr_bankarray_csrbank8_ev_enable0_we; +wire [1:0] basesoc_csr_bankarray_csrbank8_ev_enable0_w; +wire basesoc_csr_bankarray_csrbank8_txempty_re; +wire basesoc_csr_bankarray_csrbank8_txempty_r; +wire basesoc_csr_bankarray_csrbank8_txempty_we; +wire basesoc_csr_bankarray_csrbank8_txempty_w; +wire basesoc_csr_bankarray_csrbank8_rxfull_re; +wire basesoc_csr_bankarray_csrbank8_rxfull_r; +wire basesoc_csr_bankarray_csrbank8_rxfull_we; +wire basesoc_csr_bankarray_csrbank8_rxfull_w; +wire basesoc_csr_bankarray_csrbank8_sel; +wire [13:0] basesoc_csr_bankarray_interface9_bank_bus_adr; +wire basesoc_csr_bankarray_interface9_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface9_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface9_bank_bus_dat_r = 32'd0; +wire basesoc_csr_bankarray_csrbank9_tuning_word0_re; +wire [31:0] basesoc_csr_bankarray_csrbank9_tuning_word0_r; +wire basesoc_csr_bankarray_csrbank9_tuning_word0_we; +wire [31:0] basesoc_csr_bankarray_csrbank9_tuning_word0_w; +wire basesoc_csr_bankarray_csrbank9_sel; +wire [13:0] basesoc_csr_interconnect_adr; +wire basesoc_csr_interconnect_we; +wire [31:0] basesoc_csr_interconnect_dat_w; +wire [31:0] basesoc_csr_interconnect_dat_r; +reg [1:0] basesoc_state = 2'd0; +reg [1:0] basesoc_next_state = 2'd0; +reg [31:0] basesoc_basesoc_dat_w_basesoc_next_value0 = 32'd0; +reg basesoc_basesoc_dat_w_basesoc_next_value_ce0 = 1'd0; +reg [13:0] basesoc_basesoc_adr_basesoc_next_value1 = 14'd0; +reg basesoc_basesoc_adr_basesoc_next_value_ce1 = 1'd0; +reg basesoc_basesoc_we_basesoc_next_value2 = 1'd0; +reg basesoc_basesoc_we_basesoc_next_value_ce2 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [13:0] rhs_array_muxed1 = 14'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [13:0] rhs_array_muxed7 = 14'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [20:0] rhs_array_muxed12 = 21'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [20:0] rhs_array_muxed15 = 21'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [20:0] rhs_array_muxed18 = 21'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [20:0] rhs_array_muxed21 = 21'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [20:0] rhs_array_muxed24 = 21'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [20:0] rhs_array_muxed27 = 21'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [20:0] rhs_array_muxed30 = 21'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [20:0] rhs_array_muxed33 = 21'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [31:0] rhs_array_muxed36 = 32'd0; +reg [31:0] rhs_array_muxed37 = 32'd0; +reg [3:0] rhs_array_muxed38 = 4'd0; +reg rhs_array_muxed39 = 1'd0; +reg rhs_array_muxed40 = 1'd0; +reg rhs_array_muxed41 = 1'd0; +reg [2:0] rhs_array_muxed42 = 3'd0; +reg [1:0] rhs_array_muxed43 = 2'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [13:0] array_muxed1 = 14'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [13:0] array_muxed8 = 14'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [13:0] array_muxed15 = 14'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [13:0] array_muxed22 = 14'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl1_expr; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_expr; +wire xilinxasyncresetsynchronizerimpl3; +wire xilinxasyncresetsynchronizerimpl3_rst_meta; +wire xilinxasyncresetsynchronizerimpl4; +wire xilinxasyncresetsynchronizerimpl4_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl4_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl4_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl5_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl5_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl6_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl6_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl7_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl7_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl8_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl8_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl9_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl9_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl10_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl10_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl11_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl11_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl12_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl12_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl13_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl13_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl14_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl14_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl15_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl15_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl16_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl16_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl17_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl17_regs1 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl18_regs0 = 2'd0; +(* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl18_regs1 = 2'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl19_regs0 = 2'd0; +(* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl19_regs1 = 2'd0; +wire xilinxasyncresetsynchronizerimpl5; +wire xilinxasyncresetsynchronizerimpl5_rst_meta; +wire xilinxasyncresetsynchronizerimpl6; +wire xilinxasyncresetsynchronizerimpl6_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl20_regs0 = 4'd0; +(* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl20_regs1 = 4'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl21_regs0 = 4'd0; +(* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl21_regs1 = 4'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl22_regs0 = 4'd0; +(* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl22_regs1 = 4'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl23_regs0 = 4'd0; +(* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl23_regs1 = 4'd0; + +assign cpu_reset_1 = soccontroller_reset; +assign crg_rst = soccontroller_reset_re; +assign soccontroller_bus_error = basesoc_error; +always @(*) begin + cpu_interrupt <= 32'd0; + cpu_interrupt[1] <= timer_irq; + cpu_interrupt[0] <= uart_irq; +end +assign soccontroller_reset = soccontroller_reset_re; +assign soccontroller_bus_errors_status = soccontroller_bus_errors; +assign basesoc_adr = basesoc_ram_bus_adr[13:0]; +assign basesoc_ram_bus_dat_r = basesoc_dat_r; +always @(*) begin + ram_we <= 4'd0; + ram_we[0] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[0]); + ram_we[1] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[1]); + ram_we[2] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[2]); + ram_we[3] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[3]); +end +assign ram_adr = ram_bus_ram_bus_adr[10:0]; +assign ram_bus_ram_bus_dat_r = ram_dat_r; +assign ram_dat_w = ram_bus_ram_bus_dat_w; +assign uart_uart_sink_valid = uart_phy_source_valid; +assign uart_phy_source_ready = uart_uart_sink_ready; +assign uart_uart_sink_first = uart_phy_source_first; +assign uart_uart_sink_last = uart_phy_source_last; +assign uart_uart_sink_payload_data = uart_phy_source_payload_data; +assign uart_phy_sink_valid = uart_uart_source_valid; +assign uart_uart_source_ready = uart_phy_sink_ready; +assign uart_phy_sink_first = uart_uart_source_first; +assign uart_phy_sink_last = uart_uart_source_last; +assign uart_phy_sink_payload_data = uart_uart_source_payload_data; +assign uart_tx_fifo_sink_valid = uart_rxtx_re; +assign uart_tx_fifo_sink_payload_data = uart_rxtx_r; +assign uart_txfull_status = (~uart_tx_fifo_sink_ready); +assign uart_txempty_status = (~uart_tx_fifo_source_valid); +assign uart_uart_source_valid = uart_tx_fifo_source_valid; +assign uart_tx_fifo_source_ready = uart_uart_source_ready; +assign uart_uart_source_first = uart_tx_fifo_source_first; +assign uart_uart_source_last = uart_tx_fifo_source_last; +assign uart_uart_source_payload_data = uart_tx_fifo_source_payload_data; +assign uart_tx_trigger = (~uart_tx_fifo_sink_ready); +assign uart_rx_fifo_sink_valid = uart_uart_sink_valid; +assign uart_uart_sink_ready = uart_rx_fifo_sink_ready; +assign uart_rx_fifo_sink_first = uart_uart_sink_first; +assign uart_rx_fifo_sink_last = uart_uart_sink_last; +assign uart_rx_fifo_sink_payload_data = uart_uart_sink_payload_data; +assign uart_rxempty_status = (~uart_rx_fifo_source_valid); +assign uart_rxfull_status = (~uart_rx_fifo_sink_ready); +assign uart_rxtx_w = uart_rx_fifo_source_payload_data; +assign uart_rx_fifo_source_ready = (uart_rx_clear | (1'd0 & uart_rxtx_we)); +assign uart_rx_trigger = (~uart_rx_fifo_source_valid); +assign uart_tx0 = uart_tx_status; +assign uart_tx1 = uart_tx_pending; +always @(*) begin + uart_tx_clear <= 1'd0; + if ((uart_pending_re & uart_pending_r[0])) begin + uart_tx_clear <= 1'd1; + end +end +assign uart_rx0 = uart_rx_status; +assign uart_rx1 = uart_rx_pending; +always @(*) begin + uart_rx_clear <= 1'd0; + if ((uart_pending_re & uart_pending_r[1])) begin + uart_rx_clear <= 1'd1; + end +end +assign uart_irq = ((uart_pending_status[0] & uart_enable_storage[0]) | (uart_pending_status[1] & uart_enable_storage[1])); +assign uart_tx_status = uart_tx_trigger; +assign uart_rx_status = uart_rx_trigger; +assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_last, uart_tx_fifo_fifo_in_first, uart_tx_fifo_fifo_in_payload_data}; +assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout; +assign uart_tx_fifo_sink_ready = uart_tx_fifo_syncfifo_writable; +assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_valid; +assign uart_tx_fifo_fifo_in_first = uart_tx_fifo_sink_first; +assign uart_tx_fifo_fifo_in_last = uart_tx_fifo_sink_last; +assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data; +assign uart_tx_fifo_source_valid = uart_tx_fifo_readable; +assign uart_tx_fifo_source_first = uart_tx_fifo_fifo_out_first; +assign uart_tx_fifo_source_last = uart_tx_fifo_fifo_out_last; +assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data; +assign uart_tx_fifo_re = uart_tx_fifo_source_ready; +assign uart_tx_fifo_syncfifo_re = (uart_tx_fifo_syncfifo_readable & ((~uart_tx_fifo_readable) | uart_tx_fifo_re)); +assign uart_tx_fifo_level1 = (uart_tx_fifo_level0 + uart_tx_fifo_readable); +always @(*) begin + uart_tx_fifo_wrport_adr <= 4'd0; + if (uart_tx_fifo_replace) begin + uart_tx_fifo_wrport_adr <= (uart_tx_fifo_produce - 1'd1); + end else begin + uart_tx_fifo_wrport_adr <= uart_tx_fifo_produce; + end +end +assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din; +assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace)); +assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re); +assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume; +assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r; +assign uart_tx_fifo_rdport_re = uart_tx_fifo_do_read; +assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level0 != 5'd16); +assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level0 != 1'd0); +assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_last, uart_rx_fifo_fifo_in_first, uart_rx_fifo_fifo_in_payload_data}; +assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout; +assign uart_rx_fifo_sink_ready = uart_rx_fifo_syncfifo_writable; +assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_valid; +assign uart_rx_fifo_fifo_in_first = uart_rx_fifo_sink_first; +assign uart_rx_fifo_fifo_in_last = uart_rx_fifo_sink_last; +assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data; +assign uart_rx_fifo_source_valid = uart_rx_fifo_readable; +assign uart_rx_fifo_source_first = uart_rx_fifo_fifo_out_first; +assign uart_rx_fifo_source_last = uart_rx_fifo_fifo_out_last; +assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data; +assign uart_rx_fifo_re = uart_rx_fifo_source_ready; +assign uart_rx_fifo_syncfifo_re = (uart_rx_fifo_syncfifo_readable & ((~uart_rx_fifo_readable) | uart_rx_fifo_re)); +assign uart_rx_fifo_level1 = (uart_rx_fifo_level0 + uart_rx_fifo_readable); +always @(*) begin + uart_rx_fifo_wrport_adr <= 4'd0; + if (uart_rx_fifo_replace) begin + uart_rx_fifo_wrport_adr <= (uart_rx_fifo_produce - 1'd1); + end else begin + uart_rx_fifo_wrport_adr <= uart_rx_fifo_produce; + end +end +assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din; +assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace)); +assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re); +assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume; +assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r; +assign uart_rx_fifo_rdport_re = uart_rx_fifo_do_read; +assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level0 != 5'd16); +assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level0 != 1'd0); +assign timer_zero_trigger = (timer_value != 1'd0); +assign timer_zero0 = timer_zero_status; +assign timer_zero1 = timer_zero_pending; +always @(*) begin + timer_zero_clear <= 1'd0; + if ((timer_pending_re & timer_pending_r)) begin + timer_zero_clear <= 1'd1; + end +end +assign timer_irq = (timer_pending_status & timer_enable_storage); +assign timer_zero_status = timer_zero_trigger; +assign crg_reset = ((~cpu_reset) | crg_rst); +assign crg_clkin = clk100; +assign sys_clk = crg_clkout_buf0; +assign sys4x_clk = crg_clkout_buf1; +assign sys4x_dqs_clk = crg_clkout_buf2; +assign idelay_clk = crg_clkout_buf3; +assign clk100_clk = crg_clkout_buf4; +assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); +assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); +always @(*) begin + a7ddrphy_dfi_p0_rddata <= 32'd0; + a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; + a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; + a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; + a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; + a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; + a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; + a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; + a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; + a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; + a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; + a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; + a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; + a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; + a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; + a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; + a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; + a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; + a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; + a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; + a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; + a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; + a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; + a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; + a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; + a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; + a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; + a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; + a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; + a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; + a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; + a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; + a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; +end +always @(*) begin + a7ddrphy_dfi_p1_rddata <= 32'd0; + a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; + a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; + a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; + a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; + a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; + a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; + a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; + a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; + a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; + a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; + a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; + a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; + a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; + a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; + a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; + a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; + a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; + a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; + a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; + a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; + a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; + a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; + a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; + a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; + a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; + a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; + a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; + a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; + a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; + a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; + a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; + a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; +end +always @(*) begin + a7ddrphy_dfi_p2_rddata <= 32'd0; + a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; + a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; + a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; + a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; + a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; + a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; + a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; + a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; + a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; + a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; + a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; + a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; + a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; + a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; + a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; + a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; + a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; + a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; + a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; + a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; + a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; + a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; + a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; + a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; + a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; + a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; + a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; + a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; + a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; + a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; + a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; + a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; +end +always @(*) begin + a7ddrphy_dfi_p3_rddata <= 32'd0; + a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; + a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; + a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; + a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; + a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; + a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; + a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; + a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; + a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; + a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; + a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; + a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; + a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; + a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; + a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; + a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; + a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; + a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; + a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; + a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; + a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; + a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; + a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; + a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; + a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; + a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; + a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; + a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; + a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; + a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; + a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; + a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; +end +assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); +assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); +assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); +assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); +assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; +always @(*) begin + a7ddrphy_dqs_oe <= 1'd0; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqs_oe <= 1'd1; + end else begin + a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; + end +end +assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); +assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); +always @(*) begin + a7ddrphy_dqspattern_o0 <= 8'd0; + a7ddrphy_dqspattern_o0 <= 7'd85; + if (a7ddrphy_dqspattern0) begin + a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (a7ddrphy_dqspattern1) begin + a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqspattern_o0 <= 1'd0; + if (a7ddrphy_wlevel_strobe_re) begin + a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +end +always @(*) begin + a7ddrphy_bitslip00 <= 8'd0; + case (a7ddrphy_bitslip0_value0) + 1'd0: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip10 <= 8'd0; + case (a7ddrphy_bitslip1_value0) + 1'd0: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip01 <= 8'd0; + case (a7ddrphy_bitslip0_value1) + 1'd0: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip11 <= 8'd0; + case (a7ddrphy_bitslip1_value1) + 1'd0: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip02 <= 8'd0; + case (a7ddrphy_bitslip0_value2) + 1'd0: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip04 <= 8'd0; + case (a7ddrphy_bitslip0_value3) + 1'd0: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip12 <= 8'd0; + case (a7ddrphy_bitslip1_value2) + 1'd0: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip14 <= 8'd0; + case (a7ddrphy_bitslip1_value3) + 1'd0: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip20 <= 8'd0; + case (a7ddrphy_bitslip2_value0) + 1'd0: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip22 <= 8'd0; + case (a7ddrphy_bitslip2_value1) + 1'd0: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip30 <= 8'd0; + case (a7ddrphy_bitslip3_value0) + 1'd0: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip32 <= 8'd0; + case (a7ddrphy_bitslip3_value1) + 1'd0: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip40 <= 8'd0; + case (a7ddrphy_bitslip4_value0) + 1'd0: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip42 <= 8'd0; + case (a7ddrphy_bitslip4_value1) + 1'd0: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip50 <= 8'd0; + case (a7ddrphy_bitslip5_value0) + 1'd0: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip52 <= 8'd0; + case (a7ddrphy_bitslip5_value1) + 1'd0: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip60 <= 8'd0; + case (a7ddrphy_bitslip6_value0) + 1'd0: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip62 <= 8'd0; + case (a7ddrphy_bitslip6_value1) + 1'd0: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip70 <= 8'd0; + case (a7ddrphy_bitslip7_value0) + 1'd0: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip72 <= 8'd0; + case (a7ddrphy_bitslip7_value1) + 1'd0: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip80 <= 8'd0; + case (a7ddrphy_bitslip8_value0) + 1'd0: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip82 <= 8'd0; + case (a7ddrphy_bitslip8_value1) + 1'd0: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip90 <= 8'd0; + case (a7ddrphy_bitslip9_value0) + 1'd0: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip92 <= 8'd0; + case (a7ddrphy_bitslip9_value1) + 1'd0: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip100 <= 8'd0; + case (a7ddrphy_bitslip10_value0) + 1'd0: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip102 <= 8'd0; + case (a7ddrphy_bitslip10_value1) + 1'd0: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip110 <= 8'd0; + case (a7ddrphy_bitslip11_value0) + 1'd0: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip112 <= 8'd0; + case (a7ddrphy_bitslip11_value1) + 1'd0: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip120 <= 8'd0; + case (a7ddrphy_bitslip12_value0) + 1'd0: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip122 <= 8'd0; + case (a7ddrphy_bitslip12_value1) + 1'd0: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip130 <= 8'd0; + case (a7ddrphy_bitslip13_value0) + 1'd0: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip132 <= 8'd0; + case (a7ddrphy_bitslip13_value1) + 1'd0: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip140 <= 8'd0; + case (a7ddrphy_bitslip14_value0) + 1'd0: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip142 <= 8'd0; + case (a7ddrphy_bitslip14_value1) + 1'd0: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip150 <= 8'd0; + case (a7ddrphy_bitslip15_value0) + 1'd0: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip152 <= 8'd0; + case (a7ddrphy_bitslip15_value1) + 1'd0: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; + end + endcase +end +assign a7ddrphy_dfi_p0_address = sdram_master_p0_address; +assign a7ddrphy_dfi_p0_bank = sdram_master_p0_bank; +assign a7ddrphy_dfi_p0_cas_n = sdram_master_p0_cas_n; +assign a7ddrphy_dfi_p0_cs_n = sdram_master_p0_cs_n; +assign a7ddrphy_dfi_p0_ras_n = sdram_master_p0_ras_n; +assign a7ddrphy_dfi_p0_we_n = sdram_master_p0_we_n; +assign a7ddrphy_dfi_p0_cke = sdram_master_p0_cke; +assign a7ddrphy_dfi_p0_odt = sdram_master_p0_odt; +assign a7ddrphy_dfi_p0_reset_n = sdram_master_p0_reset_n; +assign a7ddrphy_dfi_p0_act_n = sdram_master_p0_act_n; +assign a7ddrphy_dfi_p0_wrdata = sdram_master_p0_wrdata; +assign a7ddrphy_dfi_p0_wrdata_en = sdram_master_p0_wrdata_en; +assign a7ddrphy_dfi_p0_wrdata_mask = sdram_master_p0_wrdata_mask; +assign a7ddrphy_dfi_p0_rddata_en = sdram_master_p0_rddata_en; +assign sdram_master_p0_rddata = a7ddrphy_dfi_p0_rddata; +assign sdram_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; +assign a7ddrphy_dfi_p1_address = sdram_master_p1_address; +assign a7ddrphy_dfi_p1_bank = sdram_master_p1_bank; +assign a7ddrphy_dfi_p1_cas_n = sdram_master_p1_cas_n; +assign a7ddrphy_dfi_p1_cs_n = sdram_master_p1_cs_n; +assign a7ddrphy_dfi_p1_ras_n = sdram_master_p1_ras_n; +assign a7ddrphy_dfi_p1_we_n = sdram_master_p1_we_n; +assign a7ddrphy_dfi_p1_cke = sdram_master_p1_cke; +assign a7ddrphy_dfi_p1_odt = sdram_master_p1_odt; +assign a7ddrphy_dfi_p1_reset_n = sdram_master_p1_reset_n; +assign a7ddrphy_dfi_p1_act_n = sdram_master_p1_act_n; +assign a7ddrphy_dfi_p1_wrdata = sdram_master_p1_wrdata; +assign a7ddrphy_dfi_p1_wrdata_en = sdram_master_p1_wrdata_en; +assign a7ddrphy_dfi_p1_wrdata_mask = sdram_master_p1_wrdata_mask; +assign a7ddrphy_dfi_p1_rddata_en = sdram_master_p1_rddata_en; +assign sdram_master_p1_rddata = a7ddrphy_dfi_p1_rddata; +assign sdram_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; +assign a7ddrphy_dfi_p2_address = sdram_master_p2_address; +assign a7ddrphy_dfi_p2_bank = sdram_master_p2_bank; +assign a7ddrphy_dfi_p2_cas_n = sdram_master_p2_cas_n; +assign a7ddrphy_dfi_p2_cs_n = sdram_master_p2_cs_n; +assign a7ddrphy_dfi_p2_ras_n = sdram_master_p2_ras_n; +assign a7ddrphy_dfi_p2_we_n = sdram_master_p2_we_n; +assign a7ddrphy_dfi_p2_cke = sdram_master_p2_cke; +assign a7ddrphy_dfi_p2_odt = sdram_master_p2_odt; +assign a7ddrphy_dfi_p2_reset_n = sdram_master_p2_reset_n; +assign a7ddrphy_dfi_p2_act_n = sdram_master_p2_act_n; +assign a7ddrphy_dfi_p2_wrdata = sdram_master_p2_wrdata; +assign a7ddrphy_dfi_p2_wrdata_en = sdram_master_p2_wrdata_en; +assign a7ddrphy_dfi_p2_wrdata_mask = sdram_master_p2_wrdata_mask; +assign a7ddrphy_dfi_p2_rddata_en = sdram_master_p2_rddata_en; +assign sdram_master_p2_rddata = a7ddrphy_dfi_p2_rddata; +assign sdram_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; +assign a7ddrphy_dfi_p3_address = sdram_master_p3_address; +assign a7ddrphy_dfi_p3_bank = sdram_master_p3_bank; +assign a7ddrphy_dfi_p3_cas_n = sdram_master_p3_cas_n; +assign a7ddrphy_dfi_p3_cs_n = sdram_master_p3_cs_n; +assign a7ddrphy_dfi_p3_ras_n = sdram_master_p3_ras_n; +assign a7ddrphy_dfi_p3_we_n = sdram_master_p3_we_n; +assign a7ddrphy_dfi_p3_cke = sdram_master_p3_cke; +assign a7ddrphy_dfi_p3_odt = sdram_master_p3_odt; +assign a7ddrphy_dfi_p3_reset_n = sdram_master_p3_reset_n; +assign a7ddrphy_dfi_p3_act_n = sdram_master_p3_act_n; +assign a7ddrphy_dfi_p3_wrdata = sdram_master_p3_wrdata; +assign a7ddrphy_dfi_p3_wrdata_en = sdram_master_p3_wrdata_en; +assign a7ddrphy_dfi_p3_wrdata_mask = sdram_master_p3_wrdata_mask; +assign a7ddrphy_dfi_p3_rddata_en = sdram_master_p3_rddata_en; +assign sdram_master_p3_rddata = a7ddrphy_dfi_p3_rddata; +assign sdram_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; +assign sdram_slave_p0_address = sdram_dfi_p0_address; +assign sdram_slave_p0_bank = sdram_dfi_p0_bank; +assign sdram_slave_p0_cas_n = sdram_dfi_p0_cas_n; +assign sdram_slave_p0_cs_n = sdram_dfi_p0_cs_n; +assign sdram_slave_p0_ras_n = sdram_dfi_p0_ras_n; +assign sdram_slave_p0_we_n = sdram_dfi_p0_we_n; +assign sdram_slave_p0_cke = sdram_dfi_p0_cke; +assign sdram_slave_p0_odt = sdram_dfi_p0_odt; +assign sdram_slave_p0_reset_n = sdram_dfi_p0_reset_n; +assign sdram_slave_p0_act_n = sdram_dfi_p0_act_n; +assign sdram_slave_p0_wrdata = sdram_dfi_p0_wrdata; +assign sdram_slave_p0_wrdata_en = sdram_dfi_p0_wrdata_en; +assign sdram_slave_p0_wrdata_mask = sdram_dfi_p0_wrdata_mask; +assign sdram_slave_p0_rddata_en = sdram_dfi_p0_rddata_en; +assign sdram_dfi_p0_rddata = sdram_slave_p0_rddata; +assign sdram_dfi_p0_rddata_valid = sdram_slave_p0_rddata_valid; +assign sdram_slave_p1_address = sdram_dfi_p1_address; +assign sdram_slave_p1_bank = sdram_dfi_p1_bank; +assign sdram_slave_p1_cas_n = sdram_dfi_p1_cas_n; +assign sdram_slave_p1_cs_n = sdram_dfi_p1_cs_n; +assign sdram_slave_p1_ras_n = sdram_dfi_p1_ras_n; +assign sdram_slave_p1_we_n = sdram_dfi_p1_we_n; +assign sdram_slave_p1_cke = sdram_dfi_p1_cke; +assign sdram_slave_p1_odt = sdram_dfi_p1_odt; +assign sdram_slave_p1_reset_n = sdram_dfi_p1_reset_n; +assign sdram_slave_p1_act_n = sdram_dfi_p1_act_n; +assign sdram_slave_p1_wrdata = sdram_dfi_p1_wrdata; +assign sdram_slave_p1_wrdata_en = sdram_dfi_p1_wrdata_en; +assign sdram_slave_p1_wrdata_mask = sdram_dfi_p1_wrdata_mask; +assign sdram_slave_p1_rddata_en = sdram_dfi_p1_rddata_en; +assign sdram_dfi_p1_rddata = sdram_slave_p1_rddata; +assign sdram_dfi_p1_rddata_valid = sdram_slave_p1_rddata_valid; +assign sdram_slave_p2_address = sdram_dfi_p2_address; +assign sdram_slave_p2_bank = sdram_dfi_p2_bank; +assign sdram_slave_p2_cas_n = sdram_dfi_p2_cas_n; +assign sdram_slave_p2_cs_n = sdram_dfi_p2_cs_n; +assign sdram_slave_p2_ras_n = sdram_dfi_p2_ras_n; +assign sdram_slave_p2_we_n = sdram_dfi_p2_we_n; +assign sdram_slave_p2_cke = sdram_dfi_p2_cke; +assign sdram_slave_p2_odt = sdram_dfi_p2_odt; +assign sdram_slave_p2_reset_n = sdram_dfi_p2_reset_n; +assign sdram_slave_p2_act_n = sdram_dfi_p2_act_n; +assign sdram_slave_p2_wrdata = sdram_dfi_p2_wrdata; +assign sdram_slave_p2_wrdata_en = sdram_dfi_p2_wrdata_en; +assign sdram_slave_p2_wrdata_mask = sdram_dfi_p2_wrdata_mask; +assign sdram_slave_p2_rddata_en = sdram_dfi_p2_rddata_en; +assign sdram_dfi_p2_rddata = sdram_slave_p2_rddata; +assign sdram_dfi_p2_rddata_valid = sdram_slave_p2_rddata_valid; +assign sdram_slave_p3_address = sdram_dfi_p3_address; +assign sdram_slave_p3_bank = sdram_dfi_p3_bank; +assign sdram_slave_p3_cas_n = sdram_dfi_p3_cas_n; +assign sdram_slave_p3_cs_n = sdram_dfi_p3_cs_n; +assign sdram_slave_p3_ras_n = sdram_dfi_p3_ras_n; +assign sdram_slave_p3_we_n = sdram_dfi_p3_we_n; +assign sdram_slave_p3_cke = sdram_dfi_p3_cke; +assign sdram_slave_p3_odt = sdram_dfi_p3_odt; +assign sdram_slave_p3_reset_n = sdram_dfi_p3_reset_n; +assign sdram_slave_p3_act_n = sdram_dfi_p3_act_n; +assign sdram_slave_p3_wrdata = sdram_dfi_p3_wrdata; +assign sdram_slave_p3_wrdata_en = sdram_dfi_p3_wrdata_en; +assign sdram_slave_p3_wrdata_mask = sdram_dfi_p3_wrdata_mask; +assign sdram_slave_p3_rddata_en = sdram_dfi_p3_rddata_en; +assign sdram_dfi_p3_rddata = sdram_slave_p3_rddata; +assign sdram_dfi_p3_rddata_valid = sdram_slave_p3_rddata_valid; +always @(*) begin + sdram_master_p0_address <= 14'd0; + sdram_master_p0_bank <= 3'd0; + sdram_master_p0_cas_n <= 1'd1; + sdram_master_p0_cs_n <= 1'd1; + sdram_master_p0_ras_n <= 1'd1; + sdram_master_p0_we_n <= 1'd1; + sdram_master_p0_cke <= 1'd0; + sdram_master_p0_odt <= 1'd0; + sdram_master_p0_reset_n <= 1'd0; + sdram_master_p0_act_n <= 1'd1; + sdram_master_p0_wrdata <= 32'd0; + sdram_inti_p1_rddata <= 32'd0; + sdram_master_p0_wrdata_en <= 1'd0; + sdram_inti_p1_rddata_valid <= 1'd0; + sdram_master_p0_wrdata_mask <= 4'd0; + sdram_master_p0_rddata_en <= 1'd0; + sdram_master_p1_address <= 14'd0; + sdram_master_p1_bank <= 3'd0; + sdram_master_p1_cas_n <= 1'd1; + sdram_master_p1_cs_n <= 1'd1; + sdram_master_p1_ras_n <= 1'd1; + sdram_master_p1_we_n <= 1'd1; + sdram_master_p1_cke <= 1'd0; + sdram_master_p1_odt <= 1'd0; + sdram_master_p1_reset_n <= 1'd0; + sdram_master_p1_act_n <= 1'd1; + sdram_master_p1_wrdata <= 32'd0; + sdram_inti_p2_rddata <= 32'd0; + sdram_master_p1_wrdata_en <= 1'd0; + sdram_inti_p2_rddata_valid <= 1'd0; + sdram_master_p1_wrdata_mask <= 4'd0; + sdram_master_p1_rddata_en <= 1'd0; + sdram_master_p2_address <= 14'd0; + sdram_master_p2_bank <= 3'd0; + sdram_master_p2_cas_n <= 1'd1; + sdram_master_p2_cs_n <= 1'd1; + sdram_master_p2_ras_n <= 1'd1; + sdram_master_p2_we_n <= 1'd1; + sdram_master_p2_cke <= 1'd0; + sdram_master_p2_odt <= 1'd0; + sdram_master_p2_reset_n <= 1'd0; + sdram_master_p2_act_n <= 1'd1; + sdram_master_p2_wrdata <= 32'd0; + sdram_inti_p3_rddata <= 32'd0; + sdram_master_p2_wrdata_en <= 1'd0; + sdram_inti_p3_rddata_valid <= 1'd0; + sdram_master_p2_wrdata_mask <= 4'd0; + sdram_master_p2_rddata_en <= 1'd0; + sdram_master_p3_address <= 14'd0; + sdram_master_p3_bank <= 3'd0; + sdram_master_p3_cas_n <= 1'd1; + sdram_master_p3_cs_n <= 1'd1; + sdram_master_p3_ras_n <= 1'd1; + sdram_master_p3_we_n <= 1'd1; + sdram_master_p3_cke <= 1'd0; + sdram_master_p3_odt <= 1'd0; + sdram_master_p3_reset_n <= 1'd0; + sdram_master_p3_act_n <= 1'd1; + sdram_master_p3_wrdata <= 32'd0; + sdram_master_p3_wrdata_en <= 1'd0; + sdram_master_p3_wrdata_mask <= 4'd0; + sdram_master_p3_rddata_en <= 1'd0; + sdram_slave_p0_rddata <= 32'd0; + sdram_slave_p0_rddata_valid <= 1'd0; + sdram_slave_p1_rddata <= 32'd0; + sdram_slave_p1_rddata_valid <= 1'd0; + sdram_slave_p2_rddata <= 32'd0; + sdram_slave_p2_rddata_valid <= 1'd0; + sdram_slave_p3_rddata <= 32'd0; + sdram_slave_p3_rddata_valid <= 1'd0; + sdram_inti_p0_rddata <= 32'd0; + sdram_inti_p0_rddata_valid <= 1'd0; + if (sdram_sel) begin + sdram_master_p0_address <= sdram_slave_p0_address; + sdram_master_p0_bank <= sdram_slave_p0_bank; + sdram_master_p0_cas_n <= sdram_slave_p0_cas_n; + sdram_master_p0_cs_n <= sdram_slave_p0_cs_n; + sdram_master_p0_ras_n <= sdram_slave_p0_ras_n; + sdram_master_p0_we_n <= sdram_slave_p0_we_n; + sdram_master_p0_cke <= sdram_slave_p0_cke; + sdram_master_p0_odt <= sdram_slave_p0_odt; + sdram_master_p0_reset_n <= sdram_slave_p0_reset_n; + sdram_master_p0_act_n <= sdram_slave_p0_act_n; + sdram_master_p0_wrdata <= sdram_slave_p0_wrdata; + sdram_master_p0_wrdata_en <= sdram_slave_p0_wrdata_en; + sdram_master_p0_wrdata_mask <= sdram_slave_p0_wrdata_mask; + sdram_master_p0_rddata_en <= sdram_slave_p0_rddata_en; + sdram_slave_p0_rddata <= sdram_master_p0_rddata; + sdram_slave_p0_rddata_valid <= sdram_master_p0_rddata_valid; + sdram_master_p1_address <= sdram_slave_p1_address; + sdram_master_p1_bank <= sdram_slave_p1_bank; + sdram_master_p1_cas_n <= sdram_slave_p1_cas_n; + sdram_master_p1_cs_n <= sdram_slave_p1_cs_n; + sdram_master_p1_ras_n <= sdram_slave_p1_ras_n; + sdram_master_p1_we_n <= sdram_slave_p1_we_n; + sdram_master_p1_cke <= sdram_slave_p1_cke; + sdram_master_p1_odt <= sdram_slave_p1_odt; + sdram_master_p1_reset_n <= sdram_slave_p1_reset_n; + sdram_master_p1_act_n <= sdram_slave_p1_act_n; + sdram_master_p1_wrdata <= sdram_slave_p1_wrdata; + sdram_master_p1_wrdata_en <= sdram_slave_p1_wrdata_en; + sdram_master_p1_wrdata_mask <= sdram_slave_p1_wrdata_mask; + sdram_master_p1_rddata_en <= sdram_slave_p1_rddata_en; + sdram_slave_p1_rddata <= sdram_master_p1_rddata; + sdram_slave_p1_rddata_valid <= sdram_master_p1_rddata_valid; + sdram_master_p2_address <= sdram_slave_p2_address; + sdram_master_p2_bank <= sdram_slave_p2_bank; + sdram_master_p2_cas_n <= sdram_slave_p2_cas_n; + sdram_master_p2_cs_n <= sdram_slave_p2_cs_n; + sdram_master_p2_ras_n <= sdram_slave_p2_ras_n; + sdram_master_p2_we_n <= sdram_slave_p2_we_n; + sdram_master_p2_cke <= sdram_slave_p2_cke; + sdram_master_p2_odt <= sdram_slave_p2_odt; + sdram_master_p2_reset_n <= sdram_slave_p2_reset_n; + sdram_master_p2_act_n <= sdram_slave_p2_act_n; + sdram_master_p2_wrdata <= sdram_slave_p2_wrdata; + sdram_master_p2_wrdata_en <= sdram_slave_p2_wrdata_en; + sdram_master_p2_wrdata_mask <= sdram_slave_p2_wrdata_mask; + sdram_master_p2_rddata_en <= sdram_slave_p2_rddata_en; + sdram_slave_p2_rddata <= sdram_master_p2_rddata; + sdram_slave_p2_rddata_valid <= sdram_master_p2_rddata_valid; + sdram_master_p3_address <= sdram_slave_p3_address; + sdram_master_p3_bank <= sdram_slave_p3_bank; + sdram_master_p3_cas_n <= sdram_slave_p3_cas_n; + sdram_master_p3_cs_n <= sdram_slave_p3_cs_n; + sdram_master_p3_ras_n <= sdram_slave_p3_ras_n; + sdram_master_p3_we_n <= sdram_slave_p3_we_n; + sdram_master_p3_cke <= sdram_slave_p3_cke; + sdram_master_p3_odt <= sdram_slave_p3_odt; + sdram_master_p3_reset_n <= sdram_slave_p3_reset_n; + sdram_master_p3_act_n <= sdram_slave_p3_act_n; + sdram_master_p3_wrdata <= sdram_slave_p3_wrdata; + sdram_master_p3_wrdata_en <= sdram_slave_p3_wrdata_en; + sdram_master_p3_wrdata_mask <= sdram_slave_p3_wrdata_mask; + sdram_master_p3_rddata_en <= sdram_slave_p3_rddata_en; + sdram_slave_p3_rddata <= sdram_master_p3_rddata; + sdram_slave_p3_rddata_valid <= sdram_master_p3_rddata_valid; + end else begin + sdram_master_p0_address <= sdram_inti_p0_address; + sdram_master_p0_bank <= sdram_inti_p0_bank; + sdram_master_p0_cas_n <= sdram_inti_p0_cas_n; + sdram_master_p0_cs_n <= sdram_inti_p0_cs_n; + sdram_master_p0_ras_n <= sdram_inti_p0_ras_n; + sdram_master_p0_we_n <= sdram_inti_p0_we_n; + sdram_master_p0_cke <= sdram_inti_p0_cke; + sdram_master_p0_odt <= sdram_inti_p0_odt; + sdram_master_p0_reset_n <= sdram_inti_p0_reset_n; + sdram_master_p0_act_n <= sdram_inti_p0_act_n; + sdram_master_p0_wrdata <= sdram_inti_p0_wrdata; + sdram_master_p0_wrdata_en <= sdram_inti_p0_wrdata_en; + sdram_master_p0_wrdata_mask <= sdram_inti_p0_wrdata_mask; + sdram_master_p0_rddata_en <= sdram_inti_p0_rddata_en; + sdram_inti_p0_rddata <= sdram_master_p0_rddata; + sdram_inti_p0_rddata_valid <= sdram_master_p0_rddata_valid; + sdram_master_p1_address <= sdram_inti_p1_address; + sdram_master_p1_bank <= sdram_inti_p1_bank; + sdram_master_p1_cas_n <= sdram_inti_p1_cas_n; + sdram_master_p1_cs_n <= sdram_inti_p1_cs_n; + sdram_master_p1_ras_n <= sdram_inti_p1_ras_n; + sdram_master_p1_we_n <= sdram_inti_p1_we_n; + sdram_master_p1_cke <= sdram_inti_p1_cke; + sdram_master_p1_odt <= sdram_inti_p1_odt; + sdram_master_p1_reset_n <= sdram_inti_p1_reset_n; + sdram_master_p1_act_n <= sdram_inti_p1_act_n; + sdram_master_p1_wrdata <= sdram_inti_p1_wrdata; + sdram_master_p1_wrdata_en <= sdram_inti_p1_wrdata_en; + sdram_master_p1_wrdata_mask <= sdram_inti_p1_wrdata_mask; + sdram_master_p1_rddata_en <= sdram_inti_p1_rddata_en; + sdram_inti_p1_rddata <= sdram_master_p1_rddata; + sdram_inti_p1_rddata_valid <= sdram_master_p1_rddata_valid; + sdram_master_p2_address <= sdram_inti_p2_address; + sdram_master_p2_bank <= sdram_inti_p2_bank; + sdram_master_p2_cas_n <= sdram_inti_p2_cas_n; + sdram_master_p2_cs_n <= sdram_inti_p2_cs_n; + sdram_master_p2_ras_n <= sdram_inti_p2_ras_n; + sdram_master_p2_we_n <= sdram_inti_p2_we_n; + sdram_master_p2_cke <= sdram_inti_p2_cke; + sdram_master_p2_odt <= sdram_inti_p2_odt; + sdram_master_p2_reset_n <= sdram_inti_p2_reset_n; + sdram_master_p2_act_n <= sdram_inti_p2_act_n; + sdram_master_p2_wrdata <= sdram_inti_p2_wrdata; + sdram_master_p2_wrdata_en <= sdram_inti_p2_wrdata_en; + sdram_master_p2_wrdata_mask <= sdram_inti_p2_wrdata_mask; + sdram_master_p2_rddata_en <= sdram_inti_p2_rddata_en; + sdram_inti_p2_rddata <= sdram_master_p2_rddata; + sdram_inti_p2_rddata_valid <= sdram_master_p2_rddata_valid; + sdram_master_p3_address <= sdram_inti_p3_address; + sdram_master_p3_bank <= sdram_inti_p3_bank; + sdram_master_p3_cas_n <= sdram_inti_p3_cas_n; + sdram_master_p3_cs_n <= sdram_inti_p3_cs_n; + sdram_master_p3_ras_n <= sdram_inti_p3_ras_n; + sdram_master_p3_we_n <= sdram_inti_p3_we_n; + sdram_master_p3_cke <= sdram_inti_p3_cke; + sdram_master_p3_odt <= sdram_inti_p3_odt; + sdram_master_p3_reset_n <= sdram_inti_p3_reset_n; + sdram_master_p3_act_n <= sdram_inti_p3_act_n; + sdram_master_p3_wrdata <= sdram_inti_p3_wrdata; + sdram_master_p3_wrdata_en <= sdram_inti_p3_wrdata_en; + sdram_master_p3_wrdata_mask <= sdram_inti_p3_wrdata_mask; + sdram_master_p3_rddata_en <= sdram_inti_p3_rddata_en; + sdram_inti_p3_rddata <= sdram_master_p3_rddata; + sdram_inti_p3_rddata_valid <= sdram_master_p3_rddata_valid; + end +end +assign sdram_inti_p0_cke = sdram_cke; +assign sdram_inti_p1_cke = sdram_cke; +assign sdram_inti_p2_cke = sdram_cke; +assign sdram_inti_p3_cke = sdram_cke; +assign sdram_inti_p0_odt = sdram_odt; +assign sdram_inti_p1_odt = sdram_odt; +assign sdram_inti_p2_odt = sdram_odt; +assign sdram_inti_p3_odt = sdram_odt; +assign sdram_inti_p0_reset_n = sdram_reset_n; +assign sdram_inti_p1_reset_n = sdram_reset_n; +assign sdram_inti_p2_reset_n = sdram_reset_n; +assign sdram_inti_p3_reset_n = sdram_reset_n; +always @(*) begin + sdram_inti_p0_cas_n <= 1'd1; + sdram_inti_p0_cs_n <= 1'd1; + sdram_inti_p0_ras_n <= 1'd1; + sdram_inti_p0_we_n <= 1'd1; + if (sdram_phaseinjector0_command_issue_re) begin + sdram_inti_p0_cs_n <= {1{(~sdram_phaseinjector0_command_storage[0])}}; + sdram_inti_p0_we_n <= (~sdram_phaseinjector0_command_storage[1]); + sdram_inti_p0_cas_n <= (~sdram_phaseinjector0_command_storage[2]); + sdram_inti_p0_ras_n <= (~sdram_phaseinjector0_command_storage[3]); + end else begin + sdram_inti_p0_cs_n <= {1{1'd1}}; + sdram_inti_p0_we_n <= 1'd1; + sdram_inti_p0_cas_n <= 1'd1; + sdram_inti_p0_ras_n <= 1'd1; + end +end +assign sdram_inti_p0_address = sdram_phaseinjector0_address_storage; +assign sdram_inti_p0_bank = sdram_phaseinjector0_baddress_storage; +assign sdram_inti_p0_wrdata_en = (sdram_phaseinjector0_command_issue_re & sdram_phaseinjector0_command_storage[4]); +assign sdram_inti_p0_rddata_en = (sdram_phaseinjector0_command_issue_re & sdram_phaseinjector0_command_storage[5]); +assign sdram_inti_p0_wrdata = sdram_phaseinjector0_wrdata_storage; +assign sdram_inti_p0_wrdata_mask = 1'd0; +always @(*) begin + sdram_inti_p1_cas_n <= 1'd1; + sdram_inti_p1_cs_n <= 1'd1; + sdram_inti_p1_ras_n <= 1'd1; + sdram_inti_p1_we_n <= 1'd1; + if (sdram_phaseinjector1_command_issue_re) begin + sdram_inti_p1_cs_n <= {1{(~sdram_phaseinjector1_command_storage[0])}}; + sdram_inti_p1_we_n <= (~sdram_phaseinjector1_command_storage[1]); + sdram_inti_p1_cas_n <= (~sdram_phaseinjector1_command_storage[2]); + sdram_inti_p1_ras_n <= (~sdram_phaseinjector1_command_storage[3]); + end else begin + sdram_inti_p1_cs_n <= {1{1'd1}}; + sdram_inti_p1_we_n <= 1'd1; + sdram_inti_p1_cas_n <= 1'd1; + sdram_inti_p1_ras_n <= 1'd1; + end +end +assign sdram_inti_p1_address = sdram_phaseinjector1_address_storage; +assign sdram_inti_p1_bank = sdram_phaseinjector1_baddress_storage; +assign sdram_inti_p1_wrdata_en = (sdram_phaseinjector1_command_issue_re & sdram_phaseinjector1_command_storage[4]); +assign sdram_inti_p1_rddata_en = (sdram_phaseinjector1_command_issue_re & sdram_phaseinjector1_command_storage[5]); +assign sdram_inti_p1_wrdata = sdram_phaseinjector1_wrdata_storage; +assign sdram_inti_p1_wrdata_mask = 1'd0; +always @(*) begin + sdram_inti_p2_cas_n <= 1'd1; + sdram_inti_p2_cs_n <= 1'd1; + sdram_inti_p2_ras_n <= 1'd1; + sdram_inti_p2_we_n <= 1'd1; + if (sdram_phaseinjector2_command_issue_re) begin + sdram_inti_p2_cs_n <= {1{(~sdram_phaseinjector2_command_storage[0])}}; + sdram_inti_p2_we_n <= (~sdram_phaseinjector2_command_storage[1]); + sdram_inti_p2_cas_n <= (~sdram_phaseinjector2_command_storage[2]); + sdram_inti_p2_ras_n <= (~sdram_phaseinjector2_command_storage[3]); + end else begin + sdram_inti_p2_cs_n <= {1{1'd1}}; + sdram_inti_p2_we_n <= 1'd1; + sdram_inti_p2_cas_n <= 1'd1; + sdram_inti_p2_ras_n <= 1'd1; + end +end +assign sdram_inti_p2_address = sdram_phaseinjector2_address_storage; +assign sdram_inti_p2_bank = sdram_phaseinjector2_baddress_storage; +assign sdram_inti_p2_wrdata_en = (sdram_phaseinjector2_command_issue_re & sdram_phaseinjector2_command_storage[4]); +assign sdram_inti_p2_rddata_en = (sdram_phaseinjector2_command_issue_re & sdram_phaseinjector2_command_storage[5]); +assign sdram_inti_p2_wrdata = sdram_phaseinjector2_wrdata_storage; +assign sdram_inti_p2_wrdata_mask = 1'd0; +always @(*) begin + sdram_inti_p3_cas_n <= 1'd1; + sdram_inti_p3_cs_n <= 1'd1; + sdram_inti_p3_ras_n <= 1'd1; + sdram_inti_p3_we_n <= 1'd1; + if (sdram_phaseinjector3_command_issue_re) begin + sdram_inti_p3_cs_n <= {1{(~sdram_phaseinjector3_command_storage[0])}}; + sdram_inti_p3_we_n <= (~sdram_phaseinjector3_command_storage[1]); + sdram_inti_p3_cas_n <= (~sdram_phaseinjector3_command_storage[2]); + sdram_inti_p3_ras_n <= (~sdram_phaseinjector3_command_storage[3]); + end else begin + sdram_inti_p3_cs_n <= {1{1'd1}}; + sdram_inti_p3_we_n <= 1'd1; + sdram_inti_p3_cas_n <= 1'd1; + sdram_inti_p3_ras_n <= 1'd1; + end +end +assign sdram_inti_p3_address = sdram_phaseinjector3_address_storage; +assign sdram_inti_p3_bank = sdram_phaseinjector3_baddress_storage; +assign sdram_inti_p3_wrdata_en = (sdram_phaseinjector3_command_issue_re & sdram_phaseinjector3_command_storage[4]); +assign sdram_inti_p3_rddata_en = (sdram_phaseinjector3_command_issue_re & sdram_phaseinjector3_command_storage[5]); +assign sdram_inti_p3_wrdata = sdram_phaseinjector3_wrdata_storage; +assign sdram_inti_p3_wrdata_mask = 1'd0; +assign sdram_bankmachine0_req_valid = sdram_interface_bank0_valid; +assign sdram_interface_bank0_ready = sdram_bankmachine0_req_ready; +assign sdram_bankmachine0_req_we = sdram_interface_bank0_we; +assign sdram_bankmachine0_req_addr = sdram_interface_bank0_addr; +assign sdram_interface_bank0_lock = sdram_bankmachine0_req_lock; +assign sdram_interface_bank0_wdata_ready = sdram_bankmachine0_req_wdata_ready; +assign sdram_interface_bank0_rdata_valid = sdram_bankmachine0_req_rdata_valid; +assign sdram_bankmachine1_req_valid = sdram_interface_bank1_valid; +assign sdram_interface_bank1_ready = sdram_bankmachine1_req_ready; +assign sdram_bankmachine1_req_we = sdram_interface_bank1_we; +assign sdram_bankmachine1_req_addr = sdram_interface_bank1_addr; +assign sdram_interface_bank1_lock = sdram_bankmachine1_req_lock; +assign sdram_interface_bank1_wdata_ready = sdram_bankmachine1_req_wdata_ready; +assign sdram_interface_bank1_rdata_valid = sdram_bankmachine1_req_rdata_valid; +assign sdram_bankmachine2_req_valid = sdram_interface_bank2_valid; +assign sdram_interface_bank2_ready = sdram_bankmachine2_req_ready; +assign sdram_bankmachine2_req_we = sdram_interface_bank2_we; +assign sdram_bankmachine2_req_addr = sdram_interface_bank2_addr; +assign sdram_interface_bank2_lock = sdram_bankmachine2_req_lock; +assign sdram_interface_bank2_wdata_ready = sdram_bankmachine2_req_wdata_ready; +assign sdram_interface_bank2_rdata_valid = sdram_bankmachine2_req_rdata_valid; +assign sdram_bankmachine3_req_valid = sdram_interface_bank3_valid; +assign sdram_interface_bank3_ready = sdram_bankmachine3_req_ready; +assign sdram_bankmachine3_req_we = sdram_interface_bank3_we; +assign sdram_bankmachine3_req_addr = sdram_interface_bank3_addr; +assign sdram_interface_bank3_lock = sdram_bankmachine3_req_lock; +assign sdram_interface_bank3_wdata_ready = sdram_bankmachine3_req_wdata_ready; +assign sdram_interface_bank3_rdata_valid = sdram_bankmachine3_req_rdata_valid; +assign sdram_bankmachine4_req_valid = sdram_interface_bank4_valid; +assign sdram_interface_bank4_ready = sdram_bankmachine4_req_ready; +assign sdram_bankmachine4_req_we = sdram_interface_bank4_we; +assign sdram_bankmachine4_req_addr = sdram_interface_bank4_addr; +assign sdram_interface_bank4_lock = sdram_bankmachine4_req_lock; +assign sdram_interface_bank4_wdata_ready = sdram_bankmachine4_req_wdata_ready; +assign sdram_interface_bank4_rdata_valid = sdram_bankmachine4_req_rdata_valid; +assign sdram_bankmachine5_req_valid = sdram_interface_bank5_valid; +assign sdram_interface_bank5_ready = sdram_bankmachine5_req_ready; +assign sdram_bankmachine5_req_we = sdram_interface_bank5_we; +assign sdram_bankmachine5_req_addr = sdram_interface_bank5_addr; +assign sdram_interface_bank5_lock = sdram_bankmachine5_req_lock; +assign sdram_interface_bank5_wdata_ready = sdram_bankmachine5_req_wdata_ready; +assign sdram_interface_bank5_rdata_valid = sdram_bankmachine5_req_rdata_valid; +assign sdram_bankmachine6_req_valid = sdram_interface_bank6_valid; +assign sdram_interface_bank6_ready = sdram_bankmachine6_req_ready; +assign sdram_bankmachine6_req_we = sdram_interface_bank6_we; +assign sdram_bankmachine6_req_addr = sdram_interface_bank6_addr; +assign sdram_interface_bank6_lock = sdram_bankmachine6_req_lock; +assign sdram_interface_bank6_wdata_ready = sdram_bankmachine6_req_wdata_ready; +assign sdram_interface_bank6_rdata_valid = sdram_bankmachine6_req_rdata_valid; +assign sdram_bankmachine7_req_valid = sdram_interface_bank7_valid; +assign sdram_interface_bank7_ready = sdram_bankmachine7_req_ready; +assign sdram_bankmachine7_req_we = sdram_interface_bank7_we; +assign sdram_bankmachine7_req_addr = sdram_interface_bank7_addr; +assign sdram_interface_bank7_lock = sdram_bankmachine7_req_lock; +assign sdram_interface_bank7_wdata_ready = sdram_bankmachine7_req_wdata_ready; +assign sdram_interface_bank7_rdata_valid = sdram_bankmachine7_req_rdata_valid; +assign sdram_timer_wait = (~sdram_timer_done0); +assign sdram_postponer_req_i = sdram_timer_done0; +assign sdram_wants_refresh = sdram_postponer_req_o; +assign sdram_wants_zqcs = sdram_zqcs_timer_done0; +assign sdram_zqcs_timer_wait = (~sdram_zqcs_executer_done); +assign sdram_timer_done1 = (sdram_timer_count1 == 1'd0); +assign sdram_timer_done0 = sdram_timer_done1; +assign sdram_timer_count0 = sdram_timer_count1; +assign sdram_sequencer_start1 = (sdram_sequencer_start0 | (sdram_sequencer_count != 1'd0)); +assign sdram_sequencer_done0 = (sdram_sequencer_done1 & (sdram_sequencer_count == 1'd0)); +assign sdram_zqcs_timer_done1 = (sdram_zqcs_timer_count1 == 1'd0); +assign sdram_zqcs_timer_done0 = sdram_zqcs_timer_done1; +assign sdram_zqcs_timer_count0 = sdram_zqcs_timer_count1; +always @(*) begin + sdram_sequencer_start0 <= 1'd0; + sdram_cmd_valid <= 1'd0; + subfragments_refresher_next_state <= 2'd0; + sdram_zqcs_executer_start <= 1'd0; + sdram_cmd_last <= 1'd0; + subfragments_refresher_next_state <= subfragments_refresher_state; + case (subfragments_refresher_state) + 1'd1: begin + sdram_cmd_valid <= 1'd1; + if (sdram_cmd_ready) begin + sdram_sequencer_start0 <= 1'd1; + subfragments_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + sdram_cmd_valid <= 1'd1; + if (sdram_sequencer_done0) begin + if (sdram_wants_zqcs) begin + sdram_zqcs_executer_start <= 1'd1; + subfragments_refresher_next_state <= 2'd3; + end else begin + sdram_cmd_valid <= 1'd0; + sdram_cmd_last <= 1'd1; + subfragments_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + sdram_cmd_valid <= 1'd1; + if (sdram_zqcs_executer_done) begin + sdram_cmd_valid <= 1'd0; + sdram_cmd_last <= 1'd1; + subfragments_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (sdram_wants_refresh) begin + subfragments_refresher_next_state <= 1'd1; + end + end + end + endcase +end +assign sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = sdram_bankmachine0_req_valid; +assign sdram_bankmachine0_req_ready = sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine0_req_we; +assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine0_req_addr; +assign sdram_bankmachine0_cmd_buffer_sink_valid = sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_ready = sdram_bankmachine0_cmd_buffer_sink_ready; +assign sdram_bankmachine0_cmd_buffer_sink_first = sdram_bankmachine0_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine0_cmd_buffer_sink_last = sdram_bankmachine0_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine0_cmd_buffer_sink_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine0_cmd_buffer_sink_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine0_cmd_buffer_source_ready = (sdram_bankmachine0_req_wdata_ready | sdram_bankmachine0_req_rdata_valid); +assign sdram_bankmachine0_req_lock = (sdram_bankmachine0_cmd_buffer_lookahead_source_valid | sdram_bankmachine0_cmd_buffer_source_valid); +assign sdram_bankmachine0_row_hit = (sdram_bankmachine0_row == sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]); +assign sdram_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + sdram_bankmachine0_cmd_payload_a <= 14'd0; + if (sdram_bankmachine0_row_col_n_addr_sel) begin + sdram_bankmachine0_cmd_payload_a <= sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end else begin + sdram_bankmachine0_cmd_payload_a <= ((sdram_bankmachine0_auto_precharge <<< 4'd10) | {sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign sdram_bankmachine0_twtpcon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_cmd_payload_is_write); +assign sdram_bankmachine0_trccon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open); +assign sdram_bankmachine0_trascon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open); +always @(*) begin + sdram_bankmachine0_auto_precharge <= 1'd0; + if ((sdram_bankmachine0_cmd_buffer_lookahead_source_valid & sdram_bankmachine0_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin + sdram_bankmachine0_auto_precharge <= (sdram_bankmachine0_row_close == 1'd0); + end + end +end +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine0_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine0_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_valid = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_first = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_last = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine0_cmd_buffer_lookahead_replace) begin + sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine0_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | sdram_bankmachine0_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine0_cmd_buffer_lookahead_do_read = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine0_cmd_buffer_lookahead_consume; +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine0_cmd_buffer_sink_ready = ((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine0_row_open <= 1'd0; + sdram_bankmachine0_row_close <= 1'd0; + sdram_bankmachine0_cmd_payload_cas <= 1'd0; + sdram_bankmachine0_req_rdata_valid <= 1'd0; + sdram_bankmachine0_cmd_payload_ras <= 1'd0; + sdram_bankmachine0_cmd_payload_we <= 1'd0; + sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine0_cmd_payload_is_read <= 1'd0; + sdram_bankmachine0_cmd_payload_is_write <= 1'd0; + sdram_bankmachine0_req_wdata_ready <= 1'd0; + subfragments_bankmachine0_next_state <= 3'd0; + sdram_bankmachine0_refresh_gnt <= 1'd0; + sdram_bankmachine0_cmd_valid <= 1'd0; + subfragments_bankmachine0_next_state <= subfragments_bankmachine0_state; + case (subfragments_bankmachine0_state) + 1'd1: begin + if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin + sdram_bankmachine0_cmd_valid <= 1'd1; + if (sdram_bankmachine0_cmd_ready) begin + subfragments_bankmachine0_next_state <= 3'd5; + end + sdram_bankmachine0_cmd_payload_ras <= 1'd1; + sdram_bankmachine0_cmd_payload_we <= 1'd1; + sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin + subfragments_bankmachine0_next_state <= 3'd5; + end + sdram_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine0_trccon_ready) begin + sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine0_row_open <= 1'd1; + sdram_bankmachine0_cmd_valid <= 1'd1; + sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine0_cmd_ready) begin + subfragments_bankmachine0_next_state <= 3'd6; + end + sdram_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine0_twtpcon_ready) begin + sdram_bankmachine0_refresh_gnt <= 1'd1; + end + sdram_bankmachine0_row_close <= 1'd1; + sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine0_refresh_req)) begin + subfragments_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine0_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine0_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine0_refresh_req) begin + subfragments_bankmachine0_next_state <= 3'd4; + end else begin + if (sdram_bankmachine0_cmd_buffer_source_valid) begin + if (sdram_bankmachine0_row_opened) begin + if (sdram_bankmachine0_row_hit) begin + sdram_bankmachine0_cmd_valid <= 1'd1; + if (sdram_bankmachine0_cmd_buffer_source_payload_we) begin + sdram_bankmachine0_req_wdata_ready <= sdram_bankmachine0_cmd_ready; + sdram_bankmachine0_cmd_payload_is_write <= 1'd1; + sdram_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine0_req_rdata_valid <= sdram_bankmachine0_cmd_ready; + sdram_bankmachine0_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine0_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine0_cmd_ready & sdram_bankmachine0_auto_precharge)) begin + subfragments_bankmachine0_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine0_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = sdram_bankmachine1_req_valid; +assign sdram_bankmachine1_req_ready = sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine1_req_we; +assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine1_req_addr; +assign sdram_bankmachine1_cmd_buffer_sink_valid = sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_ready = sdram_bankmachine1_cmd_buffer_sink_ready; +assign sdram_bankmachine1_cmd_buffer_sink_first = sdram_bankmachine1_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine1_cmd_buffer_sink_last = sdram_bankmachine1_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine1_cmd_buffer_sink_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine1_cmd_buffer_sink_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine1_cmd_buffer_source_ready = (sdram_bankmachine1_req_wdata_ready | sdram_bankmachine1_req_rdata_valid); +assign sdram_bankmachine1_req_lock = (sdram_bankmachine1_cmd_buffer_lookahead_source_valid | sdram_bankmachine1_cmd_buffer_source_valid); +assign sdram_bankmachine1_row_hit = (sdram_bankmachine1_row == sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]); +assign sdram_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + sdram_bankmachine1_cmd_payload_a <= 14'd0; + if (sdram_bankmachine1_row_col_n_addr_sel) begin + sdram_bankmachine1_cmd_payload_a <= sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end else begin + sdram_bankmachine1_cmd_payload_a <= ((sdram_bankmachine1_auto_precharge <<< 4'd10) | {sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign sdram_bankmachine1_twtpcon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_cmd_payload_is_write); +assign sdram_bankmachine1_trccon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open); +assign sdram_bankmachine1_trascon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open); +always @(*) begin + sdram_bankmachine1_auto_precharge <= 1'd0; + if ((sdram_bankmachine1_cmd_buffer_lookahead_source_valid & sdram_bankmachine1_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin + sdram_bankmachine1_auto_precharge <= (sdram_bankmachine1_row_close == 1'd0); + end + end +end +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine1_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine1_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_valid = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_first = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_last = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine1_cmd_buffer_lookahead_replace) begin + sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine1_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | sdram_bankmachine1_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine1_cmd_buffer_lookahead_do_read = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine1_cmd_buffer_lookahead_consume; +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine1_cmd_buffer_sink_ready = ((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine1_row_open <= 1'd0; + sdram_bankmachine1_row_close <= 1'd0; + sdram_bankmachine1_cmd_payload_cas <= 1'd0; + sdram_bankmachine1_cmd_payload_ras <= 1'd0; + sdram_bankmachine1_cmd_payload_we <= 1'd0; + sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine1_cmd_payload_is_read <= 1'd0; + sdram_bankmachine1_cmd_payload_is_write <= 1'd0; + subfragments_bankmachine1_next_state <= 3'd0; + sdram_bankmachine1_req_wdata_ready <= 1'd0; + sdram_bankmachine1_req_rdata_valid <= 1'd0; + sdram_bankmachine1_refresh_gnt <= 1'd0; + sdram_bankmachine1_cmd_valid <= 1'd0; + subfragments_bankmachine1_next_state <= subfragments_bankmachine1_state; + case (subfragments_bankmachine1_state) + 1'd1: begin + if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin + sdram_bankmachine1_cmd_valid <= 1'd1; + if (sdram_bankmachine1_cmd_ready) begin + subfragments_bankmachine1_next_state <= 3'd5; + end + sdram_bankmachine1_cmd_payload_ras <= 1'd1; + sdram_bankmachine1_cmd_payload_we <= 1'd1; + sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin + subfragments_bankmachine1_next_state <= 3'd5; + end + sdram_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine1_trccon_ready) begin + sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine1_row_open <= 1'd1; + sdram_bankmachine1_cmd_valid <= 1'd1; + sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine1_cmd_ready) begin + subfragments_bankmachine1_next_state <= 3'd6; + end + sdram_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine1_twtpcon_ready) begin + sdram_bankmachine1_refresh_gnt <= 1'd1; + end + sdram_bankmachine1_row_close <= 1'd1; + sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine1_refresh_req)) begin + subfragments_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine1_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine1_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine1_refresh_req) begin + subfragments_bankmachine1_next_state <= 3'd4; + end else begin + if (sdram_bankmachine1_cmd_buffer_source_valid) begin + if (sdram_bankmachine1_row_opened) begin + if (sdram_bankmachine1_row_hit) begin + sdram_bankmachine1_cmd_valid <= 1'd1; + if (sdram_bankmachine1_cmd_buffer_source_payload_we) begin + sdram_bankmachine1_req_wdata_ready <= sdram_bankmachine1_cmd_ready; + sdram_bankmachine1_cmd_payload_is_write <= 1'd1; + sdram_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine1_req_rdata_valid <= sdram_bankmachine1_cmd_ready; + sdram_bankmachine1_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine1_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine1_cmd_ready & sdram_bankmachine1_auto_precharge)) begin + subfragments_bankmachine1_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine1_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = sdram_bankmachine2_req_valid; +assign sdram_bankmachine2_req_ready = sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine2_req_we; +assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine2_req_addr; +assign sdram_bankmachine2_cmd_buffer_sink_valid = sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_ready = sdram_bankmachine2_cmd_buffer_sink_ready; +assign sdram_bankmachine2_cmd_buffer_sink_first = sdram_bankmachine2_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine2_cmd_buffer_sink_last = sdram_bankmachine2_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine2_cmd_buffer_sink_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine2_cmd_buffer_sink_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine2_cmd_buffer_source_ready = (sdram_bankmachine2_req_wdata_ready | sdram_bankmachine2_req_rdata_valid); +assign sdram_bankmachine2_req_lock = (sdram_bankmachine2_cmd_buffer_lookahead_source_valid | sdram_bankmachine2_cmd_buffer_source_valid); +assign sdram_bankmachine2_row_hit = (sdram_bankmachine2_row == sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]); +assign sdram_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + sdram_bankmachine2_cmd_payload_a <= 14'd0; + if (sdram_bankmachine2_row_col_n_addr_sel) begin + sdram_bankmachine2_cmd_payload_a <= sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end else begin + sdram_bankmachine2_cmd_payload_a <= ((sdram_bankmachine2_auto_precharge <<< 4'd10) | {sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign sdram_bankmachine2_twtpcon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_cmd_payload_is_write); +assign sdram_bankmachine2_trccon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open); +assign sdram_bankmachine2_trascon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open); +always @(*) begin + sdram_bankmachine2_auto_precharge <= 1'd0; + if ((sdram_bankmachine2_cmd_buffer_lookahead_source_valid & sdram_bankmachine2_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin + sdram_bankmachine2_auto_precharge <= (sdram_bankmachine2_row_close == 1'd0); + end + end +end +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine2_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine2_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_valid = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_first = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_last = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine2_cmd_buffer_lookahead_replace) begin + sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine2_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | sdram_bankmachine2_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine2_cmd_buffer_lookahead_do_read = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine2_cmd_buffer_lookahead_consume; +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine2_cmd_buffer_sink_ready = ((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine2_row_open <= 1'd0; + sdram_bankmachine2_row_close <= 1'd0; + sdram_bankmachine2_cmd_payload_cas <= 1'd0; + sdram_bankmachine2_cmd_payload_ras <= 1'd0; + sdram_bankmachine2_cmd_payload_we <= 1'd0; + sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; + subfragments_bankmachine2_next_state <= 3'd0; + sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine2_cmd_payload_is_read <= 1'd0; + sdram_bankmachine2_cmd_payload_is_write <= 1'd0; + sdram_bankmachine2_req_wdata_ready <= 1'd0; + sdram_bankmachine2_req_rdata_valid <= 1'd0; + sdram_bankmachine2_refresh_gnt <= 1'd0; + sdram_bankmachine2_cmd_valid <= 1'd0; + subfragments_bankmachine2_next_state <= subfragments_bankmachine2_state; + case (subfragments_bankmachine2_state) + 1'd1: begin + if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin + sdram_bankmachine2_cmd_valid <= 1'd1; + if (sdram_bankmachine2_cmd_ready) begin + subfragments_bankmachine2_next_state <= 3'd5; + end + sdram_bankmachine2_cmd_payload_ras <= 1'd1; + sdram_bankmachine2_cmd_payload_we <= 1'd1; + sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin + subfragments_bankmachine2_next_state <= 3'd5; + end + sdram_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine2_trccon_ready) begin + sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine2_row_open <= 1'd1; + sdram_bankmachine2_cmd_valid <= 1'd1; + sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine2_cmd_ready) begin + subfragments_bankmachine2_next_state <= 3'd6; + end + sdram_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine2_twtpcon_ready) begin + sdram_bankmachine2_refresh_gnt <= 1'd1; + end + sdram_bankmachine2_row_close <= 1'd1; + sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine2_refresh_req)) begin + subfragments_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine2_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine2_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine2_refresh_req) begin + subfragments_bankmachine2_next_state <= 3'd4; + end else begin + if (sdram_bankmachine2_cmd_buffer_source_valid) begin + if (sdram_bankmachine2_row_opened) begin + if (sdram_bankmachine2_row_hit) begin + sdram_bankmachine2_cmd_valid <= 1'd1; + if (sdram_bankmachine2_cmd_buffer_source_payload_we) begin + sdram_bankmachine2_req_wdata_ready <= sdram_bankmachine2_cmd_ready; + sdram_bankmachine2_cmd_payload_is_write <= 1'd1; + sdram_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine2_req_rdata_valid <= sdram_bankmachine2_cmd_ready; + sdram_bankmachine2_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine2_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine2_cmd_ready & sdram_bankmachine2_auto_precharge)) begin + subfragments_bankmachine2_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine2_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = sdram_bankmachine3_req_valid; +assign sdram_bankmachine3_req_ready = sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine3_req_we; +assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine3_req_addr; +assign sdram_bankmachine3_cmd_buffer_sink_valid = sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_ready = sdram_bankmachine3_cmd_buffer_sink_ready; +assign sdram_bankmachine3_cmd_buffer_sink_first = sdram_bankmachine3_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine3_cmd_buffer_sink_last = sdram_bankmachine3_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine3_cmd_buffer_sink_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine3_cmd_buffer_sink_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine3_cmd_buffer_source_ready = (sdram_bankmachine3_req_wdata_ready | sdram_bankmachine3_req_rdata_valid); +assign sdram_bankmachine3_req_lock = (sdram_bankmachine3_cmd_buffer_lookahead_source_valid | sdram_bankmachine3_cmd_buffer_source_valid); +assign sdram_bankmachine3_row_hit = (sdram_bankmachine3_row == sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]); +assign sdram_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + sdram_bankmachine3_cmd_payload_a <= 14'd0; + if (sdram_bankmachine3_row_col_n_addr_sel) begin + sdram_bankmachine3_cmd_payload_a <= sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end else begin + sdram_bankmachine3_cmd_payload_a <= ((sdram_bankmachine3_auto_precharge <<< 4'd10) | {sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign sdram_bankmachine3_twtpcon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_cmd_payload_is_write); +assign sdram_bankmachine3_trccon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open); +assign sdram_bankmachine3_trascon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open); +always @(*) begin + sdram_bankmachine3_auto_precharge <= 1'd0; + if ((sdram_bankmachine3_cmd_buffer_lookahead_source_valid & sdram_bankmachine3_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin + sdram_bankmachine3_auto_precharge <= (sdram_bankmachine3_row_close == 1'd0); + end + end +end +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine3_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine3_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_valid = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_first = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_last = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine3_cmd_buffer_lookahead_replace) begin + sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine3_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | sdram_bankmachine3_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine3_cmd_buffer_lookahead_do_read = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine3_cmd_buffer_lookahead_consume; +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine3_row_open <= 1'd0; + sdram_bankmachine3_row_close <= 1'd0; + sdram_bankmachine3_cmd_payload_cas <= 1'd0; + subfragments_bankmachine3_next_state <= 3'd0; + sdram_bankmachine3_cmd_payload_ras <= 1'd0; + sdram_bankmachine3_cmd_payload_we <= 1'd0; + sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine3_cmd_payload_is_read <= 1'd0; + sdram_bankmachine3_cmd_payload_is_write <= 1'd0; + sdram_bankmachine3_req_wdata_ready <= 1'd0; + sdram_bankmachine3_req_rdata_valid <= 1'd0; + sdram_bankmachine3_refresh_gnt <= 1'd0; + sdram_bankmachine3_cmd_valid <= 1'd0; + subfragments_bankmachine3_next_state <= subfragments_bankmachine3_state; + case (subfragments_bankmachine3_state) + 1'd1: begin + if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin + sdram_bankmachine3_cmd_valid <= 1'd1; + if (sdram_bankmachine3_cmd_ready) begin + subfragments_bankmachine3_next_state <= 3'd5; + end + sdram_bankmachine3_cmd_payload_ras <= 1'd1; + sdram_bankmachine3_cmd_payload_we <= 1'd1; + sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin + subfragments_bankmachine3_next_state <= 3'd5; + end + sdram_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine3_trccon_ready) begin + sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine3_row_open <= 1'd1; + sdram_bankmachine3_cmd_valid <= 1'd1; + sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine3_cmd_ready) begin + subfragments_bankmachine3_next_state <= 3'd6; + end + sdram_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine3_twtpcon_ready) begin + sdram_bankmachine3_refresh_gnt <= 1'd1; + end + sdram_bankmachine3_row_close <= 1'd1; + sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine3_refresh_req)) begin + subfragments_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine3_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine3_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine3_refresh_req) begin + subfragments_bankmachine3_next_state <= 3'd4; + end else begin + if (sdram_bankmachine3_cmd_buffer_source_valid) begin + if (sdram_bankmachine3_row_opened) begin + if (sdram_bankmachine3_row_hit) begin + sdram_bankmachine3_cmd_valid <= 1'd1; + if (sdram_bankmachine3_cmd_buffer_source_payload_we) begin + sdram_bankmachine3_req_wdata_ready <= sdram_bankmachine3_cmd_ready; + sdram_bankmachine3_cmd_payload_is_write <= 1'd1; + sdram_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine3_req_rdata_valid <= sdram_bankmachine3_cmd_ready; + sdram_bankmachine3_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine3_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine3_cmd_ready & sdram_bankmachine3_auto_precharge)) begin + subfragments_bankmachine3_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine3_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = sdram_bankmachine4_req_valid; +assign sdram_bankmachine4_req_ready = sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine4_req_we; +assign sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine4_req_addr; +assign sdram_bankmachine4_cmd_buffer_sink_valid = sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine4_cmd_buffer_lookahead_source_ready = sdram_bankmachine4_cmd_buffer_sink_ready; +assign sdram_bankmachine4_cmd_buffer_sink_first = sdram_bankmachine4_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine4_cmd_buffer_sink_last = sdram_bankmachine4_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine4_cmd_buffer_sink_payload_we = sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine4_cmd_buffer_sink_payload_addr = sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine4_cmd_buffer_source_ready = (sdram_bankmachine4_req_wdata_ready | sdram_bankmachine4_req_rdata_valid); +assign sdram_bankmachine4_req_lock = (sdram_bankmachine4_cmd_buffer_lookahead_source_valid | sdram_bankmachine4_cmd_buffer_source_valid); +assign sdram_bankmachine4_row_hit = (sdram_bankmachine4_row == sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]); +assign sdram_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + sdram_bankmachine4_cmd_payload_a <= 14'd0; + if (sdram_bankmachine4_row_col_n_addr_sel) begin + sdram_bankmachine4_cmd_payload_a <= sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end else begin + sdram_bankmachine4_cmd_payload_a <= ((sdram_bankmachine4_auto_precharge <<< 4'd10) | {sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign sdram_bankmachine4_twtpcon_valid = ((sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_ready) & sdram_bankmachine4_cmd_payload_is_write); +assign sdram_bankmachine4_trccon_valid = ((sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_ready) & sdram_bankmachine4_row_open); +assign sdram_bankmachine4_trascon_valid = ((sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_ready) & sdram_bankmachine4_row_open); +always @(*) begin + sdram_bankmachine4_auto_precharge <= 1'd0; + if ((sdram_bankmachine4_cmd_buffer_lookahead_source_valid & sdram_bankmachine4_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin + sdram_bankmachine4_auto_precharge <= (sdram_bankmachine4_row_close == 1'd0); + end + end +end +assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine4_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine4_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine4_cmd_buffer_lookahead_source_valid = sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign sdram_bankmachine4_cmd_buffer_lookahead_source_first = sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine4_cmd_buffer_lookahead_source_last = sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = sdram_bankmachine4_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine4_cmd_buffer_lookahead_replace) begin + sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine4_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | sdram_bankmachine4_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine4_cmd_buffer_lookahead_do_read = (sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine4_cmd_buffer_lookahead_consume; +assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (sdram_bankmachine4_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine4_cmd_buffer_sink_ready = ((~sdram_bankmachine4_cmd_buffer_source_valid) | sdram_bankmachine4_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine4_row_open <= 1'd0; + sdram_bankmachine4_row_close <= 1'd0; + subfragments_bankmachine4_next_state <= 3'd0; + sdram_bankmachine4_cmd_payload_cas <= 1'd0; + sdram_bankmachine4_cmd_payload_ras <= 1'd0; + sdram_bankmachine4_cmd_payload_we <= 1'd0; + sdram_bankmachine4_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine4_cmd_payload_is_read <= 1'd0; + sdram_bankmachine4_cmd_payload_is_write <= 1'd0; + sdram_bankmachine4_req_wdata_ready <= 1'd0; + sdram_bankmachine4_req_rdata_valid <= 1'd0; + sdram_bankmachine4_refresh_gnt <= 1'd0; + sdram_bankmachine4_cmd_valid <= 1'd0; + subfragments_bankmachine4_next_state <= subfragments_bankmachine4_state; + case (subfragments_bankmachine4_state) + 1'd1: begin + if ((sdram_bankmachine4_twtpcon_ready & sdram_bankmachine4_trascon_ready)) begin + sdram_bankmachine4_cmd_valid <= 1'd1; + if (sdram_bankmachine4_cmd_ready) begin + subfragments_bankmachine4_next_state <= 3'd5; + end + sdram_bankmachine4_cmd_payload_ras <= 1'd1; + sdram_bankmachine4_cmd_payload_we <= 1'd1; + sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine4_twtpcon_ready & sdram_bankmachine4_trascon_ready)) begin + subfragments_bankmachine4_next_state <= 3'd5; + end + sdram_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine4_trccon_ready) begin + sdram_bankmachine4_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine4_row_open <= 1'd1; + sdram_bankmachine4_cmd_valid <= 1'd1; + sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine4_cmd_ready) begin + subfragments_bankmachine4_next_state <= 3'd6; + end + sdram_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine4_twtpcon_ready) begin + sdram_bankmachine4_refresh_gnt <= 1'd1; + end + sdram_bankmachine4_row_close <= 1'd1; + sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine4_refresh_req)) begin + subfragments_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine4_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine4_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine4_refresh_req) begin + subfragments_bankmachine4_next_state <= 3'd4; + end else begin + if (sdram_bankmachine4_cmd_buffer_source_valid) begin + if (sdram_bankmachine4_row_opened) begin + if (sdram_bankmachine4_row_hit) begin + sdram_bankmachine4_cmd_valid <= 1'd1; + if (sdram_bankmachine4_cmd_buffer_source_payload_we) begin + sdram_bankmachine4_req_wdata_ready <= sdram_bankmachine4_cmd_ready; + sdram_bankmachine4_cmd_payload_is_write <= 1'd1; + sdram_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine4_req_rdata_valid <= sdram_bankmachine4_cmd_ready; + sdram_bankmachine4_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine4_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine4_cmd_ready & sdram_bankmachine4_auto_precharge)) begin + subfragments_bankmachine4_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine4_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = sdram_bankmachine5_req_valid; +assign sdram_bankmachine5_req_ready = sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine5_req_we; +assign sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine5_req_addr; +assign sdram_bankmachine5_cmd_buffer_sink_valid = sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine5_cmd_buffer_lookahead_source_ready = sdram_bankmachine5_cmd_buffer_sink_ready; +assign sdram_bankmachine5_cmd_buffer_sink_first = sdram_bankmachine5_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine5_cmd_buffer_sink_last = sdram_bankmachine5_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine5_cmd_buffer_sink_payload_we = sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine5_cmd_buffer_sink_payload_addr = sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine5_cmd_buffer_source_ready = (sdram_bankmachine5_req_wdata_ready | sdram_bankmachine5_req_rdata_valid); +assign sdram_bankmachine5_req_lock = (sdram_bankmachine5_cmd_buffer_lookahead_source_valid | sdram_bankmachine5_cmd_buffer_source_valid); +assign sdram_bankmachine5_row_hit = (sdram_bankmachine5_row == sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]); +assign sdram_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + sdram_bankmachine5_cmd_payload_a <= 14'd0; + if (sdram_bankmachine5_row_col_n_addr_sel) begin + sdram_bankmachine5_cmd_payload_a <= sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end else begin + sdram_bankmachine5_cmd_payload_a <= ((sdram_bankmachine5_auto_precharge <<< 4'd10) | {sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign sdram_bankmachine5_twtpcon_valid = ((sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_ready) & sdram_bankmachine5_cmd_payload_is_write); +assign sdram_bankmachine5_trccon_valid = ((sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_ready) & sdram_bankmachine5_row_open); +assign sdram_bankmachine5_trascon_valid = ((sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_ready) & sdram_bankmachine5_row_open); +always @(*) begin + sdram_bankmachine5_auto_precharge <= 1'd0; + if ((sdram_bankmachine5_cmd_buffer_lookahead_source_valid & sdram_bankmachine5_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin + sdram_bankmachine5_auto_precharge <= (sdram_bankmachine5_row_close == 1'd0); + end + end +end +assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine5_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine5_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine5_cmd_buffer_lookahead_source_valid = sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign sdram_bankmachine5_cmd_buffer_lookahead_source_first = sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine5_cmd_buffer_lookahead_source_last = sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = sdram_bankmachine5_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine5_cmd_buffer_lookahead_replace) begin + sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine5_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | sdram_bankmachine5_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine5_cmd_buffer_lookahead_do_read = (sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine5_cmd_buffer_lookahead_consume; +assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (sdram_bankmachine5_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine5_cmd_buffer_sink_ready = ((~sdram_bankmachine5_cmd_buffer_source_valid) | sdram_bankmachine5_cmd_buffer_source_ready); +always @(*) begin + subfragments_bankmachine5_next_state <= 3'd0; + sdram_bankmachine5_row_open <= 1'd0; + sdram_bankmachine5_row_close <= 1'd0; + sdram_bankmachine5_cmd_payload_cas <= 1'd0; + sdram_bankmachine5_cmd_payload_ras <= 1'd0; + sdram_bankmachine5_cmd_payload_we <= 1'd0; + sdram_bankmachine5_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine5_cmd_payload_is_read <= 1'd0; + sdram_bankmachine5_cmd_payload_is_write <= 1'd0; + sdram_bankmachine5_req_wdata_ready <= 1'd0; + sdram_bankmachine5_req_rdata_valid <= 1'd0; + sdram_bankmachine5_refresh_gnt <= 1'd0; + sdram_bankmachine5_cmd_valid <= 1'd0; + subfragments_bankmachine5_next_state <= subfragments_bankmachine5_state; + case (subfragments_bankmachine5_state) + 1'd1: begin + if ((sdram_bankmachine5_twtpcon_ready & sdram_bankmachine5_trascon_ready)) begin + sdram_bankmachine5_cmd_valid <= 1'd1; + if (sdram_bankmachine5_cmd_ready) begin + subfragments_bankmachine5_next_state <= 3'd5; + end + sdram_bankmachine5_cmd_payload_ras <= 1'd1; + sdram_bankmachine5_cmd_payload_we <= 1'd1; + sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine5_twtpcon_ready & sdram_bankmachine5_trascon_ready)) begin + subfragments_bankmachine5_next_state <= 3'd5; + end + sdram_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine5_trccon_ready) begin + sdram_bankmachine5_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine5_row_open <= 1'd1; + sdram_bankmachine5_cmd_valid <= 1'd1; + sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine5_cmd_ready) begin + subfragments_bankmachine5_next_state <= 3'd6; + end + sdram_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine5_twtpcon_ready) begin + sdram_bankmachine5_refresh_gnt <= 1'd1; + end + sdram_bankmachine5_row_close <= 1'd1; + sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine5_refresh_req)) begin + subfragments_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine5_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine5_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine5_refresh_req) begin + subfragments_bankmachine5_next_state <= 3'd4; + end else begin + if (sdram_bankmachine5_cmd_buffer_source_valid) begin + if (sdram_bankmachine5_row_opened) begin + if (sdram_bankmachine5_row_hit) begin + sdram_bankmachine5_cmd_valid <= 1'd1; + if (sdram_bankmachine5_cmd_buffer_source_payload_we) begin + sdram_bankmachine5_req_wdata_ready <= sdram_bankmachine5_cmd_ready; + sdram_bankmachine5_cmd_payload_is_write <= 1'd1; + sdram_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine5_req_rdata_valid <= sdram_bankmachine5_cmd_ready; + sdram_bankmachine5_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine5_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine5_cmd_ready & sdram_bankmachine5_auto_precharge)) begin + subfragments_bankmachine5_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine5_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = sdram_bankmachine6_req_valid; +assign sdram_bankmachine6_req_ready = sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine6_req_we; +assign sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine6_req_addr; +assign sdram_bankmachine6_cmd_buffer_sink_valid = sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine6_cmd_buffer_lookahead_source_ready = sdram_bankmachine6_cmd_buffer_sink_ready; +assign sdram_bankmachine6_cmd_buffer_sink_first = sdram_bankmachine6_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine6_cmd_buffer_sink_last = sdram_bankmachine6_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine6_cmd_buffer_sink_payload_we = sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine6_cmd_buffer_sink_payload_addr = sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine6_cmd_buffer_source_ready = (sdram_bankmachine6_req_wdata_ready | sdram_bankmachine6_req_rdata_valid); +assign sdram_bankmachine6_req_lock = (sdram_bankmachine6_cmd_buffer_lookahead_source_valid | sdram_bankmachine6_cmd_buffer_source_valid); +assign sdram_bankmachine6_row_hit = (sdram_bankmachine6_row == sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]); +assign sdram_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + sdram_bankmachine6_cmd_payload_a <= 14'd0; + if (sdram_bankmachine6_row_col_n_addr_sel) begin + sdram_bankmachine6_cmd_payload_a <= sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end else begin + sdram_bankmachine6_cmd_payload_a <= ((sdram_bankmachine6_auto_precharge <<< 4'd10) | {sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign sdram_bankmachine6_twtpcon_valid = ((sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_ready) & sdram_bankmachine6_cmd_payload_is_write); +assign sdram_bankmachine6_trccon_valid = ((sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_ready) & sdram_bankmachine6_row_open); +assign sdram_bankmachine6_trascon_valid = ((sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_ready) & sdram_bankmachine6_row_open); +always @(*) begin + sdram_bankmachine6_auto_precharge <= 1'd0; + if ((sdram_bankmachine6_cmd_buffer_lookahead_source_valid & sdram_bankmachine6_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin + sdram_bankmachine6_auto_precharge <= (sdram_bankmachine6_row_close == 1'd0); + end + end +end +assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine6_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine6_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine6_cmd_buffer_lookahead_source_valid = sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign sdram_bankmachine6_cmd_buffer_lookahead_source_first = sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine6_cmd_buffer_lookahead_source_last = sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = sdram_bankmachine6_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine6_cmd_buffer_lookahead_replace) begin + sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine6_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | sdram_bankmachine6_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine6_cmd_buffer_lookahead_do_read = (sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine6_cmd_buffer_lookahead_consume; +assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (sdram_bankmachine6_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine6_cmd_buffer_sink_ready = ((~sdram_bankmachine6_cmd_buffer_source_valid) | sdram_bankmachine6_cmd_buffer_source_ready); +always @(*) begin + subfragments_bankmachine6_next_state <= 3'd0; + sdram_bankmachine6_row_open <= 1'd0; + sdram_bankmachine6_row_close <= 1'd0; + sdram_bankmachine6_cmd_payload_cas <= 1'd0; + sdram_bankmachine6_cmd_payload_ras <= 1'd0; + sdram_bankmachine6_cmd_payload_we <= 1'd0; + sdram_bankmachine6_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine6_cmd_payload_is_read <= 1'd0; + sdram_bankmachine6_cmd_payload_is_write <= 1'd0; + sdram_bankmachine6_req_wdata_ready <= 1'd0; + sdram_bankmachine6_req_rdata_valid <= 1'd0; + sdram_bankmachine6_refresh_gnt <= 1'd0; + sdram_bankmachine6_cmd_valid <= 1'd0; + subfragments_bankmachine6_next_state <= subfragments_bankmachine6_state; + case (subfragments_bankmachine6_state) + 1'd1: begin + if ((sdram_bankmachine6_twtpcon_ready & sdram_bankmachine6_trascon_ready)) begin + sdram_bankmachine6_cmd_valid <= 1'd1; + if (sdram_bankmachine6_cmd_ready) begin + subfragments_bankmachine6_next_state <= 3'd5; + end + sdram_bankmachine6_cmd_payload_ras <= 1'd1; + sdram_bankmachine6_cmd_payload_we <= 1'd1; + sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine6_twtpcon_ready & sdram_bankmachine6_trascon_ready)) begin + subfragments_bankmachine6_next_state <= 3'd5; + end + sdram_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine6_trccon_ready) begin + sdram_bankmachine6_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine6_row_open <= 1'd1; + sdram_bankmachine6_cmd_valid <= 1'd1; + sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine6_cmd_ready) begin + subfragments_bankmachine6_next_state <= 3'd6; + end + sdram_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine6_twtpcon_ready) begin + sdram_bankmachine6_refresh_gnt <= 1'd1; + end + sdram_bankmachine6_row_close <= 1'd1; + sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine6_refresh_req)) begin + subfragments_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine6_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine6_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine6_refresh_req) begin + subfragments_bankmachine6_next_state <= 3'd4; + end else begin + if (sdram_bankmachine6_cmd_buffer_source_valid) begin + if (sdram_bankmachine6_row_opened) begin + if (sdram_bankmachine6_row_hit) begin + sdram_bankmachine6_cmd_valid <= 1'd1; + if (sdram_bankmachine6_cmd_buffer_source_payload_we) begin + sdram_bankmachine6_req_wdata_ready <= sdram_bankmachine6_cmd_ready; + sdram_bankmachine6_cmd_payload_is_write <= 1'd1; + sdram_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine6_req_rdata_valid <= sdram_bankmachine6_cmd_ready; + sdram_bankmachine6_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine6_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine6_cmd_ready & sdram_bankmachine6_auto_precharge)) begin + subfragments_bankmachine6_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine6_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = sdram_bankmachine7_req_valid; +assign sdram_bankmachine7_req_ready = sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine7_req_we; +assign sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine7_req_addr; +assign sdram_bankmachine7_cmd_buffer_sink_valid = sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine7_cmd_buffer_lookahead_source_ready = sdram_bankmachine7_cmd_buffer_sink_ready; +assign sdram_bankmachine7_cmd_buffer_sink_first = sdram_bankmachine7_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine7_cmd_buffer_sink_last = sdram_bankmachine7_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine7_cmd_buffer_sink_payload_we = sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine7_cmd_buffer_sink_payload_addr = sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine7_cmd_buffer_source_ready = (sdram_bankmachine7_req_wdata_ready | sdram_bankmachine7_req_rdata_valid); +assign sdram_bankmachine7_req_lock = (sdram_bankmachine7_cmd_buffer_lookahead_source_valid | sdram_bankmachine7_cmd_buffer_source_valid); +assign sdram_bankmachine7_row_hit = (sdram_bankmachine7_row == sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]); +assign sdram_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + sdram_bankmachine7_cmd_payload_a <= 14'd0; + if (sdram_bankmachine7_row_col_n_addr_sel) begin + sdram_bankmachine7_cmd_payload_a <= sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end else begin + sdram_bankmachine7_cmd_payload_a <= ((sdram_bankmachine7_auto_precharge <<< 4'd10) | {sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign sdram_bankmachine7_twtpcon_valid = ((sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_ready) & sdram_bankmachine7_cmd_payload_is_write); +assign sdram_bankmachine7_trccon_valid = ((sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_ready) & sdram_bankmachine7_row_open); +assign sdram_bankmachine7_trascon_valid = ((sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_ready) & sdram_bankmachine7_row_open); +always @(*) begin + sdram_bankmachine7_auto_precharge <= 1'd0; + if ((sdram_bankmachine7_cmd_buffer_lookahead_source_valid & sdram_bankmachine7_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin + sdram_bankmachine7_auto_precharge <= (sdram_bankmachine7_row_close == 1'd0); + end + end +end +assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine7_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine7_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine7_cmd_buffer_lookahead_source_valid = sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign sdram_bankmachine7_cmd_buffer_lookahead_source_first = sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine7_cmd_buffer_lookahead_source_last = sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = sdram_bankmachine7_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine7_cmd_buffer_lookahead_replace) begin + sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine7_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | sdram_bankmachine7_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine7_cmd_buffer_lookahead_do_read = (sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine7_cmd_buffer_lookahead_consume; +assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (sdram_bankmachine7_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine7_cmd_buffer_sink_ready = ((~sdram_bankmachine7_cmd_buffer_source_valid) | sdram_bankmachine7_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine7_row_open <= 1'd0; + sdram_bankmachine7_row_close <= 1'd0; + sdram_bankmachine7_cmd_payload_cas <= 1'd0; + sdram_bankmachine7_cmd_payload_ras <= 1'd0; + sdram_bankmachine7_cmd_payload_we <= 1'd0; + sdram_bankmachine7_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine7_cmd_payload_is_read <= 1'd0; + sdram_bankmachine7_cmd_payload_is_write <= 1'd0; + sdram_bankmachine7_req_wdata_ready <= 1'd0; + sdram_bankmachine7_refresh_gnt <= 1'd0; + sdram_bankmachine7_req_rdata_valid <= 1'd0; + subfragments_bankmachine7_next_state <= 3'd0; + sdram_bankmachine7_cmd_valid <= 1'd0; + subfragments_bankmachine7_next_state <= subfragments_bankmachine7_state; + case (subfragments_bankmachine7_state) + 1'd1: begin + if ((sdram_bankmachine7_twtpcon_ready & sdram_bankmachine7_trascon_ready)) begin + sdram_bankmachine7_cmd_valid <= 1'd1; + if (sdram_bankmachine7_cmd_ready) begin + subfragments_bankmachine7_next_state <= 3'd5; + end + sdram_bankmachine7_cmd_payload_ras <= 1'd1; + sdram_bankmachine7_cmd_payload_we <= 1'd1; + sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine7_twtpcon_ready & sdram_bankmachine7_trascon_ready)) begin + subfragments_bankmachine7_next_state <= 3'd5; + end + sdram_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine7_trccon_ready) begin + sdram_bankmachine7_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine7_row_open <= 1'd1; + sdram_bankmachine7_cmd_valid <= 1'd1; + sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine7_cmd_ready) begin + subfragments_bankmachine7_next_state <= 3'd6; + end + sdram_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine7_twtpcon_ready) begin + sdram_bankmachine7_refresh_gnt <= 1'd1; + end + sdram_bankmachine7_row_close <= 1'd1; + sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine7_refresh_req)) begin + subfragments_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine7_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine7_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine7_refresh_req) begin + subfragments_bankmachine7_next_state <= 3'd4; + end else begin + if (sdram_bankmachine7_cmd_buffer_source_valid) begin + if (sdram_bankmachine7_row_opened) begin + if (sdram_bankmachine7_row_hit) begin + sdram_bankmachine7_cmd_valid <= 1'd1; + if (sdram_bankmachine7_cmd_buffer_source_payload_we) begin + sdram_bankmachine7_req_wdata_ready <= sdram_bankmachine7_cmd_ready; + sdram_bankmachine7_cmd_payload_is_write <= 1'd1; + sdram_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine7_req_rdata_valid <= sdram_bankmachine7_cmd_ready; + sdram_bankmachine7_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine7_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine7_cmd_ready & sdram_bankmachine7_auto_precharge)) begin + subfragments_bankmachine7_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine7_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); +assign sdram_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); +assign sdram_trrdcon_valid = ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & ((sdram_choose_cmd_cmd_payload_ras & (~sdram_choose_cmd_cmd_payload_cas)) & (~sdram_choose_cmd_cmd_payload_we))); +assign sdram_tfawcon_valid = ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & ((sdram_choose_cmd_cmd_payload_ras & (~sdram_choose_cmd_cmd_payload_cas)) & (~sdram_choose_cmd_cmd_payload_we))); +assign sdram_ras_allowed = (sdram_trrdcon_ready & sdram_tfawcon_ready); +assign sdram_tccdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_cmd_payload_is_write | sdram_choose_req_cmd_payload_is_read)); +assign sdram_cas_allowed = sdram_tccdcon_ready; +assign sdram_twtrcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); +assign sdram_read_available = ((((((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_read) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_read)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_read)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_read)) | (sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_payload_is_read)) | (sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_payload_is_read)) | (sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_payload_is_read)) | (sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_payload_is_read)); +assign sdram_write_available = ((((((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_write) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_write)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_write)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_write)) | (sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_payload_is_write)) | (sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_payload_is_write)) | (sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_payload_is_write)) | (sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_payload_is_write)); +assign sdram_max_time0 = (sdram_time0 == 1'd0); +assign sdram_max_time1 = (sdram_time1 == 1'd0); +assign sdram_bankmachine0_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine1_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine2_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine3_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine4_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine5_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine6_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine7_refresh_req = sdram_cmd_valid; +assign sdram_go_to_refresh = (((((((sdram_bankmachine0_refresh_gnt & sdram_bankmachine1_refresh_gnt) & sdram_bankmachine2_refresh_gnt) & sdram_bankmachine3_refresh_gnt) & sdram_bankmachine4_refresh_gnt) & sdram_bankmachine5_refresh_gnt) & sdram_bankmachine6_refresh_gnt) & sdram_bankmachine7_refresh_gnt); +assign sdram_interface_rdata = {sdram_dfi_p3_rddata, sdram_dfi_p2_rddata, sdram_dfi_p1_rddata, sdram_dfi_p0_rddata}; +assign {sdram_dfi_p3_wrdata, sdram_dfi_p2_wrdata, sdram_dfi_p1_wrdata, sdram_dfi_p0_wrdata} = sdram_interface_wdata; +assign {sdram_dfi_p3_wrdata_mask, sdram_dfi_p2_wrdata_mask, sdram_dfi_p1_wrdata_mask, sdram_dfi_p0_wrdata_mask} = (~sdram_interface_wdata_we); +always @(*) begin + sdram_choose_cmd_valids <= 8'd0; + sdram_choose_cmd_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[4] <= (sdram_bankmachine4_cmd_valid & (((sdram_bankmachine4_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine4_cmd_payload_ras & (~sdram_bankmachine4_cmd_payload_cas)) & (~sdram_bankmachine4_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine4_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine4_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[5] <= (sdram_bankmachine5_cmd_valid & (((sdram_bankmachine5_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine5_cmd_payload_ras & (~sdram_bankmachine5_cmd_payload_cas)) & (~sdram_bankmachine5_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine5_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine5_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[6] <= (sdram_bankmachine6_cmd_valid & (((sdram_bankmachine6_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine6_cmd_payload_ras & (~sdram_bankmachine6_cmd_payload_cas)) & (~sdram_bankmachine6_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine6_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine6_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[7] <= (sdram_bankmachine7_cmd_valid & (((sdram_bankmachine7_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine7_cmd_payload_ras & (~sdram_bankmachine7_cmd_payload_cas)) & (~sdram_bankmachine7_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine7_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine7_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); +end +assign sdram_choose_cmd_request = sdram_choose_cmd_valids; +assign sdram_choose_cmd_cmd_valid = rhs_array_muxed0; +assign sdram_choose_cmd_cmd_payload_a = rhs_array_muxed1; +assign sdram_choose_cmd_cmd_payload_ba = rhs_array_muxed2; +assign sdram_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; +assign sdram_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; +assign sdram_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +always @(*) begin + sdram_choose_cmd_cmd_payload_cas <= 1'd0; + if (sdram_choose_cmd_cmd_valid) begin + sdram_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end +end +always @(*) begin + sdram_choose_cmd_cmd_payload_ras <= 1'd0; + if (sdram_choose_cmd_cmd_valid) begin + sdram_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end +end +always @(*) begin + sdram_choose_cmd_cmd_payload_we <= 1'd0; + if (sdram_choose_cmd_cmd_valid) begin + sdram_choose_cmd_cmd_payload_we <= t_array_muxed2; + end +end +assign sdram_choose_cmd_ce = (sdram_choose_cmd_cmd_ready | (~sdram_choose_cmd_cmd_valid)); +always @(*) begin + sdram_choose_req_valids <= 8'd0; + sdram_choose_req_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[4] <= (sdram_bankmachine4_cmd_valid & (((sdram_bankmachine4_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine4_cmd_payload_ras & (~sdram_bankmachine4_cmd_payload_cas)) & (~sdram_bankmachine4_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine4_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine4_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[5] <= (sdram_bankmachine5_cmd_valid & (((sdram_bankmachine5_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine5_cmd_payload_ras & (~sdram_bankmachine5_cmd_payload_cas)) & (~sdram_bankmachine5_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine5_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine5_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[6] <= (sdram_bankmachine6_cmd_valid & (((sdram_bankmachine6_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine6_cmd_payload_ras & (~sdram_bankmachine6_cmd_payload_cas)) & (~sdram_bankmachine6_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine6_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine6_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[7] <= (sdram_bankmachine7_cmd_valid & (((sdram_bankmachine7_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine7_cmd_payload_ras & (~sdram_bankmachine7_cmd_payload_cas)) & (~sdram_bankmachine7_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine7_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine7_cmd_payload_is_write == sdram_choose_req_want_writes)))); +end +assign sdram_choose_req_request = sdram_choose_req_valids; +assign sdram_choose_req_cmd_valid = rhs_array_muxed6; +assign sdram_choose_req_cmd_payload_a = rhs_array_muxed7; +assign sdram_choose_req_cmd_payload_ba = rhs_array_muxed8; +assign sdram_choose_req_cmd_payload_is_read = rhs_array_muxed9; +assign sdram_choose_req_cmd_payload_is_write = rhs_array_muxed10; +assign sdram_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +always @(*) begin + sdram_choose_req_cmd_payload_cas <= 1'd0; + if (sdram_choose_req_cmd_valid) begin + sdram_choose_req_cmd_payload_cas <= t_array_muxed3; + end +end +always @(*) begin + sdram_choose_req_cmd_payload_ras <= 1'd0; + if (sdram_choose_req_cmd_valid) begin + sdram_choose_req_cmd_payload_ras <= t_array_muxed4; + end +end +always @(*) begin + sdram_choose_req_cmd_payload_we <= 1'd0; + if (sdram_choose_req_cmd_valid) begin + sdram_choose_req_cmd_payload_we <= t_array_muxed5; + end +end +always @(*) begin + sdram_bankmachine0_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd0))) begin + sdram_bankmachine0_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd0))) begin + sdram_bankmachine0_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine1_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd1))) begin + sdram_bankmachine1_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd1))) begin + sdram_bankmachine1_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine2_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd2))) begin + sdram_bankmachine2_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd2))) begin + sdram_bankmachine2_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine3_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd3))) begin + sdram_bankmachine3_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd3))) begin + sdram_bankmachine3_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine4_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 3'd4))) begin + sdram_bankmachine4_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 3'd4))) begin + sdram_bankmachine4_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine5_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 3'd5))) begin + sdram_bankmachine5_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 3'd5))) begin + sdram_bankmachine5_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine6_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 3'd6))) begin + sdram_bankmachine6_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 3'd6))) begin + sdram_bankmachine6_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine7_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 3'd7))) begin + sdram_bankmachine7_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 3'd7))) begin + sdram_bankmachine7_cmd_ready <= 1'd1; + end +end +assign sdram_choose_req_ce = (sdram_choose_req_cmd_ready | (~sdram_choose_req_cmd_valid)); +assign sdram_dfi_p0_reset_n = 1'd1; +assign sdram_dfi_p0_cke = {1{sdram_steerer0}}; +assign sdram_dfi_p0_odt = {1{sdram_steerer1}}; +assign sdram_dfi_p1_reset_n = 1'd1; +assign sdram_dfi_p1_cke = {1{sdram_steerer2}}; +assign sdram_dfi_p1_odt = {1{sdram_steerer3}}; +assign sdram_dfi_p2_reset_n = 1'd1; +assign sdram_dfi_p2_cke = {1{sdram_steerer4}}; +assign sdram_dfi_p2_odt = {1{sdram_steerer5}}; +assign sdram_dfi_p3_reset_n = 1'd1; +assign sdram_dfi_p3_cke = {1{sdram_steerer6}}; +assign sdram_dfi_p3_odt = {1{sdram_steerer7}}; +assign sdram_tfawcon_count = (((sdram_tfawcon_window[0] + sdram_tfawcon_window[1]) + sdram_tfawcon_window[2]) + sdram_tfawcon_window[3]); +always @(*) begin + sdram_choose_cmd_cmd_ready <= 1'd0; + sdram_choose_req_want_reads <= 1'd0; + sdram_choose_req_want_writes <= 1'd0; + sdram_steerer_sel3 <= 2'd0; + sdram_en1 <= 1'd0; + sdram_choose_req_cmd_ready <= 1'd0; + sdram_en0 <= 1'd0; + subfragments_multiplexer_next_state <= 4'd0; + sdram_steerer_sel0 <= 2'd0; + sdram_cmd_ready <= 1'd0; + sdram_steerer_sel1 <= 2'd0; + sdram_steerer_sel2 <= 2'd0; + sdram_choose_cmd_want_activates <= 1'd0; + subfragments_multiplexer_next_state <= subfragments_multiplexer_state; + case (subfragments_multiplexer_state) + 1'd1: begin + sdram_en1 <= 1'd1; + sdram_choose_req_want_writes <= 1'd1; + if (1'd0) begin + sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed)); + end else begin + sdram_choose_cmd_want_activates <= sdram_ras_allowed; + sdram_choose_cmd_cmd_ready <= ((~((sdram_choose_cmd_cmd_payload_ras & (~sdram_choose_cmd_cmd_payload_cas)) & (~sdram_choose_cmd_cmd_payload_we))) | sdram_ras_allowed); + sdram_choose_req_cmd_ready <= sdram_cas_allowed; + end + sdram_steerer_sel0 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd0)) begin + sdram_steerer_sel0 <= 2'd2; + end + if ((sdram_wrcmdphase == 1'd0)) begin + sdram_steerer_sel0 <= 1'd1; + end + sdram_steerer_sel1 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd1)) begin + sdram_steerer_sel1 <= 2'd2; + end + if ((sdram_wrcmdphase == 1'd1)) begin + sdram_steerer_sel1 <= 1'd1; + end + sdram_steerer_sel2 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd2)) begin + sdram_steerer_sel2 <= 2'd2; + end + if ((sdram_wrcmdphase == 2'd2)) begin + sdram_steerer_sel2 <= 1'd1; + end + sdram_steerer_sel3 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd3)) begin + sdram_steerer_sel3 <= 2'd2; + end + if ((sdram_wrcmdphase == 2'd3)) begin + sdram_steerer_sel3 <= 1'd1; + end + if (sdram_read_available) begin + if (((~sdram_write_available) | sdram_max_time1)) begin + subfragments_multiplexer_next_state <= 2'd3; + end + end + if (sdram_go_to_refresh) begin + subfragments_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + sdram_steerer_sel0 <= 2'd3; + sdram_cmd_ready <= 1'd1; + if (sdram_cmd_last) begin + subfragments_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (sdram_twtrcon_ready) begin + subfragments_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + subfragments_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + subfragments_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + subfragments_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + subfragments_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + subfragments_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + subfragments_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + subfragments_multiplexer_next_state <= 1'd1; + end + default: begin + sdram_en0 <= 1'd1; + sdram_choose_req_want_reads <= 1'd1; + if (1'd0) begin + sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed)); + end else begin + sdram_choose_cmd_want_activates <= sdram_ras_allowed; + sdram_choose_cmd_cmd_ready <= ((~((sdram_choose_cmd_cmd_payload_ras & (~sdram_choose_cmd_cmd_payload_cas)) & (~sdram_choose_cmd_cmd_payload_we))) | sdram_ras_allowed); + sdram_choose_req_cmd_ready <= sdram_cas_allowed; + end + sdram_steerer_sel0 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd0)) begin + sdram_steerer_sel0 <= 2'd2; + end + if ((sdram_rdcmdphase == 1'd0)) begin + sdram_steerer_sel0 <= 1'd1; + end + sdram_steerer_sel1 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd1)) begin + sdram_steerer_sel1 <= 2'd2; + end + if ((sdram_rdcmdphase == 1'd1)) begin + sdram_steerer_sel1 <= 1'd1; + end + sdram_steerer_sel2 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd2)) begin + sdram_steerer_sel2 <= 2'd2; + end + if ((sdram_rdcmdphase == 2'd2)) begin + sdram_steerer_sel2 <= 1'd1; + end + sdram_steerer_sel3 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd3)) begin + sdram_steerer_sel3 <= 2'd2; + end + if ((sdram_rdcmdphase == 2'd3)) begin + sdram_steerer_sel3 <= 1'd1; + end + if (sdram_write_available) begin + if (((~sdram_read_available) | sdram_max_time0)) begin + subfragments_multiplexer_next_state <= 3'd4; + end + end + if (sdram_go_to_refresh) begin + subfragments_multiplexer_next_state <= 2'd2; + end + end + endcase +end +assign subfragments_roundrobin0_request = {(((port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin0_ce = ((~sdram_interface_bank0_valid) & (~sdram_interface_bank0_lock)); +assign sdram_interface_bank0_addr = rhs_array_muxed12; +assign sdram_interface_bank0_we = rhs_array_muxed13; +assign sdram_interface_bank0_valid = rhs_array_muxed14; +assign subfragments_roundrobin1_request = {(((port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin1_ce = ((~sdram_interface_bank1_valid) & (~sdram_interface_bank1_lock)); +assign sdram_interface_bank1_addr = rhs_array_muxed15; +assign sdram_interface_bank1_we = rhs_array_muxed16; +assign sdram_interface_bank1_valid = rhs_array_muxed17; +assign subfragments_roundrobin2_request = {(((port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin2_ce = ((~sdram_interface_bank2_valid) & (~sdram_interface_bank2_lock)); +assign sdram_interface_bank2_addr = rhs_array_muxed18; +assign sdram_interface_bank2_we = rhs_array_muxed19; +assign sdram_interface_bank2_valid = rhs_array_muxed20; +assign subfragments_roundrobin3_request = {(((port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin3_ce = ((~sdram_interface_bank3_valid) & (~sdram_interface_bank3_lock)); +assign sdram_interface_bank3_addr = rhs_array_muxed21; +assign sdram_interface_bank3_we = rhs_array_muxed22; +assign sdram_interface_bank3_valid = rhs_array_muxed23; +assign subfragments_roundrobin4_request = {(((port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((subfragments_locked4 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin4_ce = ((~sdram_interface_bank4_valid) & (~sdram_interface_bank4_lock)); +assign sdram_interface_bank4_addr = rhs_array_muxed24; +assign sdram_interface_bank4_we = rhs_array_muxed25; +assign sdram_interface_bank4_valid = rhs_array_muxed26; +assign subfragments_roundrobin5_request = {(((port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((subfragments_locked5 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin5_ce = ((~sdram_interface_bank5_valid) & (~sdram_interface_bank5_lock)); +assign sdram_interface_bank5_addr = rhs_array_muxed27; +assign sdram_interface_bank5_we = rhs_array_muxed28; +assign sdram_interface_bank5_valid = rhs_array_muxed29; +assign subfragments_roundrobin6_request = {(((port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((subfragments_locked6 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin6_ce = ((~sdram_interface_bank6_valid) & (~sdram_interface_bank6_lock)); +assign sdram_interface_bank6_addr = rhs_array_muxed30; +assign sdram_interface_bank6_we = rhs_array_muxed31; +assign sdram_interface_bank6_valid = rhs_array_muxed32; +assign subfragments_roundrobin7_request = {(((port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((subfragments_locked7 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin7_ce = ((~sdram_interface_bank7_valid) & (~sdram_interface_bank7_lock)); +assign sdram_interface_bank7_addr = rhs_array_muxed33; +assign sdram_interface_bank7_we = rhs_array_muxed34; +assign sdram_interface_bank7_valid = rhs_array_muxed35; +assign port_cmd_ready = ((((((((1'd0 | (((subfragments_roundrobin0_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank0_ready)) | (((subfragments_roundrobin1_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank1_ready)) | (((subfragments_roundrobin2_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank2_ready)) | (((subfragments_roundrobin3_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank3_ready)) | (((subfragments_roundrobin4_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((subfragments_locked4 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank4_ready)) | (((subfragments_roundrobin5_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((subfragments_locked5 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank5_ready)) | (((subfragments_roundrobin6_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((subfragments_locked6 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank6_ready)) | (((subfragments_roundrobin7_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((subfragments_locked7 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0)))))) & sdram_interface_bank7_ready)); +assign port_wdata_ready = subfragments_new_master_wdata_ready1; +assign port_rdata_valid = subfragments_new_master_rdata_valid8; +always @(*) begin + sdram_interface_wdata <= 128'd0; + sdram_interface_wdata_we <= 16'd0; + case ({subfragments_new_master_wdata_ready1}) + 1'd1: begin + sdram_interface_wdata <= port_wdata_payload_data; + sdram_interface_wdata_we <= port_wdata_payload_we; + end + default: begin + sdram_interface_wdata <= 1'd0; + sdram_interface_wdata_we <= 1'd0; + end + endcase +end +assign port_rdata_payload_data = sdram_interface_rdata; +assign subfragments_roundrobin0_grant = 1'd0; +assign subfragments_roundrobin1_grant = 1'd0; +assign subfragments_roundrobin2_grant = 1'd0; +assign subfragments_roundrobin3_grant = 1'd0; +assign subfragments_roundrobin4_grant = 1'd0; +assign subfragments_roundrobin5_grant = 1'd0; +assign subfragments_roundrobin6_grant = 1'd0; +assign subfragments_roundrobin7_grant = 1'd0; +assign data_port_adr = wb_sdram_adr[10:2]; +always @(*) begin + data_port_we <= 16'd0; + data_port_dat_w <= 128'd0; + if (write_from_slave) begin + data_port_dat_w <= interface_dat_r; + data_port_we <= {16{1'd1}}; + end else begin + data_port_dat_w <= {4{wb_sdram_dat_w}}; + if ((((wb_sdram_cyc & wb_sdram_stb) & wb_sdram_we) & wb_sdram_ack)) begin + data_port_we <= {({4{(wb_sdram_adr[1:0] == 1'd0)}} & wb_sdram_sel), ({4{(wb_sdram_adr[1:0] == 1'd1)}} & wb_sdram_sel), ({4{(wb_sdram_adr[1:0] == 2'd2)}} & wb_sdram_sel), ({4{(wb_sdram_adr[1:0] == 2'd3)}} & wb_sdram_sel)}; + end + end +end +assign interface_dat_w = data_port_dat_r; +assign interface_sel = 16'd65535; +always @(*) begin + wb_sdram_dat_r <= 32'd0; + case (adr_offset_r) + 1'd0: begin + wb_sdram_dat_r <= data_port_dat_r[127:96]; + end + 1'd1: begin + wb_sdram_dat_r <= data_port_dat_r[95:64]; + end + 2'd2: begin + wb_sdram_dat_r <= data_port_dat_r[63:32]; + end + default: begin + wb_sdram_dat_r <= data_port_dat_r[31:0]; + end + endcase +end +assign {tag_do_dirty, tag_do_tag} = tag_port_dat_r; +assign tag_port_dat_w = {tag_di_dirty, tag_di_tag}; +assign tag_port_adr = wb_sdram_adr[10:2]; +assign tag_di_tag = wb_sdram_adr[29:11]; +assign interface_adr = {tag_do_tag, wb_sdram_adr[10:2]}; +always @(*) begin + write_from_slave <= 1'd0; + subfragments_fullmemorywe_next_state <= 2'd0; + interface_cyc <= 1'd0; + interface_stb <= 1'd0; + tag_port_we <= 1'd0; + interface_we <= 1'd0; + wb_sdram_ack <= 1'd0; + tag_di_dirty <= 1'd0; + word_clr <= 1'd0; + word_inc <= 1'd0; + subfragments_fullmemorywe_next_state <= subfragments_fullmemorywe_state; + case (subfragments_fullmemorywe_state) + 1'd1: begin + word_clr <= 1'd1; + if ((tag_do_tag == wb_sdram_adr[29:11])) begin + wb_sdram_ack <= 1'd1; + if (wb_sdram_we) begin + tag_di_dirty <= 1'd1; + tag_port_we <= 1'd1; + end + subfragments_fullmemorywe_next_state <= 1'd0; + end else begin + if (tag_do_dirty) begin + subfragments_fullmemorywe_next_state <= 2'd2; + end else begin + tag_port_we <= 1'd1; + word_clr <= 1'd1; + subfragments_fullmemorywe_next_state <= 2'd3; + end + end + end + 2'd2: begin + interface_stb <= 1'd1; + interface_cyc <= 1'd1; + interface_we <= 1'd1; + if (interface_ack) begin + word_inc <= 1'd1; + if (1'd1) begin + tag_port_we <= 1'd1; + word_clr <= 1'd1; + subfragments_fullmemorywe_next_state <= 2'd3; + end + end + end + 2'd3: begin + interface_stb <= 1'd1; + interface_cyc <= 1'd1; + interface_we <= 1'd0; + if (interface_ack) begin + write_from_slave <= 1'd1; + word_inc <= 1'd1; + if (1'd1) begin + subfragments_fullmemorywe_next_state <= 1'd1; + end else begin + subfragments_fullmemorywe_next_state <= 2'd3; + end + end + end + default: begin + if ((wb_sdram_cyc & wb_sdram_stb)) begin + subfragments_fullmemorywe_next_state <= 1'd1; + end + end + endcase +end +assign port_cmd_payload_addr = (interface_adr - 27'd67108864); +assign port_cmd_payload_we = interface_we; +assign port_wdata_payload_data = interface_dat_w; +assign port_wdata_payload_we = interface_sel; +assign interface_dat_r = port_rdata_payload_data; +assign port_flush = (~interface_cyc); +assign port_cmd_last = (~interface_we); +assign port_cmd_valid = ((interface_cyc & interface_stb) & (~cmd_consumed)); +assign port_wdata_valid = (((port_cmd_valid | cmd_consumed) & port_cmd_payload_we) & (~wdata_consumed)); +assign port_rdata_ready = ((port_cmd_valid | cmd_consumed) & (~port_cmd_payload_we)); +assign interface_ack = (ack_cmd & ((interface_we & ack_wdata) | ((~interface_we) & ack_rdata))); +assign ack_cmd = ((port_cmd_valid & port_cmd_ready) | cmd_consumed); +assign ack_wdata = ((port_wdata_valid & port_wdata_ready) | wdata_consumed); +assign ack_rdata = (port_rdata_valid & port_rdata_ready); +assign ctrl_rx_idle = datapath_rx_idle; +assign ctrl_misalign = datapath_misalign; +assign a7litesataphy_tx_init_restart = (~enable); +assign a7litesataphy_rx_init_restart = ((~enable) | ctrl_rx_reset); +assign ready = (a7litesataphy_ready & ctrl_ready); +assign enable = litesataphy_enable_storage; +assign litesataphy_ready = (a7litesataphy_ready & ctrl_ready); +assign litesataphy_tx_ready = a7litesataphy_tx_init_done; +assign litesataphy_rx_ready = a7litesataphy_rx_init_done; +assign litesataphy_ctrl_ready = ctrl_ready; +assign a7litesataphy_tx_init_plllock0 = a7litesataphy_qplllock; +assign a7litesataphy_rx_init_plllock0 = a7litesataphy_qplllock; +assign a7litesataphy_ready = (a7litesataphy_tx_init_done & a7litesataphy_rx_init_done); +assign a7litesataphy_txelecidle0 = (a7litesataphy_tx_idle | a7litesataphy_txpd0); +assign a7litesataphy_tx_cominit_ack = (a7litesataphy_tx_cominit_stb & a7litesataphy_txcomfinish0); +assign a7litesataphy_tx_comwake_ack = (a7litesataphy_tx_comwake_stb & a7litesataphy_txcomfinish0); +assign a7litesataphy_rx_cominit_stb = a7litesataphy_rxcominitdet0; +assign a7litesataphy_rx_comwake_stb = a7litesataphy_rxcomwakedet0; +assign a7litesataphy_qplllock = a7litesataphy_qpll_lock; +assign a7litesataphy_qpll_reset = a7litesataphy_tx_init_pllreset; +assign a7litesataphy_tx_init_txphaligndone_rising = (a7litesataphy_tx_init_txphaligndone1 & (~a7litesataphy_tx_init_txphaligndone_r)); +assign a7litesataphy_tx_init_init_delay_wait = 1'd1; +assign a7litesataphy_tx_init_watchdog_wait = ((~a7litesataphy_tx_init_reset) & (~a7litesataphy_tx_init_done)); +assign a7litesataphy_tx_init_reset = (a7litesataphy_tx_init_restart | a7litesataphy_tx_init_watchdog_done); +always @(*) begin + a7litesataphy_tx_init_txdlysreset1 <= 1'd0; + a7litesataphy_tx_init_txphinit1 <= 1'd0; + a7litesataphy_tx_init_txphalign1 <= 1'd0; + a7litesataphy_tx_init_txdlyen1 <= 1'd0; + a7litesataphy_tx_init_txuserrdy1 <= 1'd0; + a7litesataphy_tx_init_drp_start <= 1'd0; + a7litesataphy_tx_init_done <= 1'd0; + a7litesataphy_tx_init_pllreset <= 1'd0; + subfragments_litesataphy_gtptxinit_next_state <= 4'd0; + a7litesataphy_tx_init_gttxreset1 <= 1'd0; + a7litesataphy_tx_init_gttxpd1 <= 1'd0; + subfragments_litesataphy_gtptxinit_next_state <= subfragments_litesataphy_gtptxinit_state; + case (subfragments_litesataphy_gtptxinit_state) + 1'd1: begin + a7litesataphy_tx_init_gttxreset1 <= 1'd1; + a7litesataphy_tx_init_pllreset <= 1'd1; + a7litesataphy_tx_init_drp_start <= 1'd1; + if (a7litesataphy_tx_init_drp_done) begin + subfragments_litesataphy_gtptxinit_next_state <= 2'd2; + end + end + 2'd2: begin + a7litesataphy_tx_init_gttxreset1 <= 1'd1; + if (a7litesataphy_tx_init_plllock1) begin + subfragments_litesataphy_gtptxinit_next_state <= 2'd3; + end + end + 2'd3: begin + a7litesataphy_tx_init_gttxreset1 <= 1'd1; + if (a7litesataphy_tx_init_init_delay_done) begin + subfragments_litesataphy_gtptxinit_next_state <= 3'd4; + end + end + 3'd4: begin + a7litesataphy_tx_init_txuserrdy1 <= 1'd1; + if (a7litesataphy_tx_init_txresetdone1) begin + if (1'd1) begin + subfragments_litesataphy_gtptxinit_next_state <= 4'd9; + end else begin + subfragments_litesataphy_gtptxinit_next_state <= 3'd5; + end + end + end + 3'd5: begin + a7litesataphy_tx_init_txuserrdy1 <= 1'd1; + a7litesataphy_tx_init_txdlysreset1 <= 1'd1; + if (a7litesataphy_tx_init_txdlysresetdone1) begin + subfragments_litesataphy_gtptxinit_next_state <= 3'd6; + end + end + 3'd6: begin + a7litesataphy_tx_init_txuserrdy1 <= 1'd1; + a7litesataphy_tx_init_txphinit1 <= 1'd1; + if (a7litesataphy_tx_init_txphinitdone1) begin + subfragments_litesataphy_gtptxinit_next_state <= 3'd7; + end + end + 3'd7: begin + a7litesataphy_tx_init_txuserrdy1 <= 1'd1; + a7litesataphy_tx_init_txphalign1 <= 1'd1; + if (a7litesataphy_tx_init_txphaligndone_rising) begin + subfragments_litesataphy_gtptxinit_next_state <= 4'd8; + end + end + 4'd8: begin + a7litesataphy_tx_init_txuserrdy1 <= 1'd1; + a7litesataphy_tx_init_txdlyen1 <= 1'd1; + if (a7litesataphy_tx_init_txphaligndone_rising) begin + subfragments_litesataphy_gtptxinit_next_state <= 4'd9; + end + end + 4'd9: begin + a7litesataphy_tx_init_txuserrdy1 <= 1'd1; + a7litesataphy_tx_init_txdlyen1 <= 1'd1; + a7litesataphy_tx_init_done <= 1'd1; + if (a7litesataphy_tx_init_restart) begin + subfragments_litesataphy_gtptxinit_next_state <= 1'd0; + end + end + default: begin + a7litesataphy_tx_init_gttxreset1 <= 1'd1; + a7litesataphy_tx_init_gttxpd1 <= 1'd1; + a7litesataphy_tx_init_pllreset <= 1'd1; + subfragments_litesataphy_gtptxinit_next_state <= 1'd1; + end + endcase +end +assign a7litesataphy_tx_init_init_delay_done = (a7litesataphy_tx_init_init_delay_count == 1'd0); +assign a7litesataphy_tx_init_watchdog_done = (a7litesataphy_tx_init_watchdog_count == 1'd0); +assign a7litesataphy_rx_init_drp_clk = sys_clk; +assign a7litesataphy_rx_init_drp_addr = 5'd17; +always @(*) begin + a7litesataphy_rx_init_drp_di <= 16'd0; + if (a7litesataphy_rx_init_drpmask) begin + a7litesataphy_rx_init_drp_di <= (a7litesataphy_rx_init_drpvalue & 16'd63487); + end else begin + a7litesataphy_rx_init_drp_di <= a7litesataphy_rx_init_drpvalue; + end +end +assign a7litesataphy_rx_init_init_delay_wait = 1'd1; +assign a7litesataphy_rx_init_watchdog_wait = ((~a7litesataphy_rx_init_reset) & (~a7litesataphy_rx_init_done)); +assign a7litesataphy_rx_init_reset = (a7litesataphy_rx_init_restart | a7litesataphy_rx_init_watchdog_done); +always @(*) begin + a7litesataphy_rx_init_gtrxreset1 <= 1'd0; + a7litesataphy_rx_init_done <= 1'd0; + a7litesataphy_rx_init_gtrxpd1 <= 1'd0; + a7litesataphy_rx_init_rxdlysreset1 <= 1'd0; + a7litesataphy_rx_init_drp_we <= 1'd0; + a7litesataphy_rx_init_rxuserrdy1 <= 1'd0; + a7litesataphy_rx_init_drpmask <= 1'd0; + a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value_ce <= 1'd0; + subfragments_litesataphy_gtprxinit_next_state <= 4'd0; + a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value <= 16'd0; + a7litesataphy_rx_init_drp_en <= 1'd0; + subfragments_litesataphy_gtprxinit_next_state <= subfragments_litesataphy_gtprxinit_state; + case (subfragments_litesataphy_gtprxinit_state) + 1'd1: begin + a7litesataphy_rx_init_gtrxreset1 <= 1'd1; + if ((a7litesataphy_rx_init_plllock1 & a7litesataphy_rx_init_init_delay_done)) begin + subfragments_litesataphy_gtprxinit_next_state <= 2'd2; + end + end + 2'd2: begin + a7litesataphy_rx_init_gtrxreset1 <= 1'd1; + a7litesataphy_rx_init_drp_en <= 1'd1; + subfragments_litesataphy_gtprxinit_next_state <= 2'd3; + end + 2'd3: begin + a7litesataphy_rx_init_gtrxreset1 <= 1'd1; + if (a7litesataphy_rx_init_drp_rdy) begin + a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value <= a7litesataphy_rx_init_drp_do; + a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value_ce <= 1'd1; + subfragments_litesataphy_gtprxinit_next_state <= 3'd4; + end + end + 3'd4: begin + a7litesataphy_rx_init_gtrxreset1 <= 1'd1; + a7litesataphy_rx_init_drpmask <= 1'd1; + a7litesataphy_rx_init_drp_en <= 1'd1; + a7litesataphy_rx_init_drp_we <= 1'd1; + subfragments_litesataphy_gtprxinit_next_state <= 3'd5; + end + 3'd5: begin + a7litesataphy_rx_init_gtrxreset1 <= 1'd1; + if (a7litesataphy_rx_init_drp_rdy) begin + subfragments_litesataphy_gtprxinit_next_state <= 3'd6; + end + end + 3'd6: begin + a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; + if ((a7litesataphy_rx_init_rxpmaresetdone_r & (~a7litesataphy_rx_init_rxpmaresetdone1))) begin + subfragments_litesataphy_gtprxinit_next_state <= 3'd7; + end + end + 3'd7: begin + a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; + a7litesataphy_rx_init_drp_en <= 1'd1; + a7litesataphy_rx_init_drp_we <= 1'd1; + subfragments_litesataphy_gtprxinit_next_state <= 4'd8; + end + 4'd8: begin + a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; + if (a7litesataphy_rx_init_drp_rdy) begin + subfragments_litesataphy_gtprxinit_next_state <= 4'd9; + end + end + 4'd9: begin + a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; + if (a7litesataphy_rx_init_rxresetdone1) begin + if (1'd0) begin + subfragments_litesataphy_gtprxinit_next_state <= 4'd12; + end else begin + subfragments_litesataphy_gtprxinit_next_state <= 4'd10; + end + end + end + 4'd10: begin + a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; + a7litesataphy_rx_init_rxdlysreset1 <= 1'd1; + if (a7litesataphy_rx_init_rxdlysresetdone1) begin + subfragments_litesataphy_gtprxinit_next_state <= 4'd11; + end + end + 4'd11: begin + a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; + if (a7litesataphy_rx_init_rxsyncdone1) begin + subfragments_litesataphy_gtprxinit_next_state <= 4'd12; + end + end + 4'd12: begin + a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; + a7litesataphy_rx_init_done <= 1'd1; + if (a7litesataphy_rx_init_restart) begin + subfragments_litesataphy_gtprxinit_next_state <= 1'd0; + end + end + default: begin + a7litesataphy_rx_init_gtrxreset1 <= 1'd1; + a7litesataphy_rx_init_gtrxpd1 <= 1'd1; + subfragments_litesataphy_gtprxinit_next_state <= 1'd1; + end + endcase +end +assign a7litesataphy_rx_init_init_delay_done = (a7litesataphy_rx_init_init_delay_count == 1'd0); +assign a7litesataphy_rx_init_watchdog_done = (a7litesataphy_rx_init_watchdog_count == 1'd0); +assign a7litesataphy_txcominit0 = (a7litesataphy_tx_cominit_stb & (~a7litesataphy_i_d0)); +assign a7litesataphy_txcomwake0 = (a7litesataphy_tx_comwake_stb & (~a7litesataphy_i_d1)); +assign a7litesataphy_pulsesynchronizer0_o = (a7litesataphy_pulsesynchronizer0_toggle_o ^ a7litesataphy_pulsesynchronizer0_toggle_o_r); +assign a7litesataphy_pulsesynchronizer0_i = a7litesataphy_txcominit0; +assign a7litesataphy_txcominit1 = a7litesataphy_pulsesynchronizer0_o; +assign a7litesataphy_pulsesynchronizer1_o = (a7litesataphy_pulsesynchronizer1_toggle_o ^ a7litesataphy_pulsesynchronizer1_toggle_o_r); +assign a7litesataphy_pulsesynchronizer1_i = a7litesataphy_txcomwake0; +assign a7litesataphy_txcomwake1 = a7litesataphy_pulsesynchronizer1_o; +assign a7litesataphy_pulsesynchronizer2_o = (a7litesataphy_pulsesynchronizer2_toggle_o ^ a7litesataphy_pulsesynchronizer2_toggle_o_r); +assign a7litesataphy_pulsesynchronizer2_i = a7litesataphy_txcomfinish1; +assign a7litesataphy_txcomfinish0 = a7litesataphy_pulsesynchronizer2_o; +assign a7litesataphy_gtrefclk0 = crg_refclk; +assign a7litesataphy_txusrclk = sata_tx_clk; +assign a7litesataphy_txusrclk2 = sata_tx_clk; +assign a7litesataphy_rxusrclk = sata_rx_clk; +assign a7litesataphy_rxusrclk2 = sata_rx_clk; +assign ctrl_source_valid = 1'd1; +assign ctrl_sink_ready = 1'd1; +assign ctrl_reset = (ctrl_retry_timer_done | ctrl_align_timer_done); +assign ctrl_align_timer_done = (ctrl_align_timer_count == 1'd0); +assign ctrl_retry_timer_done = (ctrl_retry_timer_count == 1'd0); +always @(*) begin + ctrl_stability_timer_wait <= 1'd0; + ctrl_ready <= 1'd0; + a7litesataphy_tx_cominit_stb <= 1'd0; + a7litesataphy_tx_comwake_stb <= 1'd0; + a7litesataphy_rx_cdrhold <= 1'd0; + subfragments_litesataphy_next_state <= 4'd0; + ctrl_source_payload_data <= 32'd0; + ctrl_align_count_subfragments_litesataphyctrl_next_value0 <= 4'd0; + ctrl_source_payload_charisk <= 4'd0; + ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 <= 1'd0; + ctrl_tx_idle <= 1'd0; + ctrl_rx_reset <= 1'd0; + a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 <= 1'd0; + ctrl_tx_reset <= 1'd0; + a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 <= 1'd0; + a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value2 <= 1'd0; + a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value_ce2 <= 1'd0; + ctrl_retry_timer_wait <= 1'd0; + ctrl_align_timer_wait <= 1'd0; + subfragments_litesataphy_next_state <= subfragments_litesataphy_state; + case (subfragments_litesataphy_state) + 1'd1: begin + ctrl_tx_idle <= 1'd1; + a7litesataphy_rx_cdrhold <= 1'd1; + ctrl_align_count_subfragments_litesataphyctrl_next_value0 <= 2'd3; + ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 <= 1'd1; + if (a7litesataphy_ready) begin + a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 <= 1'd0; + a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 <= 1'd1; + a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value2 <= (~a7litesataphy_tx_polarity); + a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value_ce2 <= 1'd1; + subfragments_litesataphy_next_state <= 2'd2; + end + end + 2'd2: begin + ctrl_tx_idle <= 1'd1; + a7litesataphy_rx_cdrhold <= 1'd1; + a7litesataphy_tx_cominit_stb <= 1'd1; + if ((a7litesataphy_tx_cominit_ack & (~a7litesataphy_rx_cominit_stb))) begin + subfragments_litesataphy_next_state <= 2'd3; + end + end + 2'd3: begin + ctrl_tx_idle <= 1'd1; + a7litesataphy_rx_cdrhold <= 1'd1; + ctrl_retry_timer_wait <= 1'd1; + if (a7litesataphy_rx_cominit_stb) begin + subfragments_litesataphy_next_state <= 3'd4; + end + end + 3'd4: begin + ctrl_tx_idle <= 1'd1; + a7litesataphy_rx_cdrhold <= 1'd1; + ctrl_retry_timer_wait <= 1'd1; + if ((~a7litesataphy_rx_cominit_stb)) begin + subfragments_litesataphy_next_state <= 3'd5; + end + end + 3'd5: begin + ctrl_tx_idle <= 1'd1; + a7litesataphy_rx_cdrhold <= 1'd1; + subfragments_litesataphy_next_state <= 3'd6; + end + 3'd6: begin + ctrl_tx_idle <= 1'd1; + a7litesataphy_rx_cdrhold <= 1'd1; + a7litesataphy_tx_comwake_stb <= 1'd1; + if (a7litesataphy_tx_comwake_ack) begin + subfragments_litesataphy_next_state <= 3'd7; + end + end + 3'd7: begin + ctrl_tx_idle <= 1'd1; + a7litesataphy_rx_cdrhold <= 1'd1; + ctrl_retry_timer_wait <= 1'd1; + if (a7litesataphy_rx_comwake_stb) begin + subfragments_litesataphy_next_state <= 4'd8; + end + end + 4'd8: begin + ctrl_tx_idle <= 1'd1; + a7litesataphy_rx_cdrhold <= 1'd1; + if ((~a7litesataphy_rx_comwake_stb)) begin + subfragments_litesataphy_next_state <= 4'd9; + end + end + 4'd9: begin + a7litesataphy_rx_cdrhold <= 1'd1; + ctrl_source_payload_data <= 31'd1246382666; + ctrl_source_payload_charisk <= 1'd0; + ctrl_align_timer_wait <= 1'd1; + if ((~a7litesataphy_rx_idle)) begin + if (((ctrl_sink_valid & (ctrl_sink_payload_charisk == 1'd1)) & (ctrl_sink_payload_data == 31'd2068466364))) begin + a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 <= 1'd0; + a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 <= 1'd1; + subfragments_litesataphy_next_state <= 4'd10; + end + if (((ctrl_sink_valid & (ctrl_sink_payload_charisk == 1'd1)) & (ctrl_sink_payload_data == 31'd2075506108))) begin + a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 <= 1'd1; + a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 <= 1'd1; + subfragments_litesataphy_next_state <= 4'd10; + end + end + end + 4'd10: begin + ctrl_align_timer_wait <= 1'd1; + ctrl_source_payload_data <= 31'd2068466364; + ctrl_source_payload_charisk <= 1'd1; + if ((ctrl_sink_valid & (ctrl_sink_payload_charisk == 1'd1))) begin + if ((ctrl_sink_payload_data[7:0] == 7'd124)) begin + ctrl_align_count_subfragments_litesataphyctrl_next_value0 <= (ctrl_align_count - 1'd1); + ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 <= 1'd1; + end else begin + ctrl_align_count_subfragments_litesataphyctrl_next_value0 <= 2'd3; + ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 <= 1'd1; + end + end + if ((ctrl_align_count == 1'd0)) begin + subfragments_litesataphy_next_state <= 4'd11; + end + end + 4'd11: begin + ctrl_source_payload_data <= 32'd3048576380; + ctrl_source_payload_charisk <= 1'd1; + ctrl_stability_timer_wait <= 1'd1; + ctrl_ready <= ctrl_stability_timer_done; + if (ctrl_rx_idle) begin + subfragments_litesataphy_next_state <= 1'd0; + end else begin + if (ctrl_misalign) begin + ctrl_rx_reset <= 1'd1; + subfragments_litesataphy_next_state <= 4'd12; + end + end + end + 4'd12: begin + if (a7litesataphy_ready) begin + subfragments_litesataphy_next_state <= 4'd11; + end + end + default: begin + ctrl_tx_idle <= 1'd1; + a7litesataphy_rx_cdrhold <= 1'd1; + ctrl_rx_reset <= 1'd1; + ctrl_tx_reset <= 1'd1; + subfragments_litesataphy_next_state <= 1'd1; + end + endcase +end +assign ctrl_stability_timer_done = (ctrl_stability_timer_count == 1'd0); +assign datapath_mux_sel = ctrl_ready; +assign datapath_mux_endpoint0_sink_valid = ctrl_source_valid; +assign ctrl_source_ready = datapath_mux_endpoint0_sink_ready; +assign datapath_mux_endpoint0_sink_first = ctrl_source_first; +assign datapath_mux_endpoint0_sink_last = ctrl_source_last; +assign datapath_mux_endpoint0_sink_payload_data = ctrl_source_payload_data; +assign datapath_mux_endpoint0_sink_payload_charisk = ctrl_source_payload_charisk; +assign datapath_mux_endpoint1_sink_valid = datapath_sink_sink_valid; +assign datapath_sink_sink_ready = datapath_mux_endpoint1_sink_ready; +assign datapath_mux_endpoint1_sink_first = datapath_sink_sink_first; +assign datapath_mux_endpoint1_sink_last = datapath_sink_sink_last; +assign datapath_mux_endpoint1_sink_payload_data = datapath_sink_sink_payload_data; +assign datapath_mux_endpoint1_sink_payload_charisk = datapath_sink_sink_payload_charisk; +assign datapath_tx_sink_sink_valid = datapath_mux_source_valid; +assign datapath_mux_source_ready = datapath_tx_sink_sink_ready; +assign datapath_tx_sink_sink_first = datapath_mux_source_first; +assign datapath_tx_sink_sink_last = datapath_mux_source_last; +assign datapath_tx_sink_sink_payload_data = datapath_mux_source_payload_data; +assign datapath_tx_sink_sink_payload_charisk = datapath_mux_source_payload_charisk; +assign a7litesataphy_sink_valid = datapath_tx_source_source_valid; +assign datapath_tx_source_source_ready = a7litesataphy_sink_ready; +assign a7litesataphy_sink_first = datapath_tx_source_source_first; +assign a7litesataphy_sink_last = datapath_tx_source_source_last; +assign a7litesataphy_sink_payload_data = datapath_tx_source_source_payload_data; +assign a7litesataphy_sink_payload_charisk = datapath_tx_source_source_payload_charisk; +assign datapath_demux_sel = ctrl_ready; +assign datapath_rx_sink_sink_valid = a7litesataphy_source_valid; +assign a7litesataphy_source_ready = datapath_rx_sink_sink_ready; +assign datapath_rx_sink_sink_first = a7litesataphy_source_first; +assign datapath_rx_sink_sink_last = a7litesataphy_source_last; +assign datapath_rx_sink_sink_payload_data = a7litesataphy_source_payload_data; +assign datapath_rx_sink_sink_payload_charisk = a7litesataphy_source_payload_charisk; +assign datapath_demux_sink_valid = datapath_rx_source_source_valid; +assign datapath_rx_source_source_ready = datapath_demux_sink_ready; +assign datapath_demux_sink_first = datapath_rx_source_source_first; +assign datapath_demux_sink_last = datapath_rx_source_source_last; +assign datapath_demux_sink_payload_data = datapath_rx_source_source_payload_data; +assign datapath_demux_sink_payload_charisk = datapath_rx_source_source_payload_charisk; +assign datapath_align_timer_sink_valid = datapath_rx_source_source_valid; +assign datapath_align_timer_sink_first = datapath_rx_source_source_first; +assign datapath_align_timer_sink_last = datapath_rx_source_source_last; +assign datapath_align_timer_sink_payload_data = datapath_rx_source_source_payload_data; +assign datapath_align_timer_sink_payload_charisk = datapath_rx_source_source_payload_charisk; +assign ctrl_sink_valid = datapath_demux_endpoint0_source_valid; +assign datapath_demux_endpoint0_source_ready = ctrl_sink_ready; +assign ctrl_sink_first = datapath_demux_endpoint0_source_first; +assign ctrl_sink_last = datapath_demux_endpoint0_source_last; +assign ctrl_sink_payload_data = datapath_demux_endpoint0_source_payload_data; +assign ctrl_sink_payload_charisk = datapath_demux_endpoint0_source_payload_charisk; +assign datapath_source_source_valid = datapath_demux_endpoint1_source_valid; +assign datapath_demux_endpoint1_source_ready = datapath_source_source_ready; +assign datapath_source_source_first = datapath_demux_endpoint1_source_first; +assign datapath_source_source_last = datapath_demux_endpoint1_source_last; +assign datapath_source_source_payload_data = datapath_demux_endpoint1_source_payload_data; +assign datapath_source_source_payload_charisk = datapath_demux_endpoint1_source_payload_charisk; +assign datapath_misalign = (datapath_rx_source_source_valid & ((datapath_rx_source_source_payload_charisk & 4'd14) != 1'd0)); +assign datapath_rx_idle = datapath_align_timer_done; +always @(*) begin + datapath_mux_source_payload_charisk <= 4'd0; + datapath_mux_endpoint0_sink_ready <= 1'd0; + datapath_mux_source_valid <= 1'd0; + datapath_mux_source_first <= 1'd0; + datapath_mux_source_last <= 1'd0; + datapath_mux_source_payload_data <= 32'd0; + datapath_mux_endpoint1_sink_ready <= 1'd0; + case (datapath_mux_sel) + 1'd0: begin + datapath_mux_source_valid <= datapath_mux_endpoint0_sink_valid; + datapath_mux_endpoint0_sink_ready <= datapath_mux_source_ready; + datapath_mux_source_first <= datapath_mux_endpoint0_sink_first; + datapath_mux_source_last <= datapath_mux_endpoint0_sink_last; + datapath_mux_source_payload_data <= datapath_mux_endpoint0_sink_payload_data; + datapath_mux_source_payload_charisk <= datapath_mux_endpoint0_sink_payload_charisk; + end + 1'd1: begin + datapath_mux_source_valid <= datapath_mux_endpoint1_sink_valid; + datapath_mux_endpoint1_sink_ready <= datapath_mux_source_ready; + datapath_mux_source_first <= datapath_mux_endpoint1_sink_first; + datapath_mux_source_last <= datapath_mux_endpoint1_sink_last; + datapath_mux_source_payload_data <= datapath_mux_endpoint1_sink_payload_data; + datapath_mux_source_payload_charisk <= datapath_mux_endpoint1_sink_payload_charisk; + end + endcase +end +assign datapath_tx_fifo_sink_valid = datapath_tx_sink_sink_valid; +assign datapath_tx_sink_sink_ready = datapath_tx_fifo_sink_ready; +assign datapath_tx_fifo_sink_first = datapath_tx_sink_sink_first; +assign datapath_tx_fifo_sink_last = datapath_tx_sink_sink_last; +assign datapath_tx_fifo_sink_payload_data = datapath_tx_sink_sink_payload_data; +assign datapath_tx_fifo_sink_payload_charisk = datapath_tx_sink_sink_payload_charisk; +assign datapath_tx_converter_sink_valid = datapath_tx_fifo_source_valid; +assign datapath_tx_fifo_source_ready = datapath_tx_converter_sink_ready; +assign datapath_tx_converter_sink_first = datapath_tx_fifo_source_first; +assign datapath_tx_converter_sink_last = datapath_tx_fifo_source_last; +assign datapath_tx_converter_sink_payload_data = datapath_tx_fifo_source_payload_data; +assign datapath_tx_converter_sink_payload_charisk = datapath_tx_fifo_source_payload_charisk; +assign datapath_tx_source_source_valid = datapath_tx_converter_source_valid; +assign datapath_tx_converter_source_ready = datapath_tx_source_source_ready; +assign datapath_tx_source_source_first = datapath_tx_converter_source_first; +assign datapath_tx_source_source_last = datapath_tx_converter_source_last; +assign datapath_tx_source_source_payload_data = datapath_tx_converter_source_payload_data; +assign datapath_tx_source_source_payload_charisk = datapath_tx_converter_source_payload_charisk; +assign datapath_tx_fifo_asyncfifo_din = {datapath_tx_fifo_fifo_in_last, datapath_tx_fifo_fifo_in_first, datapath_tx_fifo_fifo_in_payload_charisk, datapath_tx_fifo_fifo_in_payload_data}; +assign {datapath_tx_fifo_fifo_out_last, datapath_tx_fifo_fifo_out_first, datapath_tx_fifo_fifo_out_payload_charisk, datapath_tx_fifo_fifo_out_payload_data} = datapath_tx_fifo_asyncfifo_dout; +assign datapath_tx_fifo_sink_ready = datapath_tx_fifo_asyncfifo_writable; +assign datapath_tx_fifo_asyncfifo_we = datapath_tx_fifo_sink_valid; +assign datapath_tx_fifo_fifo_in_first = datapath_tx_fifo_sink_first; +assign datapath_tx_fifo_fifo_in_last = datapath_tx_fifo_sink_last; +assign datapath_tx_fifo_fifo_in_payload_data = datapath_tx_fifo_sink_payload_data; +assign datapath_tx_fifo_fifo_in_payload_charisk = datapath_tx_fifo_sink_payload_charisk; +assign datapath_tx_fifo_source_valid = datapath_tx_fifo_asyncfifo_readable; +assign datapath_tx_fifo_source_first = datapath_tx_fifo_fifo_out_first; +assign datapath_tx_fifo_source_last = datapath_tx_fifo_fifo_out_last; +assign datapath_tx_fifo_source_payload_data = datapath_tx_fifo_fifo_out_payload_data; +assign datapath_tx_fifo_source_payload_charisk = datapath_tx_fifo_fifo_out_payload_charisk; +assign datapath_tx_fifo_asyncfifo_re = datapath_tx_fifo_source_ready; +assign datapath_tx_fifo_graycounter0_ce = (datapath_tx_fifo_asyncfifo_writable & datapath_tx_fifo_asyncfifo_we); +assign datapath_tx_fifo_graycounter1_ce = (datapath_tx_fifo_asyncfifo_readable & datapath_tx_fifo_asyncfifo_re); +assign datapath_tx_fifo_asyncfifo_writable = (((datapath_tx_fifo_graycounter0_q[3] == datapath_tx_fifo_consume_wdomain[3]) | (datapath_tx_fifo_graycounter0_q[2] == datapath_tx_fifo_consume_wdomain[2])) | (datapath_tx_fifo_graycounter0_q[1:0] != datapath_tx_fifo_consume_wdomain[1:0])); +assign datapath_tx_fifo_asyncfifo_readable = (datapath_tx_fifo_graycounter1_q != datapath_tx_fifo_produce_rdomain); +assign datapath_tx_fifo_wrport_adr = datapath_tx_fifo_graycounter0_q_binary[2:0]; +assign datapath_tx_fifo_wrport_dat_w = datapath_tx_fifo_asyncfifo_din; +assign datapath_tx_fifo_wrport_we = datapath_tx_fifo_graycounter0_ce; +assign datapath_tx_fifo_rdport_adr = datapath_tx_fifo_graycounter1_q_next_binary[2:0]; +assign datapath_tx_fifo_asyncfifo_dout = datapath_tx_fifo_rdport_dat_r; +always @(*) begin + datapath_tx_fifo_graycounter0_q_next_binary <= 4'd0; + if (datapath_tx_fifo_graycounter0_ce) begin + datapath_tx_fifo_graycounter0_q_next_binary <= (datapath_tx_fifo_graycounter0_q_binary + 1'd1); + end else begin + datapath_tx_fifo_graycounter0_q_next_binary <= datapath_tx_fifo_graycounter0_q_binary; + end +end +assign datapath_tx_fifo_graycounter0_q_next = (datapath_tx_fifo_graycounter0_q_next_binary ^ datapath_tx_fifo_graycounter0_q_next_binary[3:1]); +always @(*) begin + datapath_tx_fifo_graycounter1_q_next_binary <= 4'd0; + if (datapath_tx_fifo_graycounter1_ce) begin + datapath_tx_fifo_graycounter1_q_next_binary <= (datapath_tx_fifo_graycounter1_q_binary + 1'd1); + end else begin + datapath_tx_fifo_graycounter1_q_next_binary <= datapath_tx_fifo_graycounter1_q_binary; + end +end +assign datapath_tx_fifo_graycounter1_q_next = (datapath_tx_fifo_graycounter1_q_next_binary ^ datapath_tx_fifo_graycounter1_q_next_binary[3:1]); +assign datapath_tx_converter_converter_sink_valid = datapath_tx_converter_sink_valid; +assign datapath_tx_converter_converter_sink_first = datapath_tx_converter_sink_first; +assign datapath_tx_converter_converter_sink_last = datapath_tx_converter_sink_last; +assign datapath_tx_converter_sink_ready = datapath_tx_converter_converter_sink_ready; +always @(*) begin + datapath_tx_converter_converter_sink_payload_data <= 36'd0; + datapath_tx_converter_converter_sink_payload_data[15:0] <= datapath_tx_converter_sink_payload_data[15:0]; + datapath_tx_converter_converter_sink_payload_data[17:16] <= datapath_tx_converter_sink_payload_charisk[1:0]; + datapath_tx_converter_converter_sink_payload_data[33:18] <= datapath_tx_converter_sink_payload_data[31:16]; + datapath_tx_converter_converter_sink_payload_data[35:34] <= datapath_tx_converter_sink_payload_charisk[3:2]; +end +assign datapath_tx_converter_source_valid = datapath_tx_converter_source_source_valid; +assign datapath_tx_converter_source_first = datapath_tx_converter_source_source_first; +assign datapath_tx_converter_source_last = datapath_tx_converter_source_source_last; +assign datapath_tx_converter_source_source_ready = datapath_tx_converter_source_ready; +assign {datapath_tx_converter_source_payload_charisk, datapath_tx_converter_source_payload_data} = datapath_tx_converter_source_source_payload_data; +assign datapath_tx_converter_source_source_valid = datapath_tx_converter_converter_source_valid; +assign datapath_tx_converter_converter_source_ready = datapath_tx_converter_source_source_ready; +assign datapath_tx_converter_source_source_first = datapath_tx_converter_converter_source_first; +assign datapath_tx_converter_source_source_last = datapath_tx_converter_converter_source_last; +assign datapath_tx_converter_source_source_payload_data = datapath_tx_converter_converter_source_payload_data; +assign datapath_tx_converter_converter_first = (datapath_tx_converter_converter_mux == 1'd0); +assign datapath_tx_converter_converter_last = (datapath_tx_converter_converter_mux == 1'd1); +assign datapath_tx_converter_converter_source_valid = datapath_tx_converter_converter_sink_valid; +assign datapath_tx_converter_converter_source_first = (datapath_tx_converter_converter_sink_first & datapath_tx_converter_converter_first); +assign datapath_tx_converter_converter_source_last = (datapath_tx_converter_converter_sink_last & datapath_tx_converter_converter_last); +assign datapath_tx_converter_converter_sink_ready = (datapath_tx_converter_converter_last & datapath_tx_converter_converter_source_ready); +always @(*) begin + datapath_tx_converter_converter_source_payload_data <= 18'd0; + case (datapath_tx_converter_converter_mux) + 1'd0: begin + datapath_tx_converter_converter_source_payload_data <= datapath_tx_converter_converter_sink_payload_data[17:0]; + end + default: begin + datapath_tx_converter_converter_source_payload_data <= datapath_tx_converter_converter_sink_payload_data[35:18]; + end + endcase +end +assign datapath_tx_converter_converter_source_payload_valid_token_count = datapath_tx_converter_converter_last; +assign datapath_rx_sr_charisk = {datapath_rx_sink_sink_payload_charisk, datapath_rx_last_charisk}; +assign datapath_rx_sr_data = {datapath_rx_sink_sink_payload_data, datapath_rx_last_data}; +assign datapath_rx_converter_sink_valid = datapath_rx_sink_sink_valid; +always @(*) begin + datapath_rx_converter_sink_payload_data <= 16'd0; + datapath_rx_converter_sink_payload_charisk <= 2'd0; + case (datapath_rx_byte_alignment) + 1'd1: begin + datapath_rx_converter_sink_payload_charisk <= datapath_rx_sr_charisk[3:2]; + datapath_rx_converter_sink_payload_data <= datapath_rx_sr_data[31:16]; + end + 2'd2: begin + datapath_rx_converter_sink_payload_charisk <= datapath_rx_sr_charisk[2:1]; + datapath_rx_converter_sink_payload_data <= datapath_rx_sr_data[23:8]; + end + endcase +end +assign datapath_rx_sink_sink_ready = datapath_rx_converter_sink_ready; +assign datapath_rx_converter_reset = (datapath_rx_converter_source_payload_charisk[3:2] != 1'd0); +assign datapath_rx_fifo_sink_valid = datapath_rx_converter_source_valid; +assign datapath_rx_converter_source_ready = datapath_rx_fifo_sink_ready; +assign datapath_rx_fifo_sink_first = datapath_rx_converter_source_first; +assign datapath_rx_fifo_sink_last = datapath_rx_converter_source_last; +assign datapath_rx_fifo_sink_payload_data = datapath_rx_converter_source_payload_data; +assign datapath_rx_fifo_sink_payload_charisk = datapath_rx_converter_source_payload_charisk; +assign datapath_rx_source_source_valid = datapath_rx_fifo_source_valid; +assign datapath_rx_fifo_source_ready = datapath_rx_source_source_ready; +assign datapath_rx_source_source_first = datapath_rx_fifo_source_first; +assign datapath_rx_source_source_last = datapath_rx_fifo_source_last; +assign datapath_rx_source_source_payload_data = datapath_rx_fifo_source_payload_data; +assign datapath_rx_source_source_payload_charisk = datapath_rx_fifo_source_payload_charisk; +assign datapath_rx_converter_converter_sink_valid = datapath_rx_converter_sink_valid; +assign datapath_rx_converter_converter_sink_first = datapath_rx_converter_sink_first; +assign datapath_rx_converter_converter_sink_last = datapath_rx_converter_sink_last; +assign datapath_rx_converter_sink_ready = datapath_rx_converter_converter_sink_ready; +assign datapath_rx_converter_converter_sink_payload_data = {datapath_rx_converter_sink_payload_charisk, datapath_rx_converter_sink_payload_data}; +assign datapath_rx_converter_source_valid = datapath_rx_converter_source_source_valid; +assign datapath_rx_converter_source_first = datapath_rx_converter_source_source_first; +assign datapath_rx_converter_source_last = datapath_rx_converter_source_source_last; +assign datapath_rx_converter_source_source_ready = datapath_rx_converter_source_ready; +always @(*) begin + datapath_rx_converter_source_payload_data <= 32'd0; + datapath_rx_converter_source_payload_data[15:0] <= datapath_rx_converter_source_source_payload_data[15:0]; + datapath_rx_converter_source_payload_data[31:16] <= datapath_rx_converter_source_source_payload_data[33:18]; +end +always @(*) begin + datapath_rx_converter_source_payload_charisk <= 4'd0; + datapath_rx_converter_source_payload_charisk[1:0] <= datapath_rx_converter_source_source_payload_data[17:16]; + datapath_rx_converter_source_payload_charisk[3:2] <= datapath_rx_converter_source_source_payload_data[35:34]; +end +assign datapath_rx_converter_source_source_valid = datapath_rx_converter_converter_source_valid; +assign datapath_rx_converter_converter_source_ready = datapath_rx_converter_source_source_ready; +assign datapath_rx_converter_source_source_first = datapath_rx_converter_converter_source_first; +assign datapath_rx_converter_source_source_last = datapath_rx_converter_converter_source_last; +assign datapath_rx_converter_source_source_payload_data = datapath_rx_converter_converter_source_payload_data; +assign datapath_rx_converter_converter_sink_ready = ((~datapath_rx_converter_converter_strobe_all) | datapath_rx_converter_converter_source_ready); +assign datapath_rx_converter_converter_source_valid = datapath_rx_converter_converter_strobe_all; +assign datapath_rx_converter_converter_load_part = (datapath_rx_converter_converter_sink_valid & datapath_rx_converter_converter_sink_ready); +assign datapath_rx_fifo_asyncfifo_din = {datapath_rx_fifo_fifo_in_last, datapath_rx_fifo_fifo_in_first, datapath_rx_fifo_fifo_in_payload_charisk, datapath_rx_fifo_fifo_in_payload_data}; +assign {datapath_rx_fifo_fifo_out_last, datapath_rx_fifo_fifo_out_first, datapath_rx_fifo_fifo_out_payload_charisk, datapath_rx_fifo_fifo_out_payload_data} = datapath_rx_fifo_asyncfifo_dout; +assign datapath_rx_fifo_sink_ready = datapath_rx_fifo_asyncfifo_writable; +assign datapath_rx_fifo_asyncfifo_we = datapath_rx_fifo_sink_valid; +assign datapath_rx_fifo_fifo_in_first = datapath_rx_fifo_sink_first; +assign datapath_rx_fifo_fifo_in_last = datapath_rx_fifo_sink_last; +assign datapath_rx_fifo_fifo_in_payload_data = datapath_rx_fifo_sink_payload_data; +assign datapath_rx_fifo_fifo_in_payload_charisk = datapath_rx_fifo_sink_payload_charisk; +assign datapath_rx_fifo_source_valid = datapath_rx_fifo_asyncfifo_readable; +assign datapath_rx_fifo_source_first = datapath_rx_fifo_fifo_out_first; +assign datapath_rx_fifo_source_last = datapath_rx_fifo_fifo_out_last; +assign datapath_rx_fifo_source_payload_data = datapath_rx_fifo_fifo_out_payload_data; +assign datapath_rx_fifo_source_payload_charisk = datapath_rx_fifo_fifo_out_payload_charisk; +assign datapath_rx_fifo_asyncfifo_re = datapath_rx_fifo_source_ready; +assign datapath_rx_fifo_graycounter0_ce = (datapath_rx_fifo_asyncfifo_writable & datapath_rx_fifo_asyncfifo_we); +assign datapath_rx_fifo_graycounter1_ce = (datapath_rx_fifo_asyncfifo_readable & datapath_rx_fifo_asyncfifo_re); +assign datapath_rx_fifo_asyncfifo_writable = (((datapath_rx_fifo_graycounter0_q[3] == datapath_rx_fifo_consume_wdomain[3]) | (datapath_rx_fifo_graycounter0_q[2] == datapath_rx_fifo_consume_wdomain[2])) | (datapath_rx_fifo_graycounter0_q[1:0] != datapath_rx_fifo_consume_wdomain[1:0])); +assign datapath_rx_fifo_asyncfifo_readable = (datapath_rx_fifo_graycounter1_q != datapath_rx_fifo_produce_rdomain); +assign datapath_rx_fifo_wrport_adr = datapath_rx_fifo_graycounter0_q_binary[2:0]; +assign datapath_rx_fifo_wrport_dat_w = datapath_rx_fifo_asyncfifo_din; +assign datapath_rx_fifo_wrport_we = datapath_rx_fifo_graycounter0_ce; +assign datapath_rx_fifo_rdport_adr = datapath_rx_fifo_graycounter1_q_next_binary[2:0]; +assign datapath_rx_fifo_asyncfifo_dout = datapath_rx_fifo_rdport_dat_r; +always @(*) begin + datapath_rx_fifo_graycounter0_q_next_binary <= 4'd0; + if (datapath_rx_fifo_graycounter0_ce) begin + datapath_rx_fifo_graycounter0_q_next_binary <= (datapath_rx_fifo_graycounter0_q_binary + 1'd1); + end else begin + datapath_rx_fifo_graycounter0_q_next_binary <= datapath_rx_fifo_graycounter0_q_binary; + end +end +assign datapath_rx_fifo_graycounter0_q_next = (datapath_rx_fifo_graycounter0_q_next_binary ^ datapath_rx_fifo_graycounter0_q_next_binary[3:1]); +always @(*) begin + datapath_rx_fifo_graycounter1_q_next_binary <= 4'd0; + if (datapath_rx_fifo_graycounter1_ce) begin + datapath_rx_fifo_graycounter1_q_next_binary <= (datapath_rx_fifo_graycounter1_q_binary + 1'd1); + end else begin + datapath_rx_fifo_graycounter1_q_next_binary <= datapath_rx_fifo_graycounter1_q_binary; + end +end +assign datapath_rx_fifo_graycounter1_q_next = (datapath_rx_fifo_graycounter1_q_next_binary ^ datapath_rx_fifo_graycounter1_q_next_binary[3:1]); +always @(*) begin + datapath_demux_endpoint0_source_first <= 1'd0; + datapath_demux_endpoint0_source_last <= 1'd0; + datapath_demux_endpoint0_source_payload_data <= 32'd0; + datapath_demux_endpoint0_source_payload_charisk <= 4'd0; + datapath_demux_endpoint1_source_valid <= 1'd0; + datapath_demux_endpoint1_source_first <= 1'd0; + datapath_demux_endpoint1_source_last <= 1'd0; + datapath_demux_endpoint1_source_payload_data <= 32'd0; + datapath_demux_sink_ready <= 1'd0; + datapath_demux_endpoint1_source_payload_charisk <= 4'd0; + datapath_demux_endpoint0_source_valid <= 1'd0; + case (datapath_demux_sel) + 1'd0: begin + datapath_demux_endpoint0_source_valid <= datapath_demux_sink_valid; + datapath_demux_sink_ready <= datapath_demux_endpoint0_source_ready; + datapath_demux_endpoint0_source_first <= datapath_demux_sink_first; + datapath_demux_endpoint0_source_last <= datapath_demux_sink_last; + datapath_demux_endpoint0_source_payload_data <= datapath_demux_sink_payload_data; + datapath_demux_endpoint0_source_payload_charisk <= datapath_demux_sink_payload_charisk; + end + 1'd1: begin + datapath_demux_endpoint1_source_valid <= datapath_demux_sink_valid; + datapath_demux_sink_ready <= datapath_demux_endpoint1_source_ready; + datapath_demux_endpoint1_source_first <= datapath_demux_sink_first; + datapath_demux_endpoint1_source_last <= datapath_demux_sink_last; + datapath_demux_endpoint1_source_payload_data <= datapath_demux_sink_payload_data; + datapath_demux_endpoint1_source_payload_charisk <= datapath_demux_sink_payload_charisk; + end + endcase +end +always @(*) begin + datapath_align_timer_wait <= 1'd0; + if (((datapath_align_timer_sink_valid & (datapath_align_timer_sink_payload_charisk == 1'd1)) & (datapath_align_timer_sink_payload_data == 31'd2068466364))) begin + datapath_align_timer_wait <= 1'd0; + end else begin + datapath_align_timer_wait <= 1'd1; + end +end +assign datapath_align_timer_done = (datapath_align_timer_count == 1'd0); +assign link_litesatalinktx_from_rx_valid = link_litesatalinkrx_to_tx_valid; +assign link_litesatalinkrx_to_tx_ready = link_litesatalinktx_from_rx_ready; +assign link_litesatalinktx_from_rx_first = link_litesatalinkrx_to_tx_first; +assign link_litesatalinktx_from_rx_last = link_litesatalinkrx_to_tx_last; +assign link_litesatalinktx_from_rx_payload_idle = link_litesatalinkrx_to_tx_payload_idle; +assign link_litesatalinktx_from_rx_payload_insert = link_litesatalinkrx_to_tx_payload_insert; +assign link_litesatalinktx_from_rx_payload_primitive_valid = link_litesatalinkrx_to_tx_payload_primitive_valid; +assign link_litesatalinktx_from_rx_payload_primitive = link_litesatalinkrx_to_tx_payload_primitive; +assign link_litesatalinkrx_hold = (link_rx_buffer_level > 7'd64); +always @(*) begin + link_litesatalinktx_scrambler_source_ready <= 1'd0; + link_litesatalinktx_source_source_valid <= 1'd0; + link_litesatalinktx_source_source_payload_charisk <= 4'd0; + link_litesatalinktx_source_source_payload_data <= 32'd0; + if (link_litesatalinktx_from_rx_payload_insert) begin + link_litesatalinktx_source_source_valid <= 1'd1; + link_litesatalinktx_source_source_payload_data <= link_litesatalinktx_from_rx_payload_insert; + link_litesatalinktx_source_source_payload_charisk <= 1'd1; + end else begin + if (link_litesatalinktx_insert) begin + link_litesatalinktx_source_source_valid <= 1'd1; + link_litesatalinktx_source_source_payload_data <= link_litesatalinktx_insert; + link_litesatalinktx_source_source_payload_charisk <= 1'd1; + end else begin + if (link_litesatalinktx_copy) begin + link_litesatalinktx_source_source_valid <= 1'd1; + link_litesatalinktx_scrambler_source_ready <= link_litesatalinktx_source_source_ready; + if (link_litesatalinktx_scrambler_source_valid) begin + link_litesatalinktx_source_source_payload_data <= link_litesatalinktx_scrambler_source_payload_data; + link_litesatalinktx_source_source_payload_charisk <= 1'd0; + end else begin + link_litesatalinktx_source_source_payload_data <= 32'd3587549820; + link_litesatalinktx_source_source_payload_charisk <= 1'd1; + end + end + end + end +end +assign link_tx_sink_valid = link_litesatalinktx_source_source_valid; +assign link_litesatalinktx_source_source_ready = link_tx_sink_ready; +assign link_tx_sink_first = link_litesatalinktx_source_source_first; +assign link_tx_sink_last = link_litesatalinktx_source_source_last; +assign link_tx_sink_payload_data = link_litesatalinktx_source_source_payload_data; +assign link_tx_sink_payload_charisk = link_litesatalinktx_source_source_payload_charisk; +assign link_litesatalinktx_crc_busy = (~link_litesatalinktx_crc_is_ongoing); +assign link_litesatalinktx_crc_data1 = link_litesatalinktx_crc_data0; +assign link_litesatalinktx_crc_last = link_litesatalinktx_crc_reg_i; +assign link_litesatalinktx_crc_value = link_litesatalinktx_crc_reg_i; +assign link_litesatalinktx_crc_error = (link_litesatalinktx_crc_next != 1'd0); +assign link_litesatalinktx_crc_new = (link_litesatalinktx_crc_last ^ link_litesatalinktx_crc_data1); +always @(*) begin + link_litesatalinktx_crc_next <= 32'd0; + link_litesatalinktx_crc_next[0] <= ((((((((((((link_litesatalinktx_crc_new[0] ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); + link_litesatalinktx_crc_next[1] <= ((((((((((((link_litesatalinktx_crc_new[1] ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[12]); + link_litesatalinktx_crc_next[2] <= (((((((((((((((link_litesatalinktx_crc_new[2] ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]); + link_litesatalinktx_crc_next[3] <= ((((((((((((((link_litesatalinktx_crc_new[3] ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[17]); + link_litesatalinktx_crc_next[4] <= ((((((((((((((((link_litesatalinktx_crc_new[4] ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); + link_litesatalinktx_crc_next[5] <= ((((((((((((((link_litesatalinktx_crc_new[5] ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[6]); + link_litesatalinktx_crc_next[6] <= ((((((((((((((link_litesatalinktx_crc_new[6] ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[7]); + link_litesatalinktx_crc_next[7] <= (((((((((((((((link_litesatalinktx_crc_new[7] ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[16]); + link_litesatalinktx_crc_next[8] <= ((((((((((((link_litesatalinktx_crc_new[8] ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); + link_litesatalinktx_crc_next[9] <= (((((((((((link_litesatalinktx_crc_new[9] ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[12]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[13]); + link_litesatalinktx_crc_next[10] <= ((((((((((((link_litesatalinktx_crc_new[5] ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]); + link_litesatalinktx_crc_next[11] <= ((((((((((((((((link_litesatalinktx_crc_new[4] ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); + link_litesatalinktx_crc_next[12] <= ((((((((((((((((link_litesatalinktx_crc_new[5] ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); + link_litesatalinktx_crc_next[13] <= (((((((((((((((link_litesatalinktx_crc_new[6] ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[13]); + link_litesatalinktx_crc_next[14] <= ((((((((((((((link_litesatalinktx_crc_new[7] ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[14]); + link_litesatalinktx_crc_next[15] <= ((((((((((((((link_litesatalinktx_crc_new[8] ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[12]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[15]); + link_litesatalinktx_crc_next[16] <= (((((((((((((link_litesatalinktx_crc_new[19] ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[12]); + link_litesatalinktx_crc_next[17] <= (((((((((((((link_litesatalinktx_crc_new[20] ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[13]); + link_litesatalinktx_crc_next[18] <= ((((((((((((link_litesatalinktx_crc_new[21] ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[14]); + link_litesatalinktx_crc_next[19] <= (((((((((((link_litesatalinktx_crc_new[22] ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[15]); + link_litesatalinktx_crc_next[20] <= (((((((((((link_litesatalinktx_crc_new[23] ^ link_litesatalinktx_crc_new[12]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[16]); + link_litesatalinktx_crc_next[21] <= (((((((((((link_litesatalinktx_crc_new[24] ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[17]); + link_litesatalinktx_crc_next[22] <= (((((((((((((link_litesatalinktx_crc_new[14] ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); + link_litesatalinktx_crc_next[23] <= (((((((((((((link_litesatalinktx_crc_new[15] ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]); + link_litesatalinktx_crc_next[24] <= ((((((((((((link_litesatalinktx_crc_new[16] ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[17]); + link_litesatalinktx_crc_next[25] <= ((((((((((((link_litesatalinktx_crc_new[17] ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[18]); + link_litesatalinktx_crc_next[26] <= ((((((((((((((link_litesatalinktx_crc_new[18] ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[31]); + link_litesatalinktx_crc_next[27] <= (((((((((((((link_litesatalinktx_crc_new[19] ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[7]); + link_litesatalinktx_crc_next[28] <= (((((((((((((link_litesatalinktx_crc_new[20] ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[12]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[8]); + link_litesatalinktx_crc_next[29] <= (((((((((((((link_litesatalinktx_crc_new[21] ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[9]); + link_litesatalinktx_crc_next[30] <= ((((((((((((link_litesatalinktx_crc_new[22] ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[10]); + link_litesatalinktx_crc_next[31] <= ((((((((((((link_litesatalinktx_crc_new[23] ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[11]); +end +always @(*) begin + link_litesatalinktx_crc_data0 <= 32'd0; + link_litesatalinktx_crc_sink_ready <= 1'd0; + link_litesatalinktx_crc_is_ongoing <= 1'd0; + subfragments_litesatalinktx_litesatacrcinserter_next_state <= 2'd0; + link_litesatalinktx_crc_source_valid <= 1'd0; + link_litesatalinktx_crc_source_first <= 1'd0; + link_litesatalinktx_crc_source_last <= 1'd0; + link_litesatalinktx_crc_source_payload_data <= 32'd0; + link_litesatalinktx_crc_ce <= 1'd0; + link_litesatalinktx_crc_source_payload_error <= 1'd0; + link_litesatalinktx_crc_reset <= 1'd0; + subfragments_litesatalinktx_litesatacrcinserter_next_state <= subfragments_litesatalinktx_litesatacrcinserter_state; + case (subfragments_litesatalinktx_litesatacrcinserter_state) + 1'd1: begin + link_litesatalinktx_crc_ce <= (link_litesatalinktx_crc_sink_valid & link_litesatalinktx_crc_source_ready); + link_litesatalinktx_crc_data0 <= link_litesatalinktx_crc_sink_payload_data; + link_litesatalinktx_crc_source_valid <= link_litesatalinktx_crc_sink_valid; + link_litesatalinktx_crc_sink_ready <= link_litesatalinktx_crc_source_ready; + link_litesatalinktx_crc_source_first <= link_litesatalinktx_crc_sink_first; + link_litesatalinktx_crc_source_last <= link_litesatalinktx_crc_sink_last; + link_litesatalinktx_crc_source_payload_data <= link_litesatalinktx_crc_sink_payload_data; + link_litesatalinktx_crc_source_payload_error <= link_litesatalinktx_crc_sink_payload_error; + link_litesatalinktx_crc_source_last <= 1'd0; + if (((link_litesatalinktx_crc_sink_valid & link_litesatalinktx_crc_sink_last) & link_litesatalinktx_crc_source_ready)) begin + subfragments_litesatalinktx_litesatacrcinserter_next_state <= 2'd2; + end + end + 2'd2: begin + link_litesatalinktx_crc_source_valid <= 1'd1; + link_litesatalinktx_crc_source_last <= 1'd1; + link_litesatalinktx_crc_source_payload_data <= link_litesatalinktx_crc_value; + if (link_litesatalinktx_crc_source_ready) begin + subfragments_litesatalinktx_litesatacrcinserter_next_state <= 1'd0; + end + end + default: begin + link_litesatalinktx_crc_reset <= 1'd1; + link_litesatalinktx_crc_sink_ready <= 1'd1; + if (link_litesatalinktx_crc_sink_valid) begin + link_litesatalinktx_crc_sink_ready <= 1'd0; + subfragments_litesatalinktx_litesatacrcinserter_next_state <= 1'd1; + end + link_litesatalinktx_crc_is_ongoing <= 1'd1; + end + endcase +end +assign link_litesatalinktx_scrambler_ce = (link_litesatalinktx_scrambler_sink_valid & link_litesatalinktx_scrambler_sink_ready); +assign link_litesatalinktx_scrambler_source_valid = link_litesatalinktx_scrambler_sink_valid; +assign link_litesatalinktx_scrambler_sink_ready = link_litesatalinktx_scrambler_source_ready; +assign link_litesatalinktx_scrambler_source_first = link_litesatalinktx_scrambler_sink_first; +assign link_litesatalinktx_scrambler_source_last = link_litesatalinktx_scrambler_sink_last; +assign link_litesatalinktx_scrambler_source_payload_error = link_litesatalinktx_scrambler_sink_payload_error; +always @(*) begin + link_litesatalinktx_scrambler_source_payload_data <= 32'd0; + link_litesatalinktx_scrambler_source_payload_data <= link_litesatalinktx_scrambler_sink_payload_data; + link_litesatalinktx_scrambler_source_payload_data <= (link_litesatalinktx_scrambler_sink_payload_data ^ link_litesatalinktx_scrambler_value); +end +always @(*) begin + link_litesatalinktx_scrambler_next_value <= 32'd0; + link_litesatalinktx_scrambler_next_value[0] <= (((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[1] <= ((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[2] <= (((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[3] <= (((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); + link_litesatalinktx_scrambler_next_value[4] <= ((((((link_litesatalinktx_scrambler_context[13] ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[5] <= ((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[1]); + link_litesatalinktx_scrambler_next_value[6] <= ((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]); + link_litesatalinktx_scrambler_next_value[7] <= (((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[8] <= ((((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[9] <= (((((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[10] <= (((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); + link_litesatalinktx_scrambler_next_value[11] <= ((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[12] <= (((((((link_litesatalinktx_scrambler_context[13] ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[13] <= (((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); + link_litesatalinktx_scrambler_next_value[14] <= (((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]); + link_litesatalinktx_scrambler_next_value[15] <= ((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[16] <= (((link_litesatalinktx_scrambler_context[11] ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[17] <= (((link_litesatalinktx_scrambler_context[12] ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); + link_litesatalinktx_scrambler_next_value[18] <= (((link_litesatalinktx_scrambler_context[13] ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]); + link_litesatalinktx_scrambler_next_value[19] <= (((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[3]); + link_litesatalinktx_scrambler_next_value[20] <= (((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]); + link_litesatalinktx_scrambler_next_value[21] <= ((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[22] <= (((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[23] <= ((((((((link_litesatalinktx_scrambler_context[13] ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[24] <= ((((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); + link_litesatalinktx_scrambler_next_value[25] <= ((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]); + link_litesatalinktx_scrambler_next_value[26] <= (((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[27] <= ((((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[28] <= (((((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[29] <= (((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); + link_litesatalinktx_scrambler_next_value[30] <= ((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[0]); + link_litesatalinktx_scrambler_next_value[31] <= (((((link_litesatalinktx_scrambler_context[12] ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); +end +assign link_litesatalinktx_scrambler_value = link_litesatalinktx_scrambler_next_value; +assign link_litesatalinktx_crc_sink_valid = link_litesatalinktx_sink_sink_valid; +assign link_litesatalinktx_sink_sink_ready = link_litesatalinktx_crc_sink_ready; +assign link_litesatalinktx_crc_sink_first = link_litesatalinktx_sink_sink_first; +assign link_litesatalinktx_crc_sink_last = link_litesatalinktx_sink_sink_last; +assign link_litesatalinktx_crc_sink_payload_data = link_litesatalinktx_sink_sink_payload_data; +assign link_litesatalinktx_crc_sink_payload_error = link_litesatalinktx_sink_sink_payload_error; +assign link_litesatalinktx_scrambler_sink_valid = link_litesatalinktx_crc_source_valid; +assign link_litesatalinktx_crc_source_ready = link_litesatalinktx_scrambler_sink_ready; +assign link_litesatalinktx_scrambler_sink_first = link_litesatalinktx_crc_source_first; +assign link_litesatalinktx_scrambler_sink_last = link_litesatalinktx_crc_source_last; +assign link_litesatalinktx_scrambler_sink_payload_data = link_litesatalinktx_crc_source_payload_data; +assign link_litesatalinktx_scrambler_sink_payload_error = link_litesatalinktx_crc_source_payload_error; +always @(*) begin + link_litesatalinktx_insert <= 32'd0; + link_litesatalinktx_copy <= 1'd0; + link_litesatalinktx_fsm_is_ongoing0 <= 1'd0; + link_litesatalinktx_fsm_is_ongoing1 <= 1'd0; + subfragments_litesatalinktx_fsm_next_state <= 3'd0; + link_litesatalinktx_scrambler_reset <= 1'd0; + subfragments_litesatalinktx_fsm_next_state <= subfragments_litesatalinktx_fsm_state; + case (subfragments_litesatalinktx_fsm_state) + 1'd1: begin + link_litesatalinktx_insert <= 31'd1465365884; + if ((~link_litesatalinktx_from_rx_payload_idle)) begin + subfragments_litesatalinktx_fsm_next_state <= 1'd0; + end else begin + if ((link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive == 31'd1246401916))) begin + subfragments_litesatalinktx_fsm_next_state <= 2'd2; + end + end + link_litesatalinktx_fsm_is_ongoing1 <= 1'd1; + end + 2'd2: begin + link_litesatalinktx_insert <= 30'd926397820; + if (link_litesatalinktx_source_source_ready) begin + subfragments_litesatalinktx_fsm_next_state <= 2'd3; + end + end + 2'd3: begin + link_litesatalinktx_copy <= 1'd1; + if (((link_litesatalinktx_scrambler_source_valid & link_litesatalinktx_scrambler_source_last) & link_litesatalinktx_scrambler_source_ready)) begin + subfragments_litesatalinktx_fsm_next_state <= 3'd5; + end else begin + if ((link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive == 32'd3587549820))) begin + subfragments_litesatalinktx_fsm_next_state <= 3'd4; + end + end + end + 3'd4: begin + link_litesatalinktx_insert <= 32'd2509613692; + if ((link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive != 32'd3587549820))) begin + subfragments_litesatalinktx_fsm_next_state <= 2'd3; + end else begin + if (link_litesatalinktx_error) begin + subfragments_litesatalinktx_fsm_next_state <= 1'd0; + end + end + end + 3'd5: begin + link_litesatalinktx_insert <= 32'd3587552636; + if (link_litesatalinktx_source_source_ready) begin + subfragments_litesatalinktx_fsm_next_state <= 3'd6; + end + end + 3'd6: begin + link_litesatalinktx_insert <= 31'd1482208636; + if (link_litesatalinktx_from_rx_payload_primitive_valid) begin + if ((link_litesatalinktx_from_rx_payload_primitive == 30'd892712316)) begin + subfragments_litesatalinktx_fsm_next_state <= 1'd0; + end else begin + if ((link_litesatalinktx_from_rx_payload_primitive == 31'd1448523132)) begin + subfragments_litesatalinktx_fsm_next_state <= 1'd0; + end + end + end else begin + if (link_litesatalinktx_error) begin + subfragments_litesatalinktx_fsm_next_state <= 1'd0; + end + end + end + default: begin + link_litesatalinktx_scrambler_reset <= 1'd1; + if (link_litesatalinktx_from_rx_payload_idle) begin + link_litesatalinktx_insert <= 32'd3048576380; + if (link_litesatalinktx_scrambler_source_valid) begin + if ((link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive == 32'd3048576380))) begin + subfragments_litesatalinktx_fsm_next_state <= 1'd1; + end + end + end + link_litesatalinktx_fsm_is_ongoing0 <= 1'd1; + end + endcase +end +assign link_tx_sink_ready = ((~link_tx_source_valid) | link_tx_source_ready); +assign link_tx_align_send = (link_tx_align_cnt < 2'd2); +always @(*) begin + link_tx_align_sink_ready <= 1'd0; + link_tx_align_source_valid <= 1'd0; + link_tx_align_source_payload_charisk <= 4'd0; + link_tx_align_source_payload_data <= 32'd0; + if (link_tx_align_send) begin + link_tx_align_source_valid <= 1'd1; + link_tx_align_source_payload_charisk <= 1'd1; + link_tx_align_source_payload_data <= 31'd2068466364; + link_tx_align_sink_ready <= 1'd0; + end else begin + link_tx_align_source_valid <= link_tx_align_sink_valid; + link_tx_align_source_payload_data <= link_tx_align_sink_payload_data; + link_tx_align_source_payload_charisk <= link_tx_align_sink_payload_charisk; + link_tx_align_sink_ready <= link_tx_align_source_ready; + end +end +assign link_tx_align_sink_valid = link_tx_source_valid; +assign link_tx_source_ready = link_tx_align_sink_ready; +assign link_tx_align_sink_first = link_tx_source_first; +assign link_tx_align_sink_last = link_tx_source_last; +assign link_tx_align_sink_payload_data = link_tx_source_payload_data; +assign link_tx_align_sink_payload_charisk = link_tx_source_payload_charisk; +assign datapath_sink_sink_valid = link_tx_align_source_valid; +assign link_tx_align_source_ready = datapath_sink_sink_ready; +assign datapath_sink_sink_first = link_tx_align_source_first; +assign datapath_sink_sink_last = link_tx_align_source_last; +assign datapath_sink_sink_payload_data = link_tx_align_source_payload_data; +assign datapath_sink_sink_payload_charisk = link_tx_align_source_payload_charisk; +always @(*) begin + link_rx_align_source_valid <= 1'd0; + link_rx_align_source_first <= 1'd0; + link_rx_align_source_last <= 1'd0; + link_rx_align_sink_ready <= 1'd0; + link_rx_align_source_payload_data <= 32'd0; + link_rx_align_source_payload_charisk <= 4'd0; + if (((link_rx_align_sink_valid & (link_rx_align_sink_payload_charisk == 1'd1)) & (link_rx_align_sink_payload_data == 31'd2068466364))) begin + link_rx_align_sink_ready <= 1'd1; + end else begin + link_rx_align_source_valid <= link_rx_align_sink_valid; + link_rx_align_sink_ready <= link_rx_align_source_ready; + link_rx_align_source_first <= link_rx_align_sink_first; + link_rx_align_source_last <= link_rx_align_sink_last; + link_rx_align_source_payload_data <= link_rx_align_sink_payload_data; + link_rx_align_source_payload_charisk <= link_rx_align_sink_payload_charisk; + end +end +assign link_rx_cont_is_data = (link_rx_cont_sink_payload_charisk == 1'd0); +assign link_rx_cont_is_cont = ((~link_rx_cont_is_data) & (link_rx_cont_sink_payload_data == 32'd2576984700)); +assign link_rx_cont_cont_ongoing = (link_rx_cont_is_cont | (link_rx_cont_in_cont & link_rx_cont_is_data)); +assign link_rx_cont_source_valid = link_rx_cont_sink_valid; +assign link_rx_cont_sink_ready = link_rx_cont_source_ready; +assign link_rx_cont_source_first = link_rx_cont_sink_first; +assign link_rx_cont_source_last = link_rx_cont_sink_last; +always @(*) begin + link_rx_cont_source_payload_charisk <= 4'd0; + link_rx_cont_source_payload_data <= 32'd0; + link_rx_cont_source_payload_data <= link_rx_cont_sink_payload_data; + link_rx_cont_source_payload_charisk <= link_rx_cont_sink_payload_charisk; + if (link_rx_cont_cont_ongoing) begin + link_rx_cont_source_payload_charisk <= 1'd1; + link_rx_cont_source_payload_data <= link_rx_cont_last_primitive; + end +end +assign link_litesatalinkrx_sink_sink_ready = 1'd1; +always @(*) begin + link_litesatalinkrx_data_valid <= 1'd0; + link_litesatalinkrx_primitive_valid <= 1'd0; + if (link_litesatalinkrx_sink_sink_valid) begin + link_litesatalinkrx_data_valid <= (link_litesatalinkrx_sink_sink_payload_charisk == 1'd0); + link_litesatalinkrx_primitive_valid <= (link_litesatalinkrx_sink_sink_payload_charisk == 1'd1); + end +end +assign link_litesatalinkrx_primitive = link_litesatalinkrx_sink_sink_payload_data; +assign link_litesatalinkrx_to_tx_payload_idle = link_litesatalinkrx_fsm_is_ongoing; +assign link_litesatalinkrx_to_tx_payload_insert = link_litesatalinkrx_insert; +assign link_litesatalinkrx_to_tx_payload_primitive_valid = link_litesatalinkrx_primitive_valid; +assign link_litesatalinkrx_to_tx_payload_primitive = link_litesatalinkrx_primitive; +assign link_litesatalinkrx_sink_sink_valid = link_rx_source_valid; +assign link_rx_source_ready = link_litesatalinkrx_sink_sink_ready; +assign link_litesatalinkrx_sink_sink_first = link_rx_source_first; +assign link_litesatalinkrx_sink_sink_last = link_rx_source_last; +assign link_litesatalinkrx_sink_sink_payload_data = link_rx_source_payload_data; +assign link_litesatalinkrx_sink_sink_payload_charisk = link_rx_source_payload_charisk; +assign link_litesatalinkrx_descrambler_ce = (link_litesatalinkrx_descrambler_sink_valid & link_litesatalinkrx_descrambler_sink_ready); +assign link_litesatalinkrx_descrambler_source_valid = link_litesatalinkrx_descrambler_sink_valid; +assign link_litesatalinkrx_descrambler_sink_ready = link_litesatalinkrx_descrambler_source_ready; +assign link_litesatalinkrx_descrambler_source_first = link_litesatalinkrx_descrambler_sink_first; +assign link_litesatalinkrx_descrambler_source_last = link_litesatalinkrx_descrambler_sink_last; +assign link_litesatalinkrx_descrambler_source_payload_error = link_litesatalinkrx_descrambler_sink_payload_error; +always @(*) begin + link_litesatalinkrx_descrambler_source_payload_data <= 32'd0; + link_litesatalinkrx_descrambler_source_payload_data <= link_litesatalinkrx_descrambler_sink_payload_data; + link_litesatalinkrx_descrambler_source_payload_data <= (link_litesatalinkrx_descrambler_sink_payload_data ^ link_litesatalinkrx_descrambler_value); +end +always @(*) begin + link_litesatalinkrx_descrambler_next_value <= 32'd0; + link_litesatalinkrx_descrambler_next_value[0] <= (((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[1] <= ((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[2] <= (((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[3] <= (((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); + link_litesatalinkrx_descrambler_next_value[4] <= ((((((link_litesatalinkrx_descrambler_context[13] ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[5] <= ((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[1]); + link_litesatalinkrx_descrambler_next_value[6] <= ((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]); + link_litesatalinkrx_descrambler_next_value[7] <= (((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[8] <= ((((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[9] <= (((((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[10] <= (((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); + link_litesatalinkrx_descrambler_next_value[11] <= ((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[12] <= (((((((link_litesatalinkrx_descrambler_context[13] ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[13] <= (((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); + link_litesatalinkrx_descrambler_next_value[14] <= (((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]); + link_litesatalinkrx_descrambler_next_value[15] <= ((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[16] <= (((link_litesatalinkrx_descrambler_context[11] ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[17] <= (((link_litesatalinkrx_descrambler_context[12] ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); + link_litesatalinkrx_descrambler_next_value[18] <= (((link_litesatalinkrx_descrambler_context[13] ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]); + link_litesatalinkrx_descrambler_next_value[19] <= (((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[3]); + link_litesatalinkrx_descrambler_next_value[20] <= (((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]); + link_litesatalinkrx_descrambler_next_value[21] <= ((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[22] <= (((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[23] <= ((((((((link_litesatalinkrx_descrambler_context[13] ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[24] <= ((((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); + link_litesatalinkrx_descrambler_next_value[25] <= ((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]); + link_litesatalinkrx_descrambler_next_value[26] <= (((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[27] <= ((((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[28] <= (((((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[29] <= (((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); + link_litesatalinkrx_descrambler_next_value[30] <= ((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[0]); + link_litesatalinkrx_descrambler_next_value[31] <= (((((link_litesatalinkrx_descrambler_context[12] ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); +end +assign link_litesatalinkrx_descrambler_value = link_litesatalinkrx_descrambler_next_value; +assign link_litesatalinkrx_crc_fifo_full = (link_litesatalinkrx_crc_syncfifo_level == 1'd1); +assign link_litesatalinkrx_crc_fifo_in = (link_litesatalinkrx_crc_sink_sink_valid & ((~link_litesatalinkrx_crc_fifo_full) | link_litesatalinkrx_crc_fifo_out)); +assign link_litesatalinkrx_crc_fifo_out = (link_litesatalinkrx_crc_source_source_valid & link_litesatalinkrx_crc_source_source_ready); +assign link_litesatalinkrx_crc_syncfifo_sink_first = link_litesatalinkrx_crc_sink_sink_first; +assign link_litesatalinkrx_crc_syncfifo_sink_last = link_litesatalinkrx_crc_sink_sink_last; +assign link_litesatalinkrx_crc_syncfifo_sink_payload_data = link_litesatalinkrx_crc_sink_sink_payload_data; +assign link_litesatalinkrx_crc_syncfifo_sink_payload_error = link_litesatalinkrx_crc_sink_sink_payload_error; +always @(*) begin + link_litesatalinkrx_crc_syncfifo_sink_valid <= 1'd0; + link_litesatalinkrx_crc_syncfifo_sink_valid <= link_litesatalinkrx_crc_sink_sink_valid; + link_litesatalinkrx_crc_syncfifo_sink_valid <= link_litesatalinkrx_crc_fifo_in; +end +always @(*) begin + link_litesatalinkrx_crc_sink_sink_ready <= 1'd0; + link_litesatalinkrx_crc_sink_sink_ready <= link_litesatalinkrx_crc_syncfifo_sink_ready; + link_litesatalinkrx_crc_sink_sink_ready <= link_litesatalinkrx_crc_fifo_in; +end +assign link_litesatalinkrx_crc_source_source_valid = (link_litesatalinkrx_crc_sink_sink_valid & link_litesatalinkrx_crc_fifo_full); +assign link_litesatalinkrx_crc_source_source_last = link_litesatalinkrx_crc_sink_sink_last; +assign link_litesatalinkrx_crc_syncfifo_source_ready = link_litesatalinkrx_crc_fifo_out; +assign link_litesatalinkrx_crc_source_source_payload_data = link_litesatalinkrx_crc_syncfifo_source_payload_data; +always @(*) begin + link_litesatalinkrx_crc_source_source_payload_error <= 1'd0; + link_litesatalinkrx_crc_source_source_payload_error <= link_litesatalinkrx_crc_syncfifo_source_payload_error; + link_litesatalinkrx_crc_source_source_payload_error <= (link_litesatalinkrx_crc_sink_sink_payload_error | (link_litesatalinkrx_crc_crc_error & link_litesatalinkrx_crc_source_source_last)); +end +assign link_litesatalinkrx_crc_busy = (~link_litesatalinkrx_crc_is_ongoing); +assign link_litesatalinkrx_crc_crc_data1 = link_litesatalinkrx_crc_crc_data0; +assign link_litesatalinkrx_crc_crc_last = link_litesatalinkrx_crc_crc_reg_i; +assign link_litesatalinkrx_crc_crc_value = link_litesatalinkrx_crc_crc_reg_i; +assign link_litesatalinkrx_crc_crc_error = (link_litesatalinkrx_crc_crc_next != 1'd0); +assign link_litesatalinkrx_crc_crc_new = (link_litesatalinkrx_crc_crc_last ^ link_litesatalinkrx_crc_crc_data1); +always @(*) begin + link_litesatalinkrx_crc_crc_next <= 32'd0; + link_litesatalinkrx_crc_crc_next[0] <= ((((((((((((link_litesatalinkrx_crc_crc_new[0] ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); + link_litesatalinkrx_crc_crc_next[1] <= ((((((((((((link_litesatalinkrx_crc_crc_new[1] ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[12]); + link_litesatalinkrx_crc_crc_next[2] <= (((((((((((((((link_litesatalinkrx_crc_crc_new[2] ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]); + link_litesatalinkrx_crc_crc_next[3] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[3] ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[17]); + link_litesatalinkrx_crc_crc_next[4] <= ((((((((((((((((link_litesatalinkrx_crc_crc_new[4] ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); + link_litesatalinkrx_crc_crc_next[5] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[5] ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[6]); + link_litesatalinkrx_crc_crc_next[6] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[6] ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[7]); + link_litesatalinkrx_crc_crc_next[7] <= (((((((((((((((link_litesatalinkrx_crc_crc_new[7] ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[16]); + link_litesatalinkrx_crc_crc_next[8] <= ((((((((((((link_litesatalinkrx_crc_crc_new[8] ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); + link_litesatalinkrx_crc_crc_next[9] <= (((((((((((link_litesatalinkrx_crc_crc_new[9] ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[12]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[13]); + link_litesatalinkrx_crc_crc_next[10] <= ((((((((((((link_litesatalinkrx_crc_crc_new[5] ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]); + link_litesatalinkrx_crc_crc_next[11] <= ((((((((((((((((link_litesatalinkrx_crc_crc_new[4] ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); + link_litesatalinkrx_crc_crc_next[12] <= ((((((((((((((((link_litesatalinkrx_crc_crc_new[5] ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); + link_litesatalinkrx_crc_crc_next[13] <= (((((((((((((((link_litesatalinkrx_crc_crc_new[6] ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[13]); + link_litesatalinkrx_crc_crc_next[14] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[7] ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[14]); + link_litesatalinkrx_crc_crc_next[15] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[8] ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[12]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[15]); + link_litesatalinkrx_crc_crc_next[16] <= (((((((((((((link_litesatalinkrx_crc_crc_new[19] ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[12]); + link_litesatalinkrx_crc_crc_next[17] <= (((((((((((((link_litesatalinkrx_crc_crc_new[20] ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[13]); + link_litesatalinkrx_crc_crc_next[18] <= ((((((((((((link_litesatalinkrx_crc_crc_new[21] ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[14]); + link_litesatalinkrx_crc_crc_next[19] <= (((((((((((link_litesatalinkrx_crc_crc_new[22] ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[15]); + link_litesatalinkrx_crc_crc_next[20] <= (((((((((((link_litesatalinkrx_crc_crc_new[23] ^ link_litesatalinkrx_crc_crc_new[12]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[16]); + link_litesatalinkrx_crc_crc_next[21] <= (((((((((((link_litesatalinkrx_crc_crc_new[24] ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[17]); + link_litesatalinkrx_crc_crc_next[22] <= (((((((((((((link_litesatalinkrx_crc_crc_new[14] ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); + link_litesatalinkrx_crc_crc_next[23] <= (((((((((((((link_litesatalinkrx_crc_crc_new[15] ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]); + link_litesatalinkrx_crc_crc_next[24] <= ((((((((((((link_litesatalinkrx_crc_crc_new[16] ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[17]); + link_litesatalinkrx_crc_crc_next[25] <= ((((((((((((link_litesatalinkrx_crc_crc_new[17] ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[18]); + link_litesatalinkrx_crc_crc_next[26] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[18] ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[31]); + link_litesatalinkrx_crc_crc_next[27] <= (((((((((((((link_litesatalinkrx_crc_crc_new[19] ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[7]); + link_litesatalinkrx_crc_crc_next[28] <= (((((((((((((link_litesatalinkrx_crc_crc_new[20] ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[12]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[8]); + link_litesatalinkrx_crc_crc_next[29] <= (((((((((((((link_litesatalinkrx_crc_crc_new[21] ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[9]); + link_litesatalinkrx_crc_crc_next[30] <= ((((((((((((link_litesatalinkrx_crc_crc_new[22] ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[10]); + link_litesatalinkrx_crc_crc_next[31] <= ((((((((((((link_litesatalinkrx_crc_crc_new[23] ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[11]); +end +assign link_litesatalinkrx_crc_syncfifo_syncfifo_din = {link_litesatalinkrx_crc_syncfifo_fifo_in_last, link_litesatalinkrx_crc_syncfifo_fifo_in_first, link_litesatalinkrx_crc_syncfifo_fifo_in_payload_error, link_litesatalinkrx_crc_syncfifo_fifo_in_payload_data}; +assign {link_litesatalinkrx_crc_syncfifo_fifo_out_last, link_litesatalinkrx_crc_syncfifo_fifo_out_first, link_litesatalinkrx_crc_syncfifo_fifo_out_payload_error, link_litesatalinkrx_crc_syncfifo_fifo_out_payload_data} = link_litesatalinkrx_crc_syncfifo_syncfifo_dout; +assign link_litesatalinkrx_crc_syncfifo_sink_ready = link_litesatalinkrx_crc_syncfifo_syncfifo_writable; +assign link_litesatalinkrx_crc_syncfifo_syncfifo_we = link_litesatalinkrx_crc_syncfifo_sink_valid; +assign link_litesatalinkrx_crc_syncfifo_fifo_in_first = link_litesatalinkrx_crc_syncfifo_sink_first; +assign link_litesatalinkrx_crc_syncfifo_fifo_in_last = link_litesatalinkrx_crc_syncfifo_sink_last; +assign link_litesatalinkrx_crc_syncfifo_fifo_in_payload_data = link_litesatalinkrx_crc_syncfifo_sink_payload_data; +assign link_litesatalinkrx_crc_syncfifo_fifo_in_payload_error = link_litesatalinkrx_crc_syncfifo_sink_payload_error; +assign link_litesatalinkrx_crc_syncfifo_source_valid = link_litesatalinkrx_crc_syncfifo_syncfifo_readable; +assign link_litesatalinkrx_crc_syncfifo_source_first = link_litesatalinkrx_crc_syncfifo_fifo_out_first; +assign link_litesatalinkrx_crc_syncfifo_source_last = link_litesatalinkrx_crc_syncfifo_fifo_out_last; +assign link_litesatalinkrx_crc_syncfifo_source_payload_data = link_litesatalinkrx_crc_syncfifo_fifo_out_payload_data; +assign link_litesatalinkrx_crc_syncfifo_source_payload_error = link_litesatalinkrx_crc_syncfifo_fifo_out_payload_error; +assign link_litesatalinkrx_crc_syncfifo_syncfifo_re = link_litesatalinkrx_crc_syncfifo_source_ready; +always @(*) begin + link_litesatalinkrx_crc_syncfifo_wrport_adr <= 1'd0; + if (link_litesatalinkrx_crc_syncfifo_replace) begin + link_litesatalinkrx_crc_syncfifo_wrport_adr <= (link_litesatalinkrx_crc_syncfifo_produce - 1'd1); + end else begin + link_litesatalinkrx_crc_syncfifo_wrport_adr <= link_litesatalinkrx_crc_syncfifo_produce; + end +end +assign link_litesatalinkrx_crc_syncfifo_wrport_dat_w = link_litesatalinkrx_crc_syncfifo_syncfifo_din; +assign link_litesatalinkrx_crc_syncfifo_wrport_we = (link_litesatalinkrx_crc_syncfifo_syncfifo_we & (link_litesatalinkrx_crc_syncfifo_syncfifo_writable | link_litesatalinkrx_crc_syncfifo_replace)); +assign link_litesatalinkrx_crc_syncfifo_do_read = (link_litesatalinkrx_crc_syncfifo_syncfifo_readable & link_litesatalinkrx_crc_syncfifo_syncfifo_re); +assign link_litesatalinkrx_crc_syncfifo_rdport_adr = link_litesatalinkrx_crc_syncfifo_consume; +assign link_litesatalinkrx_crc_syncfifo_syncfifo_dout = link_litesatalinkrx_crc_syncfifo_rdport_dat_r; +assign link_litesatalinkrx_crc_syncfifo_syncfifo_writable = (link_litesatalinkrx_crc_syncfifo_level != 2'd2); +assign link_litesatalinkrx_crc_syncfifo_syncfifo_readable = (link_litesatalinkrx_crc_syncfifo_level != 1'd0); +always @(*) begin + link_litesatalinkrx_crc_fifo_reset <= 1'd0; + link_litesatalinkrx_crc_crc_ce <= 1'd0; + subfragments_litesatalinkrx_litesatacrcchecker_next_state <= 2'd0; + link_litesatalinkrx_crc_crc_reset <= 1'd0; + link_litesatalinkrx_crc_crc_data0 <= 32'd0; + link_litesatalinkrx_crc_is_ongoing <= 1'd0; + subfragments_litesatalinkrx_litesatacrcchecker_next_state <= subfragments_litesatalinkrx_litesatacrcchecker_state; + case (subfragments_litesatalinkrx_litesatacrcchecker_state) + 1'd1: begin + link_litesatalinkrx_crc_crc_data0 <= link_litesatalinkrx_crc_sink_sink_payload_data; + if ((link_litesatalinkrx_crc_sink_sink_valid & link_litesatalinkrx_crc_sink_sink_ready)) begin + link_litesatalinkrx_crc_crc_ce <= 1'd1; + subfragments_litesatalinkrx_litesatacrcchecker_next_state <= 2'd2; + end + link_litesatalinkrx_crc_is_ongoing <= 1'd1; + end + 2'd2: begin + link_litesatalinkrx_crc_crc_data0 <= link_litesatalinkrx_crc_sink_sink_payload_data; + if ((link_litesatalinkrx_crc_sink_sink_valid & link_litesatalinkrx_crc_sink_sink_ready)) begin + link_litesatalinkrx_crc_crc_ce <= 1'd1; + if (link_litesatalinkrx_crc_sink_sink_last) begin + subfragments_litesatalinkrx_litesatacrcchecker_next_state <= 1'd0; + end + end + end + default: begin + link_litesatalinkrx_crc_crc_reset <= 1'd1; + link_litesatalinkrx_crc_fifo_reset <= 1'd1; + subfragments_litesatalinkrx_litesatacrcchecker_next_state <= 1'd1; + end + endcase +end +assign link_litesatalinkrx_crc_sink_sink_valid = link_litesatalinkrx_descrambler_source_valid; +assign link_litesatalinkrx_descrambler_source_ready = link_litesatalinkrx_crc_sink_sink_ready; +assign link_litesatalinkrx_crc_sink_sink_first = link_litesatalinkrx_descrambler_source_first; +assign link_litesatalinkrx_crc_sink_sink_last = link_litesatalinkrx_descrambler_source_last; +assign link_litesatalinkrx_crc_sink_sink_payload_data = link_litesatalinkrx_descrambler_source_payload_data; +assign link_litesatalinkrx_crc_sink_sink_payload_error = link_litesatalinkrx_descrambler_source_payload_error; +assign link_litesatalinkrx_source_source_valid = link_litesatalinkrx_crc_source_source_valid; +assign link_litesatalinkrx_crc_source_source_ready = link_litesatalinkrx_source_source_ready; +assign link_litesatalinkrx_source_source_first = link_litesatalinkrx_crc_source_source_first; +assign link_litesatalinkrx_source_source_last = link_litesatalinkrx_crc_source_source_last; +assign link_litesatalinkrx_source_source_payload_data = link_litesatalinkrx_crc_source_source_payload_data; +assign link_litesatalinkrx_source_source_payload_error = link_litesatalinkrx_crc_source_source_payload_error; +always @(*) begin + link_litesatalinkrx_insert <= 32'd0; + link_litesatalinkrx_descrambler_sink_last <= 1'd0; + link_litesatalinkrx_fsm_is_ongoing <= 1'd0; + subfragments_litesatalinkrx_fsm_next_state <= 3'd0; + link_litesatalinkrx_descrambler_sink_valid <= 1'd0; + link_litesatalinkrx_descrambler_reset <= 1'd0; + subfragments_litesatalinkrx_fsm_next_state <= subfragments_litesatalinkrx_fsm_state; + case (subfragments_litesatalinkrx_fsm_state) + 1'd1: begin + link_litesatalinkrx_insert <= 31'd1246401916; + if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 30'd926397820))) begin + subfragments_litesatalinkrx_fsm_next_state <= 2'd2; + end + end + 2'd2: begin + link_litesatalinkrx_insert <= 31'd1431680380; + if (link_litesatalinkrx_data_valid) begin + subfragments_litesatalinkrx_fsm_next_state <= 2'd3; + end + end + 2'd3: begin + link_litesatalinkrx_descrambler_sink_valid <= link_litesatalinkrx_data_valid; + link_litesatalinkrx_insert <= 31'd1431680380; + if (link_litesatalinkrx_primitive_valid) begin + if ((link_litesatalinkrx_primitive == 32'd3587549820)) begin + link_litesatalinkrx_insert <= 32'd2509613692; + end else begin + if ((link_litesatalinkrx_primitive == 32'd3587552636)) begin + link_litesatalinkrx_descrambler_sink_valid <= 1'd1; + link_litesatalinkrx_descrambler_sink_last <= 1'd1; + subfragments_litesatalinkrx_fsm_next_state <= 3'd5; + end + end + end else begin + if (link_litesatalinkrx_hold) begin + link_litesatalinkrx_insert <= 32'd3587549820; + end + end + end + 3'd4: begin + link_litesatalinkrx_insert <= 31'd1431680380; + if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 31'd1482208636))) begin + subfragments_litesatalinkrx_fsm_next_state <= 3'd5; + end + end + 3'd5: begin + link_litesatalinkrx_insert <= 31'd1431680380; + if ((~link_litesatalinkrx_crc_error)) begin + subfragments_litesatalinkrx_fsm_next_state <= 3'd6; + end else begin + subfragments_litesatalinkrx_fsm_next_state <= 3'd7; + end + end + 3'd6: begin + link_litesatalinkrx_insert <= 30'd892712316; + if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 32'd3048576380))) begin + subfragments_litesatalinkrx_fsm_next_state <= 1'd0; + end + end + 3'd7: begin + link_litesatalinkrx_insert <= 31'd1448523132; + if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 32'd3048576380))) begin + subfragments_litesatalinkrx_fsm_next_state <= 1'd0; + end + end + default: begin + link_litesatalinkrx_descrambler_reset <= 1'd1; + if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 31'd1465365884))) begin + subfragments_litesatalinkrx_fsm_next_state <= 1'd1; + end + link_litesatalinkrx_fsm_is_ongoing <= 1'd1; + end + endcase +end +assign link_rx_sink_ready = ((~link_rx_source_valid) | link_rx_source_ready); +assign link_rx_buffer_syncfifo_din = {link_rx_buffer_fifo_in_last, link_rx_buffer_fifo_in_first, link_rx_buffer_fifo_in_payload_error, link_rx_buffer_fifo_in_payload_data}; +assign {link_rx_buffer_fifo_out_last, link_rx_buffer_fifo_out_first, link_rx_buffer_fifo_out_payload_error, link_rx_buffer_fifo_out_payload_data} = link_rx_buffer_syncfifo_dout; +assign link_rx_buffer_sink_ready = link_rx_buffer_syncfifo_writable; +assign link_rx_buffer_syncfifo_we = link_rx_buffer_sink_valid; +assign link_rx_buffer_fifo_in_first = link_rx_buffer_sink_first; +assign link_rx_buffer_fifo_in_last = link_rx_buffer_sink_last; +assign link_rx_buffer_fifo_in_payload_data = link_rx_buffer_sink_payload_data; +assign link_rx_buffer_fifo_in_payload_error = link_rx_buffer_sink_payload_error; +assign link_rx_buffer_source_valid = link_rx_buffer_syncfifo_readable; +assign link_rx_buffer_source_first = link_rx_buffer_fifo_out_first; +assign link_rx_buffer_source_last = link_rx_buffer_fifo_out_last; +assign link_rx_buffer_source_payload_data = link_rx_buffer_fifo_out_payload_data; +assign link_rx_buffer_source_payload_error = link_rx_buffer_fifo_out_payload_error; +assign link_rx_buffer_syncfifo_re = link_rx_buffer_source_ready; +always @(*) begin + link_rx_buffer_wrport_adr <= 7'd0; + if (link_rx_buffer_replace) begin + link_rx_buffer_wrport_adr <= (link_rx_buffer_produce - 1'd1); + end else begin + link_rx_buffer_wrport_adr <= link_rx_buffer_produce; + end +end +assign link_rx_buffer_wrport_dat_w = link_rx_buffer_syncfifo_din; +assign link_rx_buffer_wrport_we = (link_rx_buffer_syncfifo_we & (link_rx_buffer_syncfifo_writable | link_rx_buffer_replace)); +assign link_rx_buffer_do_read = (link_rx_buffer_syncfifo_readable & link_rx_buffer_syncfifo_re); +assign link_rx_buffer_rdport_adr = link_rx_buffer_consume; +assign link_rx_buffer_syncfifo_dout = link_rx_buffer_rdport_dat_r; +assign link_rx_buffer_syncfifo_writable = (link_rx_buffer_level != 8'd128); +assign link_rx_buffer_syncfifo_readable = (link_rx_buffer_level != 1'd0); +assign link_rx_align_sink_valid = datapath_source_source_valid; +assign datapath_source_source_ready = link_rx_align_sink_ready; +assign link_rx_align_sink_first = datapath_source_source_first; +assign link_rx_align_sink_last = datapath_source_source_last; +assign link_rx_align_sink_payload_data = datapath_source_source_payload_data; +assign link_rx_align_sink_payload_charisk = datapath_source_source_payload_charisk; +assign link_rx_cont_sink_valid = link_rx_align_source_valid; +assign link_rx_align_source_ready = link_rx_cont_sink_ready; +assign link_rx_cont_sink_first = link_rx_align_source_first; +assign link_rx_cont_sink_last = link_rx_align_source_last; +assign link_rx_cont_sink_payload_data = link_rx_align_source_payload_data; +assign link_rx_cont_sink_payload_charisk = link_rx_align_source_payload_charisk; +assign link_rx_sink_valid = link_rx_cont_source_valid; +assign link_rx_cont_source_ready = link_rx_sink_ready; +assign link_rx_sink_first = link_rx_cont_source_first; +assign link_rx_sink_last = link_rx_cont_source_last; +assign link_rx_sink_payload_data = link_rx_cont_source_payload_data; +assign link_rx_sink_payload_charisk = link_rx_cont_source_payload_charisk; +assign link_rx_buffer_sink_valid = link_litesatalinkrx_source_source_valid; +assign link_litesatalinkrx_source_source_ready = link_rx_buffer_sink_ready; +assign link_rx_buffer_sink_first = link_litesatalinkrx_source_source_first; +assign link_rx_buffer_sink_last = link_litesatalinkrx_source_source_last; +assign link_rx_buffer_sink_payload_data = link_litesatalinkrx_source_source_payload_data; +assign link_rx_buffer_sink_payload_error = link_litesatalinkrx_source_source_payload_error; +assign transport_tx_counter_ce = (transport_tx_sink_valid & link_litesatalinktx_sink_sink_ready); +assign transport_tx_cmd_done = (((transport_tx_counter == transport_tx_cmd_len) & link_litesatalinktx_sink_sink_valid) & link_litesatalinktx_sink_sink_ready); +always @(*) begin + link_litesatalinktx_sink_sink_payload_data <= 32'd0; + link_litesatalinktx_sink_sink_last <= 1'd0; + link_litesatalinktx_sink_sink_valid <= 1'd0; + if (transport_tx_cmd_send) begin + link_litesatalinktx_sink_sink_valid <= transport_tx_sink_valid; + link_litesatalinktx_sink_sink_last <= ((transport_tx_counter == transport_tx_cmd_len) & (~transport_tx_cmd_with_data)); + case (transport_tx_counter) + 1'd0: begin + link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[31:0]; + end + 1'd1: begin + link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[63:32]; + end + 2'd2: begin + link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[95:64]; + end + 2'd3: begin + link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[127:96]; + end + 3'd4: begin + link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[159:128]; + end + endcase + end else begin + if (transport_tx_data_send) begin + link_litesatalinktx_sink_sink_valid <= transport_tx_sink_valid; + link_litesatalinktx_sink_sink_last <= transport_tx_sink_last; + link_litesatalinktx_sink_sink_payload_data <= transport_tx_sink_payload_data; + end + end +end +always @(*) begin + transport_tx_counter_reset <= 1'd0; + transport_tx_cmd_len <= 3'd0; + transport_tx_cmd_with_data <= 1'd0; + transport_tx_cmd_send <= 1'd0; + transport_tx_data_send <= 1'd0; + transport_tx_update_fis_type <= 1'd0; + subfragments_litesatatransporttx_next_state <= 2'd0; + transport_tx_encoded_cmd <= 160'd0; + transport_tx_sink_ready <= 1'd0; + subfragments_litesatatransporttx_next_state <= subfragments_litesatatransporttx_state; + case (subfragments_litesatatransporttx_state) + 1'd1: begin + transport_tx_encoded_cmd[15] <= transport_tx_sink_param_c; + transport_tx_encoded_cmd[23:16] <= transport_tx_sink_param_command; + transport_tx_encoded_cmd[127:120] <= transport_tx_sink_param_control; + transport_tx_encoded_cmd[111:96] <= transport_tx_sink_param_count; + transport_tx_encoded_cmd[63:56] <= transport_tx_sink_param_device; + transport_tx_encoded_cmd[31:24] <= transport_tx_sink_param_features[7:0]; + transport_tx_encoded_cmd[95:88] <= transport_tx_sink_param_features[15:8]; + transport_tx_encoded_cmd[119:112] <= transport_tx_sink_param_icc; + transport_tx_encoded_cmd[55:32] <= transport_tx_sink_param_lba[23:0]; + transport_tx_encoded_cmd[87:64] <= transport_tx_sink_param_lba[47:24]; + transport_tx_encoded_cmd[11:8] <= transport_tx_sink_param_pm_port; + transport_tx_encoded_cmd[7:0] <= transport_tx_sink_param_type; + transport_tx_cmd_len <= 3'd4; + transport_tx_cmd_send <= 1'd1; + if (transport_tx_cmd_done) begin + transport_tx_sink_ready <= 1'd1; + subfragments_litesatatransporttx_next_state <= 1'd0; + end + end + 2'd2: begin + transport_tx_sink_ready <= 1'd0; + transport_tx_encoded_cmd[7:0] <= transport_tx_sink_param_type; + transport_tx_cmd_len <= 1'd0; + transport_tx_cmd_with_data <= 1'd1; + transport_tx_cmd_send <= 1'd1; + if (transport_tx_cmd_done) begin + subfragments_litesatatransporttx_next_state <= 2'd3; + end + end + 2'd3: begin + transport_tx_data_send <= 1'd1; + transport_tx_sink_ready <= link_litesatalinktx_sink_sink_ready; + if (((transport_tx_sink_valid & transport_tx_sink_last) & transport_tx_sink_ready)) begin + subfragments_litesatatransporttx_next_state <= 1'd0; + end + end + default: begin + transport_tx_sink_ready <= 1'd0; + transport_tx_counter_reset <= 1'd1; + transport_tx_update_fis_type <= 1'd1; + if (transport_tx_sink_valid) begin + if ((transport_tx_sink_param_type == 6'd39)) begin + subfragments_litesatatransporttx_next_state <= 1'd1; + end else begin + if ((transport_tx_sink_param_type == 7'd70)) begin + subfragments_litesatatransporttx_next_state <= 2'd2; + end else begin + transport_tx_sink_ready <= 1'd1; + end + end + end else begin + transport_tx_sink_ready <= 1'd1; + end + end + endcase +end +always @(*) begin + transport_rx_counter_ce <= 1'd0; + if ((transport_rx_cmd_receive & link_rx_buffer_source_valid)) begin + transport_rx_counter_ce <= 1'd1; + end +end +assign transport_rx_cmd_done = ((transport_rx_counter == transport_rx_cmd_len) & link_rx_buffer_source_ready); +always @(*) begin + transport_rx_source_param_errors <= 8'd0; + transport_rx_source_param_lba <= 48'd0; + transport_rx_source_param_device <= 8'd0; + transport_rx_source_param_count <= 16'd0; + transport_rx_source_param_status <= 8'd0; + transport_rx_source_param_transfer_count <= 16'd0; + transport_rx_source_param_error <= 1'd0; + transport_rx_counter_reset <= 1'd0; + transport_rx_cmd_len <= 3'd0; + transport_rx_cmd_receive <= 1'd0; + transport_rx_data_receive <= 1'd0; + link_rx_buffer_source_ready <= 1'd0; + transport_rx_update_fis_type <= 1'd0; + transport_rx_source_valid <= 1'd0; + transport_rx_source_last <= 1'd0; + transport_rx_source_payload_data <= 32'd0; + transport_rx_source_param_type <= 8'd0; + transport_rx_source_param_pm_port <= 4'd0; + transport_rx_source_param_d <= 1'd0; + transport_rx_source_param_i <= 1'd0; + subfragments_litesatatransportrx_next_state <= 3'd0; + subfragments_litesatatransportrx_next_state <= subfragments_litesatatransportrx_state; + case (subfragments_litesatatransportrx_state) + 1'd1: begin + if ((transport_rx_fis_type == 6'd52)) begin + transport_rx_cmd_len <= 3'd4; + end else begin + if ((transport_rx_fis_type == 6'd57)) begin + transport_rx_cmd_len <= 1'd0; + end else begin + transport_rx_cmd_len <= 3'd4; + end + end + transport_rx_cmd_receive <= 1'd1; + link_rx_buffer_source_ready <= 1'd1; + if (transport_rx_cmd_done) begin + subfragments_litesatatransportrx_next_state <= 2'd2; + end + end + 2'd2: begin + transport_rx_source_valid <= 1'd1; + transport_rx_source_last <= 1'd1; + if ((transport_rx_fis_type == 6'd52)) begin + transport_rx_source_param_count <= transport_rx_encoded_cmd[111:96]; + transport_rx_source_param_device <= transport_rx_encoded_cmd[63:56]; + transport_rx_source_param_errors <= transport_rx_encoded_cmd[31:24]; + transport_rx_source_param_i <= transport_rx_encoded_cmd[14]; + transport_rx_source_param_lba[23:0] <= transport_rx_encoded_cmd[55:32]; + transport_rx_source_param_lba[47:24] <= transport_rx_encoded_cmd[87:64]; + transport_rx_source_param_pm_port <= transport_rx_encoded_cmd[11:8]; + transport_rx_source_param_status <= transport_rx_encoded_cmd[23:16]; + transport_rx_source_param_type <= transport_rx_encoded_cmd[7:0]; + end else begin + if ((transport_rx_fis_type == 6'd57)) begin + transport_rx_source_param_pm_port <= transport_rx_encoded_cmd[11:8]; + transport_rx_source_param_type <= transport_rx_encoded_cmd[7:0]; + end else begin + transport_rx_source_param_count <= transport_rx_encoded_cmd[111:96]; + transport_rx_source_param_d <= transport_rx_encoded_cmd[13]; + transport_rx_source_param_errors <= transport_rx_encoded_cmd[31:24]; + transport_rx_source_param_i <= transport_rx_encoded_cmd[14]; + transport_rx_source_param_lba[23:0] <= transport_rx_encoded_cmd[55:32]; + transport_rx_source_param_lba[47:24] <= transport_rx_encoded_cmd[87:64]; + transport_rx_source_param_pm_port <= transport_rx_encoded_cmd[11:8]; + transport_rx_source_param_status <= transport_rx_encoded_cmd[23:16]; + transport_rx_source_param_transfer_count <= transport_rx_encoded_cmd[143:128]; + transport_rx_source_param_type <= transport_rx_encoded_cmd[7:0]; + end + end + if ((transport_rx_source_valid & transport_rx_source_ready)) begin + subfragments_litesatatransportrx_next_state <= 1'd0; + end + end + 2'd3: begin + transport_rx_cmd_len <= 1'd0; + transport_rx_cmd_receive <= 1'd1; + link_rx_buffer_source_ready <= 1'd1; + if (transport_rx_cmd_done) begin + subfragments_litesatatransportrx_next_state <= 3'd4; + end + end + 3'd4: begin + transport_rx_data_receive <= 1'd1; + transport_rx_source_valid <= link_rx_buffer_source_valid; + transport_rx_source_param_type <= transport_rx_encoded_cmd[7:0]; + transport_rx_source_last <= link_rx_buffer_source_last; + transport_rx_source_param_error <= link_rx_buffer_source_payload_error; + transport_rx_source_payload_data <= link_rx_buffer_source_payload_data; + link_rx_buffer_source_ready <= transport_rx_source_ready; + if (((transport_rx_source_valid & transport_rx_source_last) & transport_rx_source_ready)) begin + subfragments_litesatatransportrx_next_state <= 1'd0; + end + end + default: begin + link_rx_buffer_source_ready <= 1'd0; + transport_rx_counter_reset <= 1'd1; + transport_rx_update_fis_type <= 1'd1; + if (link_rx_buffer_source_valid) begin + if ((link_rx_buffer_source_payload_data[7:0] == 6'd52)) begin + subfragments_litesatatransportrx_next_state <= 1'd1; + end else begin + if ((link_rx_buffer_source_payload_data[7:0] == 6'd57)) begin + subfragments_litesatatransportrx_next_state <= 1'd1; + end else begin + if ((link_rx_buffer_source_payload_data[7:0] == 7'd95)) begin + subfragments_litesatatransportrx_next_state <= 1'd1; + end else begin + if ((link_rx_buffer_source_payload_data[7:0] == 7'd70)) begin + subfragments_litesatatransportrx_next_state <= 2'd3; + end else begin + link_rx_buffer_source_ready <= 1'd1; + end + end + end + end + end else begin + link_rx_buffer_source_ready <= 1'd1; + end + end + endcase +end +assign command_tx_from_rx_valid = command_rx_to_tx_valid; +assign command_rx_to_tx_ready = command_tx_from_rx_ready; +assign command_tx_from_rx_first = command_rx_to_tx_first; +assign command_tx_from_rx_last = command_rx_to_tx_last; +assign command_tx_from_rx_payload_dma_activate = command_rx_to_tx_payload_dma_activate; +assign command_tx_from_rx_payload_d2h_error = command_rx_to_tx_payload_d2h_error; +assign command_rx_from_tx_valid = command_tx_to_rx_valid; +assign command_tx_to_rx_ready = command_rx_from_tx_ready; +assign command_rx_from_tx_first = command_tx_to_rx_first; +assign command_rx_from_tx_last = command_tx_to_rx_last; +assign command_rx_from_tx_payload_write = command_tx_to_rx_payload_write; +assign command_rx_from_tx_payload_read = command_tx_to_rx_payload_read; +assign command_rx_from_tx_payload_identify = command_tx_to_rx_payload_identify; +assign command_rx_from_tx_payload_count = command_tx_to_rx_payload_count; +assign transport_tx_sink_param_pm_port = 1'd0; +assign transport_tx_sink_param_features = 1'd0; +assign transport_tx_sink_param_lba = command_tx_sink_param_sector; +assign transport_tx_sink_param_device = 8'd224; +assign transport_tx_sink_param_count = command_tx_sink_param_count; +assign transport_tx_sink_param_icc = 1'd0; +assign transport_tx_sink_param_control = 1'd0; +assign transport_tx_sink_payload_data = command_tx_sink_payload_data; +always @(*) begin + transport_tx_sink_param_command <= 8'd0; + transport_tx_sink_param_type <= 8'd0; + if (command_tx_is_ongoing1) begin + transport_tx_sink_param_type <= 7'd70; + end else begin + transport_tx_sink_param_type <= 6'd39; + if (command_tx_is_write) begin + transport_tx_sink_param_command <= 6'd53; + end else begin + if (command_tx_is_read) begin + transport_tx_sink_param_command <= 6'd37; + end else begin + transport_tx_sink_param_command <= 8'd236; + end + end + end +end +always @(*) begin + command_tx_to_rx_payload_write <= 1'd0; + command_tx_to_rx_payload_read <= 1'd0; + command_tx_to_rx_payload_identify <= 1'd0; + command_tx_to_rx_payload_count <= 16'd0; + if (command_tx_sink_valid) begin + command_tx_to_rx_payload_write <= command_tx_sink_param_write; + command_tx_to_rx_payload_read <= command_tx_sink_param_read; + command_tx_to_rx_payload_identify <= command_tx_sink_param_identify; + command_tx_to_rx_payload_count <= command_tx_sink_param_count; + end +end +always @(*) begin + command_tx_dwords_counter_subfragments_litesatacommandtx_next_value <= 11'd0; + transport_tx_sink_last <= 1'd0; + command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce <= 1'd0; + command_tx_is_ongoing1 <= 1'd0; + transport_tx_sink_param_c <= 1'd0; + command_tx_is_ongoing0 <= 1'd0; + command_tx_sink_ready <= 1'd0; + subfragments_litesatacommandtx_next_state <= 2'd0; + transport_tx_sink_valid <= 1'd0; + subfragments_litesatacommandtx_next_state <= subfragments_litesatacommandtx_state; + case (subfragments_litesatacommandtx_state) + 1'd1: begin + transport_tx_sink_valid <= command_tx_sink_valid; + transport_tx_sink_last <= 1'd1; + transport_tx_sink_param_c <= 1'd1; + if ((transport_tx_sink_valid & transport_tx_sink_ready)) begin + if (command_tx_is_write) begin + subfragments_litesatacommandtx_next_state <= 2'd2; + end else begin + command_tx_sink_ready <= 1'd1; + subfragments_litesatacommandtx_next_state <= 1'd0; + end + end + end + 2'd2: begin + command_tx_dwords_counter_subfragments_litesatacommandtx_next_value <= 1'd0; + command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce <= 1'd1; + if (command_tx_from_rx_payload_dma_activate) begin + subfragments_litesatacommandtx_next_state <= 2'd3; + end else begin + if (command_tx_from_rx_payload_d2h_error) begin + command_tx_sink_ready <= 1'd1; + subfragments_litesatacommandtx_next_state <= 1'd0; + end + end + end + 2'd3: begin + transport_tx_sink_valid <= command_tx_sink_valid; + transport_tx_sink_last <= ((command_tx_dwords_counter == 11'd2047) | command_tx_sink_last); + command_tx_sink_ready <= transport_tx_sink_ready; + if ((command_tx_sink_valid & command_tx_sink_ready)) begin + command_tx_dwords_counter_subfragments_litesatacommandtx_next_value <= (command_tx_dwords_counter + 1'd1); + command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce <= 1'd1; + if (command_tx_sink_last) begin + subfragments_litesatacommandtx_next_state <= 1'd0; + end else begin + if ((command_tx_dwords_counter == 11'd2047)) begin + subfragments_litesatacommandtx_next_state <= 2'd2; + end + end + end + command_tx_is_ongoing1 <= 1'd1; + end + default: begin + command_tx_sink_ready <= 1'd0; + if (command_tx_sink_valid) begin + subfragments_litesatacommandtx_next_state <= 1'd1; + end else begin + command_tx_sink_ready <= 1'd1; + end + command_tx_is_ongoing0 <= 1'd1; + end + endcase +end +assign command_rx_read_done = (command_rx_dwords_counter == command_rx_read_ndwords); +assign command_rx_to_tx_payload_dma_activate = command_rx_is_dma_activate; +assign command_rx_to_tx_payload_d2h_error = command_rx_d2h_error; +always @(*) begin + command_rx_is_dma_activate <= 1'd0; + command_rx_source_valid <= 1'd0; + command_rx_clr_d2h_error <= 1'd0; + command_rx_source_last <= 1'd0; + command_rx_set_d2h_error <= 1'd0; + command_rx_source_payload_data <= 32'd0; + command_rx_source_param_write <= 1'd0; + command_rx_source_param_read <= 1'd0; + command_rx_clr_read_error <= 1'd0; + subfragments_litesatacommandrx_next_state <= 4'd0; + command_rx_set_read_error <= 1'd0; + command_rx_dwords_counter_subfragments_litesatacommandrx_next_value <= 23'd0; + command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce <= 1'd0; + command_rx_source_param_identify <= 1'd0; + command_rx_update_d2h <= 1'd0; + command_rx_source_param_end <= 1'd0; + command_rx_source_param_failed <= 1'd0; + command_rx_is_ongoing <= 1'd0; + transport_rx_source_ready <= 1'd0; + subfragments_litesatacommandrx_next_state <= subfragments_litesatacommandrx_state; + case (subfragments_litesatacommandrx_state) + 1'd1: begin + transport_rx_source_ready <= 1'd1; + if (transport_rx_source_valid) begin + if ((transport_rx_source_param_type == 6'd57)) begin + command_rx_is_dma_activate <= 1'd1; + end else begin + if ((transport_rx_source_param_type == 6'd52)) begin + command_rx_update_d2h <= 1'd1; + command_rx_set_d2h_error <= transport_rx_source_param_status[0]; + subfragments_litesatacommandrx_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + command_rx_source_valid <= 1'd1; + command_rx_source_last <= 1'd1; + command_rx_source_param_write <= 1'd1; + command_rx_source_param_end <= 1'd1; + command_rx_source_param_failed <= (transport_rx_source_param_error | command_rx_d2h_error); + if ((command_rx_source_valid & command_rx_source_ready)) begin + subfragments_litesatacommandrx_next_state <= 1'd0; + end + end + 2'd3: begin + transport_rx_source_ready <= 1'd1; + if (transport_rx_source_valid) begin + transport_rx_source_ready <= 1'd0; + if ((transport_rx_source_param_type == 7'd70)) begin + subfragments_litesatacommandrx_next_state <= 3'd6; + end else begin + if ((transport_rx_source_param_type == 6'd52)) begin + command_rx_update_d2h <= 1'd1; + command_rx_set_d2h_error <= transport_rx_source_param_status[0]; + subfragments_litesatacommandrx_next_state <= 3'd7; + end + end + end + end + 3'd4: begin + transport_rx_source_ready <= 1'd1; + if (transport_rx_source_valid) begin + transport_rx_source_ready <= 1'd0; + if ((transport_rx_source_param_type == 7'd95)) begin + subfragments_litesatacommandrx_next_state <= 3'd5; + end else begin + subfragments_litesatacommandrx_next_state <= 4'd8; + end + end + end + 3'd5: begin + transport_rx_source_ready <= 1'd1; + if ((transport_rx_source_valid & transport_rx_source_last)) begin + subfragments_litesatacommandrx_next_state <= 2'd3; + end + end + 3'd6: begin + command_rx_set_read_error <= transport_rx_source_param_error; + command_rx_source_valid <= transport_rx_source_valid; + command_rx_source_last <= transport_rx_source_last; + command_rx_source_param_read <= (~command_rx_is_identify); + command_rx_source_param_identify <= command_rx_is_identify; + command_rx_source_param_failed <= transport_rx_source_param_error; + command_rx_source_param_end <= command_rx_is_identify; + command_rx_source_payload_data <= transport_rx_source_payload_data; + transport_rx_source_ready <= command_rx_source_ready; + if ((command_rx_source_valid & command_rx_source_ready)) begin + if ((~command_rx_read_done)) begin + command_rx_dwords_counter_subfragments_litesatacommandrx_next_value <= (command_rx_dwords_counter + 1'd1); + command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce <= 1'd1; + end + if (command_rx_source_last) begin + if (command_rx_is_identify) begin + subfragments_litesatacommandrx_next_state <= 1'd0; + end else begin + subfragments_litesatacommandrx_next_state <= 2'd3; + end + end + end + end + 3'd7: begin + command_rx_source_valid <= 1'd1; + command_rx_source_last <= 1'd1; + command_rx_source_param_read <= 1'd1; + command_rx_source_param_end <= 1'd1; + command_rx_source_param_failed <= (((~command_rx_read_done) | command_rx_read_error) | command_rx_d2h_error); + if ((command_rx_source_valid & command_rx_source_ready)) begin + subfragments_litesatacommandrx_next_state <= 1'd0; + end + end + 4'd8: begin + transport_rx_source_ready <= 1'd1; + if ((transport_rx_source_valid & transport_rx_source_last)) begin + subfragments_litesatacommandrx_next_state <= 3'd4; + end + end + default: begin + command_rx_dwords_counter_subfragments_litesatacommandrx_next_value <= 1'd0; + command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce <= 1'd1; + transport_rx_source_ready <= 1'd1; + command_rx_clr_d2h_error <= 1'd1; + command_rx_clr_read_error <= 1'd1; + if (command_rx_from_tx_payload_write) begin + subfragments_litesatacommandrx_next_state <= 1'd1; + end else begin + if (command_rx_from_tx_payload_read) begin + subfragments_litesatacommandrx_next_state <= 2'd3; + end else begin + if (command_rx_from_tx_payload_identify) begin + subfragments_litesatacommandrx_next_state <= 3'd4; + end + end + end + command_rx_is_ongoing <= 1'd1; + end + endcase +end +assign command_tx_sink_valid = source_valid; +assign source_ready = command_tx_sink_ready; +assign command_tx_sink_first = source_first; +assign command_tx_sink_last = source_last; +assign command_tx_sink_payload_data = source_payload_data; +assign command_tx_sink_param_write = source_param_write; +assign command_tx_sink_param_read = source_param_read; +assign command_tx_sink_param_identify = source_param_identify; +assign command_tx_sink_param_sector = source_param_sector; +assign command_tx_sink_param_count = source_param_count; +assign sink_valid = command_rx_source_valid; +assign command_rx_source_ready = sink_ready; +assign sink_first = command_rx_source_first; +assign sink_last = command_rx_source_last; +assign sink_payload_data = command_rx_source_payload_data; +assign sink_param_write = command_rx_source_param_write; +assign sink_param_read = command_rx_source_param_read; +assign sink_param_identify = command_rx_source_param_identify; +assign sink_param_end = command_rx_source_param_end; +assign sink_param_failed = command_rx_source_param_failed; +assign subfragments_done0 = (((litesatauserport0_source_valid & litesatauserport0_source_last) & litesatauserport0_source_param_end) & litesatauserport0_source_ready); +assign subfragments_done1 = (((litesatauserport1_source_valid & litesatauserport1_source_last) & litesatauserport1_source_param_end) & litesatauserport1_source_ready); +always @(*) begin + subfragments_request <= 2'd0; + subfragments_request[0] <= ((litesatauserport0_sink_valid | subfragments_ongoing0) & (~subfragments_done0)); + subfragments_request[1] <= ((litesatauserport1_sink_valid | subfragments_ongoing1) & (~subfragments_done1)); +end +always @(*) begin + litesatauserport1_sink_ready <= 1'd0; + litesatauserport0_sink_ready <= 1'd0; + source_valid <= 1'd0; + litesatauserport1_source_valid <= 1'd0; + source_first <= 1'd0; + source_last <= 1'd0; + litesatauserport1_source_first <= 1'd0; + source_payload_data <= 32'd0; + litesatauserport1_source_last <= 1'd0; + source_param_write <= 1'd0; + litesatauserport1_source_payload_data <= 32'd0; + source_param_read <= 1'd0; + litesatauserport1_source_param_write <= 1'd0; + source_param_identify <= 1'd0; + litesatauserport1_source_param_read <= 1'd0; + source_param_sector <= 48'd0; + litesatauserport1_source_param_identify <= 1'd0; + litesatauserport0_source_valid <= 1'd0; + source_param_count <= 16'd0; + litesatauserport1_source_param_end <= 1'd0; + litesatauserport1_source_param_failed <= 1'd0; + litesatauserport0_source_first <= 1'd0; + sink_ready <= 1'd0; + litesatauserport0_source_last <= 1'd0; + litesatauserport0_source_payload_data <= 32'd0; + litesatauserport0_source_param_write <= 1'd0; + litesatauserport0_source_param_read <= 1'd0; + litesatauserport0_source_param_identify <= 1'd0; + litesatauserport0_source_param_end <= 1'd0; + litesatauserport0_source_param_failed <= 1'd0; + case (subfragments_grant) + 1'd0: begin + source_valid <= litesatauserport0_sink_valid; + litesatauserport0_sink_ready <= source_ready; + source_first <= litesatauserport0_sink_first; + source_last <= litesatauserport0_sink_last; + source_payload_data <= litesatauserport0_sink_payload_data; + source_param_write <= litesatauserport0_sink_param_write; + source_param_read <= litesatauserport0_sink_param_read; + source_param_identify <= litesatauserport0_sink_param_identify; + source_param_sector <= litesatauserport0_sink_param_sector; + source_param_count <= litesatauserport0_sink_param_count; + litesatauserport0_source_valid <= sink_valid; + sink_ready <= litesatauserport0_source_ready; + litesatauserport0_source_first <= sink_first; + litesatauserport0_source_last <= sink_last; + litesatauserport0_source_payload_data <= sink_payload_data; + litesatauserport0_source_param_write <= sink_param_write; + litesatauserport0_source_param_read <= sink_param_read; + litesatauserport0_source_param_identify <= sink_param_identify; + litesatauserport0_source_param_end <= sink_param_end; + litesatauserport0_source_param_failed <= sink_param_failed; + end + 1'd1: begin + source_valid <= litesatauserport1_sink_valid; + litesatauserport1_sink_ready <= source_ready; + source_first <= litesatauserport1_sink_first; + source_last <= litesatauserport1_sink_last; + source_payload_data <= litesatauserport1_sink_payload_data; + source_param_write <= litesatauserport1_sink_param_write; + source_param_read <= litesatauserport1_sink_param_read; + source_param_identify <= litesatauserport1_sink_param_identify; + source_param_sector <= litesatauserport1_sink_param_sector; + source_param_count <= litesatauserport1_sink_param_count; + litesatauserport1_source_valid <= sink_valid; + sink_ready <= litesatauserport1_source_ready; + litesatauserport1_source_first <= sink_first; + litesatauserport1_source_last <= sink_last; + litesatauserport1_source_payload_data <= sink_payload_data; + litesatauserport1_source_param_write <= sink_param_write; + litesatauserport1_source_param_read <= sink_param_read; + litesatauserport1_source_param_identify <= sink_param_identify; + litesatauserport1_source_param_end <= sink_param_end; + litesatauserport1_source_param_failed <= sink_param_failed; + end + endcase +end +assign sata_sector2mem_buf_sink_valid = litesatauserport0_source_valid; +assign litesatauserport0_source_ready = sata_sector2mem_buf_sink_ready; +assign sata_sector2mem_buf_sink_last = litesatauserport0_source_last; +assign sata_sector2mem_buf_sink_payload_data = litesatauserport0_source_payload_data; +assign sata_sector2mem_converter_sink_valid = sata_sector2mem_buf_source_valid; +assign sata_sector2mem_buf_source_ready = sata_sector2mem_converter_sink_ready; +assign sata_sector2mem_converter_sink_first = sata_sector2mem_buf_source_first; +assign sata_sector2mem_converter_sink_last = sata_sector2mem_buf_source_last; +assign sata_sector2mem_converter_sink_payload_data = sata_sector2mem_buf_source_payload_data; +assign sata_sector2mem_buf_syncfifo_din = {sata_sector2mem_buf_fifo_in_last, sata_sector2mem_buf_fifo_in_first, sata_sector2mem_buf_fifo_in_payload_data}; +assign {sata_sector2mem_buf_fifo_out_last, sata_sector2mem_buf_fifo_out_first, sata_sector2mem_buf_fifo_out_payload_data} = sata_sector2mem_buf_syncfifo_dout; +assign sata_sector2mem_buf_sink_ready = sata_sector2mem_buf_syncfifo_writable; +assign sata_sector2mem_buf_syncfifo_we = sata_sector2mem_buf_sink_valid; +assign sata_sector2mem_buf_fifo_in_first = sata_sector2mem_buf_sink_first; +assign sata_sector2mem_buf_fifo_in_last = sata_sector2mem_buf_sink_last; +assign sata_sector2mem_buf_fifo_in_payload_data = sata_sector2mem_buf_sink_payload_data; +assign sata_sector2mem_buf_source_valid = sata_sector2mem_buf_syncfifo_readable; +assign sata_sector2mem_buf_source_first = sata_sector2mem_buf_fifo_out_first; +assign sata_sector2mem_buf_source_last = sata_sector2mem_buf_fifo_out_last; +assign sata_sector2mem_buf_source_payload_data = sata_sector2mem_buf_fifo_out_payload_data; +assign sata_sector2mem_buf_syncfifo_re = sata_sector2mem_buf_source_ready; +always @(*) begin + sata_sector2mem_buf_wrport_adr <= 7'd0; + if (sata_sector2mem_buf_replace) begin + sata_sector2mem_buf_wrport_adr <= (sata_sector2mem_buf_produce - 1'd1); + end else begin + sata_sector2mem_buf_wrport_adr <= sata_sector2mem_buf_produce; + end +end +assign sata_sector2mem_buf_wrport_dat_w = sata_sector2mem_buf_syncfifo_din; +assign sata_sector2mem_buf_wrport_we = (sata_sector2mem_buf_syncfifo_we & (sata_sector2mem_buf_syncfifo_writable | sata_sector2mem_buf_replace)); +assign sata_sector2mem_buf_do_read = (sata_sector2mem_buf_syncfifo_readable & sata_sector2mem_buf_syncfifo_re); +assign sata_sector2mem_buf_rdport_adr = sata_sector2mem_buf_consume; +assign sata_sector2mem_buf_syncfifo_dout = sata_sector2mem_buf_rdport_dat_r; +assign sata_sector2mem_buf_syncfifo_writable = (sata_sector2mem_buf_level != 8'd128); +assign sata_sector2mem_buf_syncfifo_readable = (sata_sector2mem_buf_level != 1'd0); +assign sata_sector2mem_source_source_valid = sata_sector2mem_converter_source_valid; +assign sata_sector2mem_converter_source_ready = sata_sector2mem_source_source_ready; +assign sata_sector2mem_source_source_first = sata_sector2mem_converter_source_first; +assign sata_sector2mem_source_source_last = sata_sector2mem_converter_source_last; +assign sata_sector2mem_source_source_payload_data = sata_sector2mem_converter_source_payload_data; +assign sata_sector2mem_converter_source_valid = sata_sector2mem_converter_sink_valid; +assign sata_sector2mem_converter_sink_ready = sata_sector2mem_converter_source_ready; +assign sata_sector2mem_converter_source_first = sata_sector2mem_converter_sink_first; +assign sata_sector2mem_converter_source_last = sata_sector2mem_converter_sink_last; +assign sata_sector2mem_converter_source_payload_data = sata_sector2mem_converter_sink_payload_data; +assign sata_sector2mem_converter_source_payload_valid_token_count = 1'd1; +assign interface0_bus_stb = sata_sector2mem_dma_sink_valid; +assign interface0_bus_cyc = sata_sector2mem_dma_sink_valid; +assign interface0_bus_we = 1'd1; +assign interface0_bus_sel = 4'd15; +assign interface0_bus_adr = sata_sector2mem_dma_sink_payload_address; +assign interface0_bus_dat_w = {sata_sector2mem_dma_sink_payload_data[7:0], sata_sector2mem_dma_sink_payload_data[15:8], sata_sector2mem_dma_sink_payload_data[23:16], sata_sector2mem_dma_sink_payload_data[31:24]}; +assign sata_sector2mem_dma_sink_ready = interface0_bus_ack; +always @(*) begin + sata_sector2mem_error_status_subfragments_next_value1 <= 1'd0; + sata_sector2mem_error_status_subfragments_next_value_ce1 <= 1'd0; + sata_sector2mem_dma_sink_valid <= 1'd0; + sata_sector2mem_dma_sink_last <= 1'd0; + sata_sector2mem_dma_sink_payload_address <= 32'd0; + sata_sector2mem_dma_sink_payload_data <= 32'd0; + litesatauserport0_sink_valid <= 1'd0; + litesatauserport0_sink_last <= 1'd0; + litesatauserport0_sink_param_read <= 1'd0; + litesatauserport0_sink_param_sector <= 48'd0; + litesatauserport0_sink_param_count <= 16'd0; + sata_sector2mem_done_status <= 1'd0; + subfragments_litesatasector2memdma_next_state <= 2'd0; + sata_sector2mem_count_subfragments_next_value0 <= 7'd0; + sata_sector2mem_source_source_ready <= 1'd0; + sata_sector2mem_count_subfragments_next_value_ce0 <= 1'd0; + subfragments_litesatasector2memdma_next_state <= subfragments_litesatasector2memdma_state; + case (subfragments_litesatasector2memdma_state) + 1'd1: begin + litesatauserport0_sink_valid <= 1'd1; + litesatauserport0_sink_last <= 1'd1; + litesatauserport0_sink_param_read <= 1'd1; + litesatauserport0_sink_param_sector <= sata_sector2mem_sector_storage; + litesatauserport0_sink_param_count <= 1'd1; + if (litesatauserport0_sink_ready) begin + subfragments_litesatasector2memdma_next_state <= 2'd2; + end + end + 2'd2: begin + sata_sector2mem_dma_sink_valid <= sata_sector2mem_source_source_valid; + sata_sector2mem_dma_sink_last <= sata_sector2mem_source_source_last; + sata_sector2mem_dma_sink_payload_address <= (sata_sector2mem_base_storage[63:2] + sata_sector2mem_count); + sata_sector2mem_dma_sink_payload_data <= {sata_sector2mem_source_source_payload_data[7:0], sata_sector2mem_source_source_payload_data[15:8], sata_sector2mem_source_source_payload_data[23:16], sata_sector2mem_source_source_payload_data[31:24]}; + sata_sector2mem_source_source_ready <= sata_sector2mem_dma_sink_ready; + if ((sata_sector2mem_dma_sink_valid & sata_sector2mem_dma_sink_ready)) begin + sata_sector2mem_count_subfragments_next_value0 <= (sata_sector2mem_count + 1'd1); + sata_sector2mem_count_subfragments_next_value_ce0 <= 1'd1; + if (sata_sector2mem_dma_sink_last) begin + subfragments_litesatasector2memdma_next_state <= 1'd0; + end + end + if ((litesatauserport0_source_valid & litesatauserport0_source_ready)) begin + if (litesatauserport0_source_param_failed) begin + sata_sector2mem_error_status_subfragments_next_value1 <= 1'd1; + sata_sector2mem_error_status_subfragments_next_value_ce1 <= 1'd1; + subfragments_litesatasector2memdma_next_state <= 1'd0; + end + end + end + default: begin + if (sata_sector2mem_start_re) begin + sata_sector2mem_count_subfragments_next_value0 <= 1'd0; + sata_sector2mem_count_subfragments_next_value_ce0 <= 1'd1; + sata_sector2mem_error_status_subfragments_next_value1 <= 1'd0; + sata_sector2mem_error_status_subfragments_next_value_ce1 <= 1'd1; + subfragments_litesatasector2memdma_next_state <= 1'd1; + end else begin + sata_sector2mem_done_status <= 1'd1; + end + sata_sector2mem_source_source_ready <= 1'd1; + end + endcase +end +assign sata_mem2sector_buf_sink_valid = sata_mem2sector_dma_source_valid; +assign sata_mem2sector_dma_source_ready = sata_mem2sector_buf_sink_ready; +assign sata_mem2sector_buf_sink_first = sata_mem2sector_dma_source_first; +assign sata_mem2sector_buf_sink_last = sata_mem2sector_dma_source_last; +assign sata_mem2sector_buf_sink_payload_data = sata_mem2sector_dma_source_payload_data; +assign sata_mem2sector_converter_sink_valid = sata_mem2sector_buf_source_valid; +assign sata_mem2sector_buf_source_ready = sata_mem2sector_converter_sink_ready; +assign sata_mem2sector_converter_sink_first = sata_mem2sector_buf_source_first; +assign sata_mem2sector_converter_sink_last = sata_mem2sector_buf_source_last; +assign sata_mem2sector_converter_sink_payload_data = sata_mem2sector_buf_source_payload_data; +always @(*) begin + subfragments_wishbonedmareader_next_state <= 1'd0; + sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value <= 32'd0; + sata_mem2sector_dma_source_last <= 1'd0; + sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value_ce <= 1'd0; + sata_mem2sector_dma_source_payload_data <= 32'd0; + interface1_bus_adr <= 32'd0; + interface1_bus_sel <= 4'd0; + interface1_bus_cyc <= 1'd0; + interface1_bus_stb <= 1'd0; + sata_mem2sector_dma_sink_ready <= 1'd0; + interface1_bus_we <= 1'd0; + sata_mem2sector_dma_source_valid <= 1'd0; + subfragments_wishbonedmareader_next_state <= subfragments_wishbonedmareader_state; + case (subfragments_wishbonedmareader_state) + 1'd1: begin + sata_mem2sector_dma_source_valid <= 1'd1; + sata_mem2sector_dma_source_last <= sata_mem2sector_dma_sink_last; + sata_mem2sector_dma_source_payload_data <= sata_mem2sector_dma_data; + if (sata_mem2sector_dma_source_ready) begin + sata_mem2sector_dma_sink_ready <= 1'd1; + subfragments_wishbonedmareader_next_state <= 1'd0; + end + end + default: begin + interface1_bus_stb <= sata_mem2sector_dma_sink_valid; + interface1_bus_cyc <= sata_mem2sector_dma_sink_valid; + interface1_bus_we <= 1'd0; + interface1_bus_sel <= 4'd15; + interface1_bus_adr <= sata_mem2sector_dma_sink_payload_address; + if ((interface1_bus_stb & interface1_bus_ack)) begin + sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value <= {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; + sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value_ce <= 1'd1; + subfragments_wishbonedmareader_next_state <= 1'd1; + end + end + endcase +end +assign sata_mem2sector_buf_syncfifo_din = {sata_mem2sector_buf_fifo_in_last, sata_mem2sector_buf_fifo_in_first, sata_mem2sector_buf_fifo_in_payload_data}; +assign {sata_mem2sector_buf_fifo_out_last, sata_mem2sector_buf_fifo_out_first, sata_mem2sector_buf_fifo_out_payload_data} = sata_mem2sector_buf_syncfifo_dout; +assign sata_mem2sector_buf_sink_ready = sata_mem2sector_buf_syncfifo_writable; +assign sata_mem2sector_buf_syncfifo_we = sata_mem2sector_buf_sink_valid; +assign sata_mem2sector_buf_fifo_in_first = sata_mem2sector_buf_sink_first; +assign sata_mem2sector_buf_fifo_in_last = sata_mem2sector_buf_sink_last; +assign sata_mem2sector_buf_fifo_in_payload_data = sata_mem2sector_buf_sink_payload_data; +assign sata_mem2sector_buf_source_valid = sata_mem2sector_buf_syncfifo_readable; +assign sata_mem2sector_buf_source_first = sata_mem2sector_buf_fifo_out_first; +assign sata_mem2sector_buf_source_last = sata_mem2sector_buf_fifo_out_last; +assign sata_mem2sector_buf_source_payload_data = sata_mem2sector_buf_fifo_out_payload_data; +assign sata_mem2sector_buf_syncfifo_re = sata_mem2sector_buf_source_ready; +always @(*) begin + sata_mem2sector_buf_wrport_adr <= 7'd0; + if (sata_mem2sector_buf_replace) begin + sata_mem2sector_buf_wrport_adr <= (sata_mem2sector_buf_produce - 1'd1); + end else begin + sata_mem2sector_buf_wrport_adr <= sata_mem2sector_buf_produce; + end +end +assign sata_mem2sector_buf_wrport_dat_w = sata_mem2sector_buf_syncfifo_din; +assign sata_mem2sector_buf_wrport_we = (sata_mem2sector_buf_syncfifo_we & (sata_mem2sector_buf_syncfifo_writable | sata_mem2sector_buf_replace)); +assign sata_mem2sector_buf_do_read = (sata_mem2sector_buf_syncfifo_readable & sata_mem2sector_buf_syncfifo_re); +assign sata_mem2sector_buf_rdport_adr = sata_mem2sector_buf_consume; +assign sata_mem2sector_buf_syncfifo_dout = sata_mem2sector_buf_rdport_dat_r; +assign sata_mem2sector_buf_syncfifo_writable = (sata_mem2sector_buf_level != 8'd128); +assign sata_mem2sector_buf_syncfifo_readable = (sata_mem2sector_buf_level != 1'd0); +assign sata_mem2sector_source_source_valid = sata_mem2sector_converter_source_valid; +assign sata_mem2sector_converter_source_ready = sata_mem2sector_source_source_ready; +assign sata_mem2sector_source_source_first = sata_mem2sector_converter_source_first; +assign sata_mem2sector_source_source_last = sata_mem2sector_converter_source_last; +assign sata_mem2sector_source_source_payload_data = sata_mem2sector_converter_source_payload_data; +assign sata_mem2sector_converter_source_valid = sata_mem2sector_converter_sink_valid; +assign sata_mem2sector_converter_sink_ready = sata_mem2sector_converter_source_ready; +assign sata_mem2sector_converter_source_first = sata_mem2sector_converter_sink_first; +assign sata_mem2sector_converter_source_last = sata_mem2sector_converter_sink_last; +assign sata_mem2sector_converter_source_payload_data = sata_mem2sector_converter_sink_payload_data; +assign sata_mem2sector_converter_source_payload_valid_token_count = 1'd1; +always @(*) begin + litesatauserport1_sink_valid <= 1'd0; + litesatauserport1_sink_last <= 1'd0; + litesatauserport1_sink_payload_data <= 32'd0; + litesatauserport1_sink_param_write <= 1'd0; + sata_mem2sector_source_source_ready <= 1'd0; + litesatauserport1_sink_param_sector <= 48'd0; + litesatauserport1_sink_param_count <= 16'd0; + litesatauserport1_source_ready <= 1'd0; + sata_mem2sector_done_status <= 1'd0; + subfragments_fsm_next_state <= 2'd0; + sata_mem2sector_count_subfragments_fsm_next_value0 <= 7'd0; + sata_mem2sector_dma_sink_valid <= 1'd0; + sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd0; + sata_mem2sector_error_status_subfragments_fsm_next_value1 <= 1'd0; + sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 <= 1'd0; + sata_mem2sector_dma_sink_payload_address <= 32'd0; + subfragments_fsm_next_state <= subfragments_fsm_state; + case (subfragments_fsm_state) + 1'd1: begin + sata_mem2sector_dma_sink_valid <= 1'd1; + sata_mem2sector_dma_sink_payload_address <= (sata_mem2sector_base_storage[63:2] + sata_mem2sector_count); + if ((sata_mem2sector_dma_sink_valid & sata_mem2sector_dma_sink_ready)) begin + sata_mem2sector_count_subfragments_fsm_next_value0 <= (sata_mem2sector_count + 1'd1); + sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd1; + if ((sata_mem2sector_count == 7'd127)) begin + sata_mem2sector_count_subfragments_fsm_next_value0 <= 1'd0; + sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd1; + subfragments_fsm_next_state <= 2'd2; + end + end + end + 2'd2: begin + litesatauserport1_sink_valid <= 1'd1; + litesatauserport1_sink_last <= (sata_mem2sector_count == 7'd127); + litesatauserport1_sink_param_write <= 1'd1; + litesatauserport1_sink_param_sector <= sata_mem2sector_sector_storage; + litesatauserport1_sink_param_count <= 1'd1; + litesatauserport1_sink_payload_data <= {sata_mem2sector_source_source_payload_data[7:0], sata_mem2sector_source_source_payload_data[15:8], sata_mem2sector_source_source_payload_data[23:16], sata_mem2sector_source_source_payload_data[31:24]}; + if (litesatauserport1_sink_ready) begin + sata_mem2sector_source_source_ready <= 1'd1; + sata_mem2sector_count_subfragments_fsm_next_value0 <= (sata_mem2sector_count + 1'd1); + sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd1; + if (litesatauserport1_sink_last) begin + subfragments_fsm_next_state <= 2'd3; + end + end + litesatauserport1_source_ready <= 1'd1; + if ((litesatauserport1_source_valid & litesatauserport1_source_ready)) begin + if (litesatauserport1_source_param_failed) begin + sata_mem2sector_error_status_subfragments_fsm_next_value1 <= 1'd1; + sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 <= 1'd1; + subfragments_fsm_next_state <= 1'd0; + end + end + end + 2'd3: begin + litesatauserport1_source_ready <= 1'd1; + if (litesatauserport1_source_valid) begin + if (litesatauserport1_source_param_failed) begin + sata_mem2sector_error_status_subfragments_fsm_next_value1 <= 1'd1; + sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 <= 1'd1; + end + subfragments_fsm_next_state <= 1'd0; + end + end + default: begin + if (sata_mem2sector_start_re) begin + sata_mem2sector_count_subfragments_fsm_next_value0 <= 1'd0; + sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd1; + sata_mem2sector_error_status_subfragments_fsm_next_value1 <= 1'd0; + sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 <= 1'd1; + subfragments_fsm_next_state <= 1'd1; + end else begin + sata_mem2sector_done_status <= 1'd1; + end + sata_mem2sector_source_source_ready <= 1'd1; + end + endcase +end +assign wait_1 = (~done); +always @(*) begin + user_led0 <= 1'd0; + user_led1 <= 1'd0; + user_led2 <= 1'd0; + user_led3 <= 1'd0; + user_led4 <= 1'd0; + user_led5 <= 1'd0; + user_led6 <= 1'd0; + user_led7 <= 1'd0; + if ((mode == 1'd1)) begin + {user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= storage; + end else begin + {user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= chaser; + end +end +assign done = (count == 1'd0); +always @(*) begin + basesoc_next_state <= 2'd0; + basesoc_basesoc_dat_w_basesoc_next_value0 <= 32'd0; + basesoc_basesoc_dat_w_basesoc_next_value_ce0 <= 1'd0; + basesoc_basesoc_wishbone_dat_r <= 32'd0; + basesoc_basesoc_adr_basesoc_next_value1 <= 14'd0; + basesoc_basesoc_adr_basesoc_next_value_ce1 <= 1'd0; + basesoc_basesoc_we_basesoc_next_value2 <= 1'd0; + basesoc_basesoc_we_basesoc_next_value_ce2 <= 1'd0; + basesoc_basesoc_wishbone_ack <= 1'd0; + basesoc_next_state <= basesoc_state; + case (basesoc_state) + 1'd1: begin + basesoc_basesoc_adr_basesoc_next_value1 <= 1'd0; + basesoc_basesoc_adr_basesoc_next_value_ce1 <= 1'd1; + basesoc_basesoc_we_basesoc_next_value2 <= 1'd0; + basesoc_basesoc_we_basesoc_next_value_ce2 <= 1'd1; + basesoc_next_state <= 2'd2; + end + 2'd2: begin + basesoc_basesoc_wishbone_ack <= 1'd1; + basesoc_basesoc_wishbone_dat_r <= basesoc_basesoc_dat_r; + basesoc_next_state <= 1'd0; + end + default: begin + basesoc_basesoc_dat_w_basesoc_next_value0 <= basesoc_basesoc_wishbone_dat_w; + basesoc_basesoc_dat_w_basesoc_next_value_ce0 <= 1'd1; + if ((basesoc_basesoc_wishbone_cyc & basesoc_basesoc_wishbone_stb)) begin + basesoc_basesoc_adr_basesoc_next_value1 <= basesoc_basesoc_wishbone_adr; + basesoc_basesoc_adr_basesoc_next_value_ce1 <= 1'd1; + basesoc_basesoc_we_basesoc_next_value2 <= (basesoc_basesoc_wishbone_we & (basesoc_basesoc_wishbone_sel != 1'd0)); + basesoc_basesoc_we_basesoc_next_value_ce2 <= 1'd1; + basesoc_next_state <= 1'd1; + end + end + endcase +end +assign basesoc_shared_adr = rhs_array_muxed36; +assign basesoc_shared_dat_w = rhs_array_muxed37; +assign basesoc_shared_sel = rhs_array_muxed38; +assign basesoc_shared_cyc = rhs_array_muxed39; +assign basesoc_shared_stb = rhs_array_muxed40; +assign basesoc_shared_we = rhs_array_muxed41; +assign basesoc_shared_cti = rhs_array_muxed42; +assign basesoc_shared_bte = rhs_array_muxed43; +assign cpu_ibus_dat_r = basesoc_shared_dat_r; +assign cpu_dbus_dat_r = basesoc_shared_dat_r; +assign interface0_bus_dat_r = basesoc_shared_dat_r; +assign interface1_bus_dat_r = basesoc_shared_dat_r; +assign cpu_ibus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd0)); +assign cpu_dbus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd1)); +assign interface0_bus_ack = (basesoc_shared_ack & (basesoc_grant == 2'd2)); +assign interface1_bus_ack = (basesoc_shared_ack & (basesoc_grant == 2'd3)); +assign cpu_ibus_err = (basesoc_shared_err & (basesoc_grant == 1'd0)); +assign cpu_dbus_err = (basesoc_shared_err & (basesoc_grant == 1'd1)); +assign interface0_bus_err = (basesoc_shared_err & (basesoc_grant == 2'd2)); +assign interface1_bus_err = (basesoc_shared_err & (basesoc_grant == 2'd3)); +assign basesoc_request = {interface1_bus_cyc, interface0_bus_cyc, cpu_dbus_cyc, cpu_ibus_cyc}; +always @(*) begin + basesoc_slave_sel <= 4'd0; + basesoc_slave_sel[0] <= (basesoc_shared_adr[29:14] == 1'd0); + basesoc_slave_sel[1] <= (basesoc_shared_adr[29:11] == 12'd2048); + basesoc_slave_sel[2] <= (basesoc_shared_adr[29:26] == 3'd4); + basesoc_slave_sel[3] <= (basesoc_shared_adr[29:14] == 16'd33280); +end +assign basesoc_ram_bus_adr = basesoc_shared_adr; +assign basesoc_ram_bus_dat_w = basesoc_shared_dat_w; +assign basesoc_ram_bus_sel = basesoc_shared_sel; +assign basesoc_ram_bus_stb = basesoc_shared_stb; +assign basesoc_ram_bus_we = basesoc_shared_we; +assign basesoc_ram_bus_cti = basesoc_shared_cti; +assign basesoc_ram_bus_bte = basesoc_shared_bte; +assign ram_bus_ram_bus_adr = basesoc_shared_adr; +assign ram_bus_ram_bus_dat_w = basesoc_shared_dat_w; +assign ram_bus_ram_bus_sel = basesoc_shared_sel; +assign ram_bus_ram_bus_stb = basesoc_shared_stb; +assign ram_bus_ram_bus_we = basesoc_shared_we; +assign ram_bus_ram_bus_cti = basesoc_shared_cti; +assign ram_bus_ram_bus_bte = basesoc_shared_bte; +assign wb_sdram_adr = basesoc_shared_adr; +assign wb_sdram_dat_w = basesoc_shared_dat_w; +assign wb_sdram_sel = basesoc_shared_sel; +assign wb_sdram_stb = basesoc_shared_stb; +assign wb_sdram_we = basesoc_shared_we; +assign wb_sdram_cti = basesoc_shared_cti; +assign wb_sdram_bte = basesoc_shared_bte; +assign basesoc_basesoc_wishbone_adr = basesoc_shared_adr; +assign basesoc_basesoc_wishbone_dat_w = basesoc_shared_dat_w; +assign basesoc_basesoc_wishbone_sel = basesoc_shared_sel; +assign basesoc_basesoc_wishbone_stb = basesoc_shared_stb; +assign basesoc_basesoc_wishbone_we = basesoc_shared_we; +assign basesoc_basesoc_wishbone_cti = basesoc_shared_cti; +assign basesoc_basesoc_wishbone_bte = basesoc_shared_bte; +assign basesoc_ram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[0]); +assign ram_bus_ram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[1]); +assign wb_sdram_cyc = (basesoc_shared_cyc & basesoc_slave_sel[2]); +assign basesoc_basesoc_wishbone_cyc = (basesoc_shared_cyc & basesoc_slave_sel[3]); +assign basesoc_shared_err = (((basesoc_ram_bus_err | ram_bus_ram_bus_err) | wb_sdram_err) | basesoc_basesoc_wishbone_err); +assign basesoc_wait = ((basesoc_shared_stb & basesoc_shared_cyc) & (~basesoc_shared_ack)); +always @(*) begin + basesoc_error <= 1'd0; + basesoc_shared_dat_r <= 32'd0; + basesoc_shared_ack <= 1'd0; + basesoc_shared_ack <= (((basesoc_ram_bus_ack | ram_bus_ram_bus_ack) | wb_sdram_ack) | basesoc_basesoc_wishbone_ack); + basesoc_shared_dat_r <= (((({32{basesoc_slave_sel_r[0]}} & basesoc_ram_bus_dat_r) | ({32{basesoc_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{basesoc_slave_sel_r[2]}} & wb_sdram_dat_r)) | ({32{basesoc_slave_sel_r[3]}} & basesoc_basesoc_wishbone_dat_r)); + if (basesoc_done) begin + basesoc_shared_dat_r <= 32'd4294967295; + basesoc_shared_ack <= 1'd1; + basesoc_error <= 1'd1; + end +end +assign basesoc_done = (basesoc_count == 1'd0); +assign basesoc_csr_bankarray_csrbank0_sel = (basesoc_csr_bankarray_interface0_bank_bus_adr[13:9] == 1'd0); +assign basesoc_csr_bankarray_csrbank0_reset0_r = basesoc_csr_bankarray_interface0_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank0_reset0_re = ((basesoc_csr_bankarray_csrbank0_sel & basesoc_csr_bankarray_interface0_bank_bus_we) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank0_reset0_we = ((basesoc_csr_bankarray_csrbank0_sel & (~basesoc_csr_bankarray_interface0_bank_bus_we)) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank0_scratch0_r = basesoc_csr_bankarray_interface0_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank0_scratch0_re = ((basesoc_csr_bankarray_csrbank0_sel & basesoc_csr_bankarray_interface0_bank_bus_we) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank0_scratch0_we = ((basesoc_csr_bankarray_csrbank0_sel & (~basesoc_csr_bankarray_interface0_bank_bus_we)) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank0_bus_errors_r = basesoc_csr_bankarray_interface0_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank0_bus_errors_re = ((basesoc_csr_bankarray_csrbank0_sel & basesoc_csr_bankarray_interface0_bank_bus_we) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank0_bus_errors_we = ((basesoc_csr_bankarray_csrbank0_sel & (~basesoc_csr_bankarray_interface0_bank_bus_we)) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank0_reset0_w = soccontroller_reset_storage; +assign basesoc_csr_bankarray_csrbank0_scratch0_w = soccontroller_scratch_storage[31:0]; +assign basesoc_csr_bankarray_csrbank0_bus_errors_w = soccontroller_bus_errors_status[31:0]; +assign soccontroller_bus_errors_we = basesoc_csr_bankarray_csrbank0_bus_errors_we; +assign basesoc_csr_bankarray_csrbank1_sel = (basesoc_csr_bankarray_interface1_bank_bus_adr[13:9] == 3'd6); +assign basesoc_csr_bankarray_csrbank1_rst0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank1_rst0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank1_rst0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[4:0]; +assign basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank1_wlevel_en0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank1_wlevel_en0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank1_wlevel_en0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd2)); +assign a7ddrphy_wlevel_strobe_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; +assign a7ddrphy_wlevel_strobe_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd3)); +assign a7ddrphy_wlevel_strobe_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd3)); +assign basesoc_csr_bankarray_csrbank1_dly_sel0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[1:0]; +assign basesoc_csr_bankarray_csrbank1_dly_sel0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd4)); +assign basesoc_csr_bankarray_csrbank1_dly_sel0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd4)); +assign a7ddrphy_rdly_dq_rst_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_rst_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd5)); +assign a7ddrphy_rdly_dq_rst_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd5)); +assign a7ddrphy_rdly_dq_inc_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_inc_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd6)); +assign a7ddrphy_rdly_dq_inc_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd6)); +assign a7ddrphy_rdly_dq_bitslip_rst_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd7)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd7)); +assign a7ddrphy_rdly_dq_bitslip_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_bitslip_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd8)); +assign a7ddrphy_wdly_dq_bitslip_rst_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; +assign a7ddrphy_wdly_dq_bitslip_rst_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd9)); +assign a7ddrphy_wdly_dq_bitslip_rst_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd9)); +assign a7ddrphy_wdly_dq_bitslip_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; +assign a7ddrphy_wdly_dq_bitslip_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd10)); +assign a7ddrphy_wdly_dq_bitslip_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd10)); +assign basesoc_csr_bankarray_csrbank1_rdphase0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[1:0]; +assign basesoc_csr_bankarray_csrbank1_rdphase0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd11)); +assign basesoc_csr_bankarray_csrbank1_rdphase0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd11)); +assign basesoc_csr_bankarray_csrbank1_wrphase0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[1:0]; +assign basesoc_csr_bankarray_csrbank1_wrphase0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd12)); +assign basesoc_csr_bankarray_csrbank1_wrphase0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd12)); +assign basesoc_csr_bankarray_csrbank1_rst0_w = a7ddrphy_rst_storage; +assign basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; +assign basesoc_csr_bankarray_csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; +assign basesoc_csr_bankarray_csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; +assign basesoc_csr_bankarray_csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0]; +assign basesoc_csr_bankarray_csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; +assign basesoc_csr_bankarray_sel = (basesoc_csr_bankarray_sram_bus_adr[13:9] == 2'd2); +always @(*) begin + basesoc_csr_bankarray_sram_bus_dat_r <= 32'd0; + if (basesoc_csr_bankarray_sel_r) begin + basesoc_csr_bankarray_sram_bus_dat_r <= basesoc_csr_bankarray_dat_r; + end +end +assign basesoc_csr_bankarray_adr = basesoc_csr_bankarray_sram_bus_adr[5:0]; +assign basesoc_csr_bankarray_csrbank2_sel = (basesoc_csr_bankarray_interface2_bank_bus_adr[13:9] == 4'd11); +assign basesoc_csr_bankarray_csrbank2_out0_r = basesoc_csr_bankarray_interface2_bank_bus_dat_w[7:0]; +assign basesoc_csr_bankarray_csrbank2_out0_re = ((basesoc_csr_bankarray_csrbank2_sel & basesoc_csr_bankarray_interface2_bank_bus_we) & (basesoc_csr_bankarray_interface2_bank_bus_adr[0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank2_out0_we = ((basesoc_csr_bankarray_csrbank2_sel & (~basesoc_csr_bankarray_interface2_bank_bus_we)) & (basesoc_csr_bankarray_interface2_bank_bus_adr[0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank2_out0_w = storage[7:0]; +assign basesoc_csr_bankarray_csrbank3_sel = (basesoc_csr_bankarray_interface3_bank_bus_adr[13:9] == 4'd10); +assign basesoc_csr_bankarray_csrbank3_sector1_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[15:0]; +assign basesoc_csr_bankarray_csrbank3_sector1_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank3_sector1_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank3_sector0_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank3_sector0_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank3_sector0_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank3_base1_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank3_base1_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank3_base1_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank3_base0_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank3_base0_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 2'd3)); +assign basesoc_csr_bankarray_csrbank3_base0_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 2'd3)); +assign sata_mem2sector_start_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[0]; +assign sata_mem2sector_start_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd4)); +assign sata_mem2sector_start_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd4)); +assign basesoc_csr_bankarray_csrbank3_done_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank3_done_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank3_done_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank3_error_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank3_error_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank3_error_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank3_sector1_w = sata_mem2sector_sector_storage[47:32]; +assign basesoc_csr_bankarray_csrbank3_sector0_w = sata_mem2sector_sector_storage[31:0]; +assign basesoc_csr_bankarray_csrbank3_base1_w = sata_mem2sector_base_storage[63:32]; +assign basesoc_csr_bankarray_csrbank3_base0_w = sata_mem2sector_base_storage[31:0]; +assign basesoc_csr_bankarray_csrbank3_done_w = sata_mem2sector_done_status; +assign sata_mem2sector_done_we = basesoc_csr_bankarray_csrbank3_done_we; +assign basesoc_csr_bankarray_csrbank3_error_w = sata_mem2sector_error_status; +assign sata_mem2sector_error_we = basesoc_csr_bankarray_csrbank3_error_we; +assign basesoc_csr_bankarray_csrbank4_sel = (basesoc_csr_bankarray_interface4_bank_bus_adr[13:9] == 4'd8); +assign basesoc_csr_bankarray_csrbank4_enable0_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank4_enable0_re = ((basesoc_csr_bankarray_csrbank4_sel & basesoc_csr_bankarray_interface4_bank_bus_we) & (basesoc_csr_bankarray_interface4_bank_bus_adr[0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank4_enable0_we = ((basesoc_csr_bankarray_csrbank4_sel & (~basesoc_csr_bankarray_interface4_bank_bus_we)) & (basesoc_csr_bankarray_interface4_bank_bus_adr[0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank4_status_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[3:0]; +assign basesoc_csr_bankarray_csrbank4_status_re = ((basesoc_csr_bankarray_csrbank4_sel & basesoc_csr_bankarray_interface4_bank_bus_we) & (basesoc_csr_bankarray_interface4_bank_bus_adr[0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank4_status_we = ((basesoc_csr_bankarray_csrbank4_sel & (~basesoc_csr_bankarray_interface4_bank_bus_we)) & (basesoc_csr_bankarray_interface4_bank_bus_adr[0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank4_enable0_w = litesataphy_enable_storage; +always @(*) begin + litesataphy_status_status <= 4'd0; + litesataphy_status_status[0] <= litesataphy_ready; + litesataphy_status_status[1] <= litesataphy_tx_ready; + litesataphy_status_status[2] <= litesataphy_rx_ready; + litesataphy_status_status[3] <= litesataphy_ctrl_ready; +end +assign basesoc_csr_bankarray_csrbank4_status_w = litesataphy_status_status[3:0]; +assign litesataphy_status_we = basesoc_csr_bankarray_csrbank4_status_we; +assign basesoc_csr_bankarray_csrbank5_sel = (basesoc_csr_bankarray_interface5_bank_bus_adr[13:9] == 4'd9); +assign basesoc_csr_bankarray_csrbank5_sector1_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[15:0]; +assign basesoc_csr_bankarray_csrbank5_sector1_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank5_sector1_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank5_sector0_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank5_sector0_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank5_sector0_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank5_base1_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank5_base1_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank5_base1_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank5_base0_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank5_base0_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 2'd3)); +assign basesoc_csr_bankarray_csrbank5_base0_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 2'd3)); +assign sata_sector2mem_start_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[0]; +assign sata_sector2mem_start_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd4)); +assign sata_sector2mem_start_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd4)); +assign basesoc_csr_bankarray_csrbank5_done_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank5_done_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank5_done_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank5_error_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank5_error_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank5_error_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank5_sector1_w = sata_sector2mem_sector_storage[47:32]; +assign basesoc_csr_bankarray_csrbank5_sector0_w = sata_sector2mem_sector_storage[31:0]; +assign basesoc_csr_bankarray_csrbank5_base1_w = sata_sector2mem_base_storage[63:32]; +assign basesoc_csr_bankarray_csrbank5_base0_w = sata_sector2mem_base_storage[31:0]; +assign basesoc_csr_bankarray_csrbank5_done_w = sata_sector2mem_done_status; +assign sata_sector2mem_done_we = basesoc_csr_bankarray_csrbank5_done_we; +assign basesoc_csr_bankarray_csrbank5_error_w = sata_sector2mem_error_status; +assign sata_sector2mem_error_we = basesoc_csr_bankarray_csrbank5_error_we; +assign basesoc_csr_bankarray_csrbank6_sel = (basesoc_csr_bankarray_interface6_bank_bus_adr[13:9] == 3'd7); +assign basesoc_csr_bankarray_csrbank6_dfii_control0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[3:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_control0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank6_dfii_control0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[5:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 1'd1)); +assign sdram_phaseinjector0_command_issue_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +assign sdram_phaseinjector0_command_issue_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 2'd2)); +assign sdram_phaseinjector0_command_issue_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[13:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 2'd3)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 2'd3)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[2:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd4)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd4)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[5:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd7)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd7)); +assign sdram_phaseinjector1_command_issue_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +assign sdram_phaseinjector1_command_issue_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd8)); +assign sdram_phaseinjector1_command_issue_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd8)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[13:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd9)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd9)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[2:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd10)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd10)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd11)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd11)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd12)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd12)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[5:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd13)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd13)); +assign sdram_phaseinjector2_command_issue_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +assign sdram_phaseinjector2_command_issue_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd14)); +assign sdram_phaseinjector2_command_issue_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd14)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[13:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd15)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd15)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[2:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd16)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd16)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd17)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd17)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd18)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd18)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[5:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd19)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd19)); +assign sdram_phaseinjector3_command_issue_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +assign sdram_phaseinjector3_command_issue_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd20)); +assign sdram_phaseinjector3_command_issue_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd20)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[13:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd21)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd21)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[2:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd22)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd22)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd23)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd23)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd24)); +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd24)); +assign sdram_sel = sdram_storage[0]; +assign sdram_cke = sdram_storage[1]; +assign sdram_odt = sdram_storage[2]; +assign sdram_reset_n = sdram_storage[3]; +assign basesoc_csr_bankarray_csrbank6_dfii_control0_w = sdram_storage[3:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_w = sdram_phaseinjector0_command_storage[5:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_w = sdram_phaseinjector0_address_storage[13:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_w = sdram_phaseinjector0_baddress_storage[2:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_w = sdram_phaseinjector0_wrdata_storage[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_w = sdram_phaseinjector0_rddata_status[31:0]; +assign sdram_phaseinjector0_rddata_we = basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_we; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_w = sdram_phaseinjector1_command_storage[5:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_w = sdram_phaseinjector1_address_storage[13:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_w = sdram_phaseinjector1_baddress_storage[2:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_w = sdram_phaseinjector1_wrdata_storage[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_w = sdram_phaseinjector1_rddata_status[31:0]; +assign sdram_phaseinjector1_rddata_we = basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_we; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_w = sdram_phaseinjector2_command_storage[5:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_w = sdram_phaseinjector2_address_storage[13:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_w = sdram_phaseinjector2_baddress_storage[2:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_w = sdram_phaseinjector2_wrdata_storage[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_w = sdram_phaseinjector2_rddata_status[31:0]; +assign sdram_phaseinjector2_rddata_we = basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_we; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_w = sdram_phaseinjector3_command_storage[5:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_w = sdram_phaseinjector3_address_storage[13:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_w = sdram_phaseinjector3_baddress_storage[2:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_w = sdram_phaseinjector3_wrdata_storage[31:0]; +assign basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_w = sdram_phaseinjector3_rddata_status[31:0]; +assign sdram_phaseinjector3_rddata_we = basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_we; +assign basesoc_csr_bankarray_csrbank7_sel = (basesoc_csr_bankarray_interface7_bank_bus_adr[13:9] == 3'd5); +assign basesoc_csr_bankarray_csrbank7_load0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank7_load0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank7_load0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank7_reload0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank7_reload0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank7_reload0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank7_en0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank7_en0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank7_en0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank7_update_value0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank7_update_value0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 2'd3)); +assign basesoc_csr_bankarray_csrbank7_update_value0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 2'd3)); +assign basesoc_csr_bankarray_csrbank7_value_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank7_value_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd4)); +assign basesoc_csr_bankarray_csrbank7_value_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd4)); +assign basesoc_csr_bankarray_csrbank7_ev_status_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank7_ev_status_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank7_ev_status_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank7_ev_pending_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank7_ev_pending_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank7_ev_pending_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank7_ev_enable0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank7_ev_enable0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd7)); +assign basesoc_csr_bankarray_csrbank7_ev_enable0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd7)); +assign basesoc_csr_bankarray_csrbank7_load0_w = timer_load_storage[31:0]; +assign basesoc_csr_bankarray_csrbank7_reload0_w = timer_reload_storage[31:0]; +assign basesoc_csr_bankarray_csrbank7_en0_w = timer_en_storage; +assign basesoc_csr_bankarray_csrbank7_update_value0_w = timer_update_value_storage; +assign basesoc_csr_bankarray_csrbank7_value_w = timer_value_status[31:0]; +assign timer_value_we = basesoc_csr_bankarray_csrbank7_value_we; +assign timer_status_status = timer_zero0; +assign basesoc_csr_bankarray_csrbank7_ev_status_w = timer_status_status; +assign timer_status_we = basesoc_csr_bankarray_csrbank7_ev_status_we; +assign timer_pending_status = timer_zero1; +assign basesoc_csr_bankarray_csrbank7_ev_pending_w = timer_pending_status; +assign timer_pending_we = basesoc_csr_bankarray_csrbank7_ev_pending_we; +assign timer_zero2 = timer_enable_storage; +assign basesoc_csr_bankarray_csrbank7_ev_enable0_w = timer_enable_storage; +assign basesoc_csr_bankarray_csrbank8_sel = (basesoc_csr_bankarray_interface8_bank_bus_adr[13:9] == 3'd4); +assign uart_rxtx_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[7:0]; +assign uart_rxtx_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 1'd0)); +assign uart_rxtx_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank8_txfull_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank8_txfull_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank8_txfull_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 1'd1)); +assign basesoc_csr_bankarray_csrbank8_rxempty_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank8_rxempty_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank8_rxempty_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 2'd2)); +assign basesoc_csr_bankarray_csrbank8_ev_status_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[1:0]; +assign basesoc_csr_bankarray_csrbank8_ev_status_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 2'd3)); +assign basesoc_csr_bankarray_csrbank8_ev_status_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 2'd3)); +assign basesoc_csr_bankarray_csrbank8_ev_pending_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[1:0]; +assign basesoc_csr_bankarray_csrbank8_ev_pending_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd4)); +assign basesoc_csr_bankarray_csrbank8_ev_pending_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd4)); +assign basesoc_csr_bankarray_csrbank8_ev_enable0_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[1:0]; +assign basesoc_csr_bankarray_csrbank8_ev_enable0_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank8_ev_enable0_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd5)); +assign basesoc_csr_bankarray_csrbank8_txempty_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank8_txempty_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank8_txempty_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd6)); +assign basesoc_csr_bankarray_csrbank8_rxfull_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; +assign basesoc_csr_bankarray_csrbank8_rxfull_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd7)); +assign basesoc_csr_bankarray_csrbank8_rxfull_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd7)); +assign basesoc_csr_bankarray_csrbank8_txfull_w = uart_txfull_status; +assign uart_txfull_we = basesoc_csr_bankarray_csrbank8_txfull_we; +assign basesoc_csr_bankarray_csrbank8_rxempty_w = uart_rxempty_status; +assign uart_rxempty_we = basesoc_csr_bankarray_csrbank8_rxempty_we; +always @(*) begin + uart_status_status <= 2'd0; + uart_status_status[0] <= uart_tx0; + uart_status_status[1] <= uart_rx0; +end +assign basesoc_csr_bankarray_csrbank8_ev_status_w = uart_status_status[1:0]; +assign uart_status_we = basesoc_csr_bankarray_csrbank8_ev_status_we; +always @(*) begin + uart_pending_status <= 2'd0; + uart_pending_status[0] <= uart_tx1; + uart_pending_status[1] <= uart_rx1; +end +assign basesoc_csr_bankarray_csrbank8_ev_pending_w = uart_pending_status[1:0]; +assign uart_pending_we = basesoc_csr_bankarray_csrbank8_ev_pending_we; +assign uart_tx2 = uart_enable_storage[0]; +assign uart_rx2 = uart_enable_storage[1]; +assign basesoc_csr_bankarray_csrbank8_ev_enable0_w = uart_enable_storage[1:0]; +assign basesoc_csr_bankarray_csrbank8_txempty_w = uart_txempty_status; +assign uart_txempty_we = basesoc_csr_bankarray_csrbank8_txempty_we; +assign basesoc_csr_bankarray_csrbank8_rxfull_w = uart_rxfull_status; +assign uart_rxfull_we = basesoc_csr_bankarray_csrbank8_rxfull_we; +assign basesoc_csr_bankarray_csrbank9_sel = (basesoc_csr_bankarray_interface9_bank_bus_adr[13:9] == 2'd3); +assign basesoc_csr_bankarray_csrbank9_tuning_word0_r = basesoc_csr_bankarray_interface9_bank_bus_dat_w[31:0]; +assign basesoc_csr_bankarray_csrbank9_tuning_word0_re = ((basesoc_csr_bankarray_csrbank9_sel & basesoc_csr_bankarray_interface9_bank_bus_we) & (basesoc_csr_bankarray_interface9_bank_bus_adr[0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank9_tuning_word0_we = ((basesoc_csr_bankarray_csrbank9_sel & (~basesoc_csr_bankarray_interface9_bank_bus_we)) & (basesoc_csr_bankarray_interface9_bank_bus_adr[0] == 1'd0)); +assign basesoc_csr_bankarray_csrbank9_tuning_word0_w = uart_phy_storage[31:0]; +assign basesoc_csr_interconnect_adr = basesoc_basesoc_adr; +assign basesoc_csr_interconnect_we = basesoc_basesoc_we; +assign basesoc_csr_interconnect_dat_w = basesoc_basesoc_dat_w; +assign basesoc_basesoc_dat_r = basesoc_csr_interconnect_dat_r; +assign basesoc_csr_bankarray_interface0_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface1_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface2_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface3_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface4_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface5_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface6_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface7_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface8_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface9_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_sram_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface0_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface1_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface2_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface3_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface4_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface5_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface6_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface7_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface8_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface9_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_sram_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface0_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface1_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface2_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface3_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface4_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface5_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface6_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface7_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface8_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface9_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_sram_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_interconnect_dat_r = ((((((((((basesoc_csr_bankarray_interface0_bank_bus_dat_r | basesoc_csr_bankarray_interface1_bank_bus_dat_r) | basesoc_csr_bankarray_interface2_bank_bus_dat_r) | basesoc_csr_bankarray_interface3_bank_bus_dat_r) | basesoc_csr_bankarray_interface4_bank_bus_dat_r) | basesoc_csr_bankarray_interface5_bank_bus_dat_r) | basesoc_csr_bankarray_interface6_bank_bus_dat_r) | basesoc_csr_bankarray_interface7_bank_bus_dat_r) | basesoc_csr_bankarray_interface8_bank_bus_dat_r) | basesoc_csr_bankarray_interface9_bank_bus_dat_r) | basesoc_csr_bankarray_sram_bus_dat_r); +always @(*) begin + rhs_array_muxed0 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 14'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 <= sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 <= sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 <= sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 <= sdram_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= sdram_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 3'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 <= sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 <= sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 <= sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 <= sdram_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= sdram_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 <= sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 <= sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 <= sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 <= sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= sdram_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 <= sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 <= sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 <= sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 <= sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= sdram_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 <= sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 <= sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 <= sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 <= sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 <= sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 <= sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 <= sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 <= sdram_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= sdram_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 <= sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 <= sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 <= sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 <= sdram_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= sdram_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 <= sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 <= sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 <= sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 <= sdram_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 <= sdram_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= sdram_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= sdram_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= sdram_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 <= sdram_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 <= sdram_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 <= sdram_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 <= sdram_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 <= sdram_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 14'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 <= sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 <= sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 <= sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 <= sdram_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= sdram_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 3'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= sdram_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= sdram_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= sdram_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= sdram_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= sdram_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= sdram_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= sdram_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= sdram_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= sdram_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 <= sdram_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 21'd0; + case (subfragments_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (subfragments_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (subfragments_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 21'd0; + case (subfragments_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (subfragments_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (subfragments_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 21'd0; + case (subfragments_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (subfragments_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (subfragments_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 21'd0; + case (subfragments_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (subfragments_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (subfragments_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed24 <= 21'd0; + case (subfragments_roundrobin4_grant) + default: begin + rhs_array_muxed24 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 1'd0; + case (subfragments_roundrobin4_grant) + default: begin + rhs_array_muxed25 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 1'd0; + case (subfragments_roundrobin4_grant) + default: begin + rhs_array_muxed26 <= (((port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((subfragments_locked4 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 21'd0; + case (subfragments_roundrobin5_grant) + default: begin + rhs_array_muxed27 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (subfragments_roundrobin5_grant) + default: begin + rhs_array_muxed28 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (subfragments_roundrobin5_grant) + default: begin + rhs_array_muxed29 <= (((port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((subfragments_locked5 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 21'd0; + case (subfragments_roundrobin6_grant) + default: begin + rhs_array_muxed30 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 1'd0; + case (subfragments_roundrobin6_grant) + default: begin + rhs_array_muxed31 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 <= 1'd0; + case (subfragments_roundrobin6_grant) + default: begin + rhs_array_muxed32 <= (((port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((subfragments_locked6 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 <= 21'd0; + case (subfragments_roundrobin7_grant) + default: begin + rhs_array_muxed33 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 <= 1'd0; + case (subfragments_roundrobin7_grant) + default: begin + rhs_array_muxed34 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 <= 1'd0; + case (subfragments_roundrobin7_grant) + default: begin + rhs_array_muxed35 <= (((port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((subfragments_locked7 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed36 <= 32'd0; + case (basesoc_grant) + 1'd0: begin + rhs_array_muxed36 <= cpu_ibus_adr; + end + 1'd1: begin + rhs_array_muxed36 <= cpu_dbus_adr; + end + 2'd2: begin + rhs_array_muxed36 <= interface0_bus_adr; + end + default: begin + rhs_array_muxed36 <= interface1_bus_adr; + end + endcase +end +always @(*) begin + rhs_array_muxed37 <= 32'd0; + case (basesoc_grant) + 1'd0: begin + rhs_array_muxed37 <= cpu_ibus_dat_w; + end + 1'd1: begin + rhs_array_muxed37 <= cpu_dbus_dat_w; + end + 2'd2: begin + rhs_array_muxed37 <= interface0_bus_dat_w; + end + default: begin + rhs_array_muxed37 <= interface1_bus_dat_w; + end + endcase +end +always @(*) begin + rhs_array_muxed38 <= 4'd0; + case (basesoc_grant) + 1'd0: begin + rhs_array_muxed38 <= cpu_ibus_sel; + end + 1'd1: begin + rhs_array_muxed38 <= cpu_dbus_sel; + end + 2'd2: begin + rhs_array_muxed38 <= interface0_bus_sel; + end + default: begin + rhs_array_muxed38 <= interface1_bus_sel; + end + endcase +end +always @(*) begin + rhs_array_muxed39 <= 1'd0; + case (basesoc_grant) + 1'd0: begin + rhs_array_muxed39 <= cpu_ibus_cyc; + end + 1'd1: begin + rhs_array_muxed39 <= cpu_dbus_cyc; + end + 2'd2: begin + rhs_array_muxed39 <= interface0_bus_cyc; + end + default: begin + rhs_array_muxed39 <= interface1_bus_cyc; + end + endcase +end +always @(*) begin + rhs_array_muxed40 <= 1'd0; + case (basesoc_grant) + 1'd0: begin + rhs_array_muxed40 <= cpu_ibus_stb; + end + 1'd1: begin + rhs_array_muxed40 <= cpu_dbus_stb; + end + 2'd2: begin + rhs_array_muxed40 <= interface0_bus_stb; + end + default: begin + rhs_array_muxed40 <= interface1_bus_stb; + end + endcase +end +always @(*) begin + rhs_array_muxed41 <= 1'd0; + case (basesoc_grant) + 1'd0: begin + rhs_array_muxed41 <= cpu_ibus_we; + end + 1'd1: begin + rhs_array_muxed41 <= cpu_dbus_we; + end + 2'd2: begin + rhs_array_muxed41 <= interface0_bus_we; + end + default: begin + rhs_array_muxed41 <= interface1_bus_we; + end + endcase +end +always @(*) begin + rhs_array_muxed42 <= 3'd0; + case (basesoc_grant) + 1'd0: begin + rhs_array_muxed42 <= cpu_ibus_cti; + end + 1'd1: begin + rhs_array_muxed42 <= cpu_dbus_cti; + end + 2'd2: begin + rhs_array_muxed42 <= interface0_bus_cti; + end + default: begin + rhs_array_muxed42 <= interface1_bus_cti; + end + endcase +end +always @(*) begin + rhs_array_muxed43 <= 2'd0; + case (basesoc_grant) + 1'd0: begin + rhs_array_muxed43 <= cpu_ibus_bte; + end + 1'd1: begin + rhs_array_muxed43 <= cpu_dbus_bte; + end + 2'd2: begin + rhs_array_muxed43 <= interface0_bus_bte; + end + default: begin + rhs_array_muxed43 <= interface1_bus_bte; + end + endcase +end +always @(*) begin + array_muxed0 <= 3'd0; + case (sdram_steerer_sel0) + 1'd0: begin + array_muxed0 <= sdram_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 <= sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 <= sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 <= sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 14'd0; + case (sdram_steerer_sel0) + 1'd0: begin + array_muxed1 <= sdram_nop_a; + end + 1'd1: begin + array_muxed1 <= sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= sdram_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (sdram_steerer_sel0) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (sdram_steerer_sel0) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (sdram_steerer_sel0) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (sdram_steerer_sel0) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (sdram_steerer_sel0) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 <= 3'd0; + case (sdram_steerer_sel1) + 1'd0: begin + array_muxed7 <= sdram_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 <= sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 <= sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 <= sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 <= 14'd0; + case (sdram_steerer_sel1) + 1'd0: begin + array_muxed8 <= sdram_nop_a; + end + 1'd1: begin + array_muxed8 <= sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 <= sdram_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 <= sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 <= 1'd0; + case (sdram_steerer_sel1) + 1'd0: begin + array_muxed9 <= 1'd0; + end + 1'd1: begin + array_muxed9 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 <= 1'd0; + case (sdram_steerer_sel1) + 1'd0: begin + array_muxed10 <= 1'd0; + end + 1'd1: begin + array_muxed10 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 <= 1'd0; + case (sdram_steerer_sel1) + 1'd0: begin + array_muxed11 <= 1'd0; + end + 1'd1: begin + array_muxed11 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 <= 1'd0; + case (sdram_steerer_sel1) + 1'd0: begin + array_muxed12 <= 1'd0; + end + 1'd1: begin + array_muxed12 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 <= 1'd0; + case (sdram_steerer_sel1) + 1'd0: begin + array_muxed13 <= 1'd0; + end + 1'd1: begin + array_muxed13 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed14 <= 3'd0; + case (sdram_steerer_sel2) + 1'd0: begin + array_muxed14 <= sdram_nop_ba[2:0]; + end + 1'd1: begin + array_muxed14 <= sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed14 <= sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed14 <= sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed15 <= 14'd0; + case (sdram_steerer_sel2) + 1'd0: begin + array_muxed15 <= sdram_nop_a; + end + 1'd1: begin + array_muxed15 <= sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed15 <= sdram_choose_req_cmd_payload_a; + end + default: begin + array_muxed15 <= sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed16 <= 1'd0; + case (sdram_steerer_sel2) + 1'd0: begin + array_muxed16 <= 1'd0; + end + 1'd1: begin + array_muxed16 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed16 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); + end + default: begin + array_muxed16 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed17 <= 1'd0; + case (sdram_steerer_sel2) + 1'd0: begin + array_muxed17 <= 1'd0; + end + 1'd1: begin + array_muxed17 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed17 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); + end + default: begin + array_muxed17 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed18 <= 1'd0; + case (sdram_steerer_sel2) + 1'd0: begin + array_muxed18 <= 1'd0; + end + 1'd1: begin + array_muxed18 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed18 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); + end + default: begin + array_muxed18 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed19 <= 1'd0; + case (sdram_steerer_sel2) + 1'd0: begin + array_muxed19 <= 1'd0; + end + 1'd1: begin + array_muxed19 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed19 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed19 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed20 <= 1'd0; + case (sdram_steerer_sel2) + 1'd0: begin + array_muxed20 <= 1'd0; + end + 1'd1: begin + array_muxed20 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed20 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed20 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed21 <= 3'd0; + case (sdram_steerer_sel3) + 1'd0: begin + array_muxed21 <= sdram_nop_ba[2:0]; + end + 1'd1: begin + array_muxed21 <= sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed21 <= sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed21 <= sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed22 <= 14'd0; + case (sdram_steerer_sel3) + 1'd0: begin + array_muxed22 <= sdram_nop_a; + end + 1'd1: begin + array_muxed22 <= sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed22 <= sdram_choose_req_cmd_payload_a; + end + default: begin + array_muxed22 <= sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed23 <= 1'd0; + case (sdram_steerer_sel3) + 1'd0: begin + array_muxed23 <= 1'd0; + end + 1'd1: begin + array_muxed23 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed23 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); + end + default: begin + array_muxed23 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed24 <= 1'd0; + case (sdram_steerer_sel3) + 1'd0: begin + array_muxed24 <= 1'd0; + end + 1'd1: begin + array_muxed24 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed24 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); + end + default: begin + array_muxed24 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed25 <= 1'd0; + case (sdram_steerer_sel3) + 1'd0: begin + array_muxed25 <= 1'd0; + end + 1'd1: begin + array_muxed25 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed25 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); + end + default: begin + array_muxed25 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed26 <= 1'd0; + case (sdram_steerer_sel3) + 1'd0: begin + array_muxed26 <= 1'd0; + end + 1'd1: begin + array_muxed26 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed26 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed26 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed27 <= 1'd0; + case (sdram_steerer_sel3) + 1'd0: begin + array_muxed27 <= 1'd0; + end + 1'd1: begin + array_muxed27 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed27 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed27 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); + end + endcase +end +assign uart_phy_rx = xilinxmultiregimpl0_regs1; +assign xilinxasyncresetsynchronizerimpl0 = (~crg_locked); +assign xilinxasyncresetsynchronizerimpl1 = (~crg_locked); +assign xilinxasyncresetsynchronizerimpl2 = (~crg_locked); +assign xilinxasyncresetsynchronizerimpl3 = (~crg_locked); +assign xilinxasyncresetsynchronizerimpl4 = (~crg_locked); +assign a7litesataphy_tx_init_plllock1 = xilinxmultiregimpl1_regs1; +assign a7litesataphy_tx_init_txresetdone1 = xilinxmultiregimpl2_regs1; +assign a7litesataphy_tx_init_txdlysresetdone1 = xilinxmultiregimpl3_regs1; +assign a7litesataphy_tx_init_txphinitdone1 = xilinxmultiregimpl4_regs1; +assign a7litesataphy_tx_init_txphaligndone1 = xilinxmultiregimpl5_regs1; +assign a7litesataphy_rx_init_rxpmaresetdone1 = xilinxmultiregimpl6_regs1; +assign a7litesataphy_rx_init_plllock1 = xilinxmultiregimpl7_regs1; +assign a7litesataphy_rx_init_rxresetdone1 = xilinxmultiregimpl8_regs1; +assign a7litesataphy_rx_init_rxdlysresetdone1 = xilinxmultiregimpl9_regs1; +assign a7litesataphy_rx_init_rxsyncdone1 = xilinxmultiregimpl10_regs1; +assign a7litesataphy_txpd1 = xilinxmultiregimpl11_regs1; +assign a7litesataphy_txelecidle1 = xilinxmultiregimpl12_regs1; +assign a7litesataphy_pulsesynchronizer0_toggle_o = xilinxmultiregimpl13_regs1; +assign a7litesataphy_pulsesynchronizer1_toggle_o = xilinxmultiregimpl14_regs1; +assign a7litesataphy_pulsesynchronizer2_toggle_o = xilinxmultiregimpl15_regs1; +assign a7litesataphy_rxcominitdet0 = xilinxmultiregimpl16_regs1; +assign a7litesataphy_rxcomwakedet0 = xilinxmultiregimpl17_regs1; +assign a7litesataphy_rxdisperr0 = xilinxmultiregimpl18_regs1; +assign a7litesataphy_rxnotintable0 = xilinxmultiregimpl19_regs1; +assign xilinxasyncresetsynchronizerimpl5 = ((~a7litesataphy_qplllock) | crg_tx_reset); +assign xilinxasyncresetsynchronizerimpl6 = ((~a7litesataphy_qplllock) | crg_rx_reset); +assign datapath_tx_fifo_produce_rdomain = xilinxmultiregimpl20_regs1; +assign datapath_tx_fifo_consume_wdomain = xilinxmultiregimpl21_regs1; +assign datapath_rx_fifo_produce_rdomain = xilinxmultiregimpl22_regs1; +assign datapath_rx_fifo_consume_wdomain = xilinxmultiregimpl23_regs1; + +always @(posedge idelay_clk) begin + if ((crg_reset_counter != 1'd0)) begin + crg_reset_counter <= (crg_reset_counter - 1'd1); + end else begin + crg_ic_reset <= 1'd0; + end + if (idelay_rst) begin + crg_reset_counter <= 4'd15; + crg_ic_reset <= 1'd1; + end +end + +always @(posedge sata_rx_clk) begin + a7litesataphy_source_valid <= 1'd1; + a7litesataphy_source_payload_charisk <= a7litesataphy_rxcharisk; + a7litesataphy_source_payload_data <= a7litesataphy_rxdata; + if ((datapath_rx_sink_sink_valid & datapath_rx_sink_sink_ready)) begin + if ((datapath_rx_sink_sink_payload_charisk != 1'd0)) begin + datapath_rx_byte_alignment <= datapath_rx_sink_sink_payload_charisk; + end + datapath_rx_last_charisk <= datapath_rx_sink_sink_payload_charisk; + datapath_rx_last_data <= datapath_rx_sink_sink_payload_data; + end + if (datapath_rx_converter_converter_source_ready) begin + datapath_rx_converter_converter_strobe_all <= 1'd0; + end + if (datapath_rx_converter_converter_load_part) begin + if (((datapath_rx_converter_converter_demux == 1'd1) | datapath_rx_converter_converter_sink_last)) begin + datapath_rx_converter_converter_demux <= 1'd0; + datapath_rx_converter_converter_strobe_all <= 1'd1; + end else begin + datapath_rx_converter_converter_demux <= (datapath_rx_converter_converter_demux + 1'd1); + end + end + if ((datapath_rx_converter_converter_source_valid & datapath_rx_converter_converter_source_ready)) begin + if ((datapath_rx_converter_converter_sink_valid & datapath_rx_converter_converter_sink_ready)) begin + datapath_rx_converter_converter_source_first <= datapath_rx_converter_converter_sink_first; + datapath_rx_converter_converter_source_last <= datapath_rx_converter_converter_sink_last; + end else begin + datapath_rx_converter_converter_source_first <= 1'd0; + datapath_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((datapath_rx_converter_converter_sink_valid & datapath_rx_converter_converter_sink_ready)) begin + datapath_rx_converter_converter_source_first <= (datapath_rx_converter_converter_sink_first | datapath_rx_converter_converter_source_first); + datapath_rx_converter_converter_source_last <= (datapath_rx_converter_converter_sink_last | datapath_rx_converter_converter_source_last); + end + end + if (datapath_rx_converter_converter_load_part) begin + case (datapath_rx_converter_converter_demux) + 1'd0: begin + datapath_rx_converter_converter_source_payload_data[17:0] <= datapath_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + datapath_rx_converter_converter_source_payload_data[35:18] <= datapath_rx_converter_converter_sink_payload_data; + end + endcase + end + if (datapath_rx_converter_converter_load_part) begin + datapath_rx_converter_converter_source_payload_valid_token_count <= (datapath_rx_converter_converter_demux + 1'd1); + end + if (datapath_rx_converter_reset) begin + datapath_rx_converter_converter_source_payload_data <= 36'd0; + datapath_rx_converter_converter_source_payload_valid_token_count <= 2'd0; + datapath_rx_converter_converter_demux <= 1'd0; + datapath_rx_converter_converter_strobe_all <= 1'd0; + end + datapath_rx_fifo_graycounter0_q_binary <= datapath_rx_fifo_graycounter0_q_next_binary; + datapath_rx_fifo_graycounter0_q <= datapath_rx_fifo_graycounter0_q_next; + if (sata_rx_rst) begin + a7litesataphy_source_valid <= 1'd0; + a7litesataphy_source_payload_data <= 16'd0; + a7litesataphy_source_payload_charisk <= 2'd0; + datapath_rx_byte_alignment <= 2'd0; + datapath_rx_last_charisk <= 2'd0; + datapath_rx_last_data <= 16'd0; + datapath_rx_converter_converter_source_payload_data <= 36'd0; + datapath_rx_converter_converter_source_payload_valid_token_count <= 2'd0; + datapath_rx_converter_converter_demux <= 1'd0; + datapath_rx_converter_converter_strobe_all <= 1'd0; + datapath_rx_fifo_graycounter0_q <= 4'd0; + datapath_rx_fifo_graycounter0_q_binary <= 4'd0; + end + xilinxmultiregimpl23_regs0 <= datapath_rx_fifo_graycounter1_q; + xilinxmultiregimpl23_regs1 <= xilinxmultiregimpl23_regs0; +end + +always @(posedge sata_tx_clk) begin + a7litesataphy_txcharisk <= a7litesataphy_sink_payload_charisk; + a7litesataphy_txdata <= a7litesataphy_sink_payload_data; + a7litesataphy_sink_ready <= 1'd1; + a7litesataphy_pulsesynchronizer0_toggle_o_r <= a7litesataphy_pulsesynchronizer0_toggle_o; + a7litesataphy_pulsesynchronizer1_toggle_o_r <= a7litesataphy_pulsesynchronizer1_toggle_o; + if (a7litesataphy_pulsesynchronizer2_i) begin + a7litesataphy_pulsesynchronizer2_toggle_i <= (~a7litesataphy_pulsesynchronizer2_toggle_i); + end + datapath_tx_fifo_graycounter1_q_binary <= datapath_tx_fifo_graycounter1_q_next_binary; + datapath_tx_fifo_graycounter1_q <= datapath_tx_fifo_graycounter1_q_next; + if ((datapath_tx_converter_converter_source_valid & datapath_tx_converter_converter_source_ready)) begin + if (datapath_tx_converter_converter_last) begin + datapath_tx_converter_converter_mux <= 1'd0; + end else begin + datapath_tx_converter_converter_mux <= (datapath_tx_converter_converter_mux + 1'd1); + end + end + if (sata_tx_rst) begin + a7litesataphy_sink_ready <= 1'd0; + a7litesataphy_txcharisk <= 2'd0; + a7litesataphy_txdata <= 16'd0; + datapath_tx_fifo_graycounter1_q <= 4'd0; + datapath_tx_fifo_graycounter1_q_binary <= 4'd0; + datapath_tx_converter_converter_mux <= 1'd0; + end + xilinxmultiregimpl11_regs0 <= a7litesataphy_txpd0; + xilinxmultiregimpl11_regs1 <= xilinxmultiregimpl11_regs0; + xilinxmultiregimpl12_regs0 <= a7litesataphy_txelecidle0; + xilinxmultiregimpl12_regs1 <= xilinxmultiregimpl12_regs0; + xilinxmultiregimpl13_regs0 <= a7litesataphy_pulsesynchronizer0_toggle_i; + xilinxmultiregimpl13_regs1 <= xilinxmultiregimpl13_regs0; + xilinxmultiregimpl14_regs0 <= a7litesataphy_pulsesynchronizer1_toggle_i; + xilinxmultiregimpl14_regs1 <= xilinxmultiregimpl14_regs0; + xilinxmultiregimpl20_regs0 <= datapath_tx_fifo_graycounter0_q; + xilinxmultiregimpl20_regs1 <= xilinxmultiregimpl20_regs0; +end + +always @(posedge sys_clk) begin + if ((soccontroller_bus_errors != 32'd4294967295)) begin + if (soccontroller_bus_error) begin + soccontroller_bus_errors <= (soccontroller_bus_errors + 1'd1); + end + end + basesoc_ram_bus_ack <= 1'd0; + if (((basesoc_ram_bus_cyc & basesoc_ram_bus_stb) & (~basesoc_ram_bus_ack))) begin + basesoc_ram_bus_ack <= 1'd1; + end + ram_bus_ram_bus_ack <= 1'd0; + if (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & (~ram_bus_ram_bus_ack))) begin + ram_bus_ram_bus_ack <= 1'd1; + end + uart_phy_sink_ready <= 1'd0; + if (((uart_phy_sink_valid & (~uart_phy_tx_busy)) & (~uart_phy_sink_ready))) begin + uart_phy_tx_reg <= uart_phy_sink_payload_data; + uart_phy_tx_bitcount <= 1'd0; + uart_phy_tx_busy <= 1'd1; + serial_tx <= 1'd0; + end else begin + if ((uart_phy_tx_clken & uart_phy_tx_busy)) begin + uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1); + if ((uart_phy_tx_bitcount == 4'd8)) begin + serial_tx <= 1'd1; + end else begin + if ((uart_phy_tx_bitcount == 4'd9)) begin + serial_tx <= 1'd1; + uart_phy_tx_busy <= 1'd0; + uart_phy_sink_ready <= 1'd1; + end else begin + serial_tx <= uart_phy_tx_reg[0]; + uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]}; + end + end + end + end + if (uart_phy_tx_busy) begin + {uart_phy_tx_clken, uart_phy_tx_clkphase} <= (uart_phy_tx_clkphase + uart_phy_storage); + end else begin + {uart_phy_tx_clken, uart_phy_tx_clkphase} <= uart_phy_storage; + end + uart_phy_source_valid <= 1'd0; + uart_phy_rx_r <= uart_phy_rx; + if ((~uart_phy_rx_busy)) begin + if (((~uart_phy_rx) & uart_phy_rx_r)) begin + uart_phy_rx_busy <= 1'd1; + uart_phy_rx_bitcount <= 1'd0; + end + end else begin + if (uart_phy_rx_clken) begin + uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1); + if ((uart_phy_rx_bitcount == 1'd0)) begin + if (uart_phy_rx) begin + uart_phy_rx_busy <= 1'd0; + end + end else begin + if ((uart_phy_rx_bitcount == 4'd9)) begin + uart_phy_rx_busy <= 1'd0; + if (uart_phy_rx) begin + uart_phy_source_payload_data <= uart_phy_rx_reg; + uart_phy_source_valid <= 1'd1; + end + end else begin + uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]}; + end + end + end + end + if (uart_phy_rx_busy) begin + {uart_phy_rx_clken, uart_phy_rx_clkphase} <= (uart_phy_rx_clkphase + uart_phy_storage); + end else begin + {uart_phy_rx_clken, uart_phy_rx_clkphase} <= 32'd2147483648; + end + if (uart_tx_clear) begin + uart_tx_pending <= 1'd0; + end + uart_tx_old_trigger <= uart_tx_trigger; + if (((~uart_tx_trigger) & uart_tx_old_trigger)) begin + uart_tx_pending <= 1'd1; + end + if (uart_rx_clear) begin + uart_rx_pending <= 1'd0; + end + uart_rx_old_trigger <= uart_rx_trigger; + if (((~uart_rx_trigger) & uart_rx_old_trigger)) begin + uart_rx_pending <= 1'd1; + end + if (uart_tx_fifo_syncfifo_re) begin + uart_tx_fifo_readable <= 1'd1; + end else begin + if (uart_tx_fifo_re) begin + uart_tx_fifo_readable <= 1'd0; + end + end + if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin + uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1); + end + if (uart_tx_fifo_do_read) begin + uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1); + end + if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin + if ((~uart_tx_fifo_do_read)) begin + uart_tx_fifo_level0 <= (uart_tx_fifo_level0 + 1'd1); + end + end else begin + if (uart_tx_fifo_do_read) begin + uart_tx_fifo_level0 <= (uart_tx_fifo_level0 - 1'd1); + end + end + if (uart_rx_fifo_syncfifo_re) begin + uart_rx_fifo_readable <= 1'd1; + end else begin + if (uart_rx_fifo_re) begin + uart_rx_fifo_readable <= 1'd0; + end + end + if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin + uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1); + end + if (uart_rx_fifo_do_read) begin + uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1); + end + if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin + if ((~uart_rx_fifo_do_read)) begin + uart_rx_fifo_level0 <= (uart_rx_fifo_level0 + 1'd1); + end + end else begin + if (uart_rx_fifo_do_read) begin + uart_rx_fifo_level0 <= (uart_rx_fifo_level0 - 1'd1); + end + end + if (timer_en_storage) begin + if ((timer_value == 1'd0)) begin + timer_value <= timer_reload_storage; + end else begin + timer_value <= (timer_value - 1'd1); + end + end else begin + timer_value <= timer_load_storage; + end + if (timer_update_value_re) begin + timer_value_status <= timer_value; + end + if (timer_zero_clear) begin + timer_zero_pending <= 1'd0; + end + timer_zero_old_trigger <= timer_zero_trigger; + if (((~timer_zero_trigger) & timer_zero_old_trigger)) begin + timer_zero_pending <= 1'd1; + end + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value0 <= 3'd7; + end + a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value0 <= 3'd7; + end + a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value1 <= 3'd7; + end + a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value1 <= 3'd7; + end + a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value2 <= 3'd7; + end + a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value3 <= 3'd7; + end + a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value2 <= 3'd7; + end + a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value3 <= 3'd7; + end + a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value0 <= 3'd7; + end + a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value1 <= 3'd7; + end + a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value0 <= 3'd7; + end + a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value1 <= 3'd7; + end + a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value0 <= 3'd7; + end + a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value1 <= 3'd7; + end + a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value0 <= 3'd7; + end + a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value1 <= 3'd7; + end + a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value0 <= 3'd7; + end + a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value1 <= 3'd7; + end + a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value0 <= 3'd7; + end + a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value1 <= 3'd7; + end + a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value0 <= 3'd7; + end + a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value1 <= 3'd7; + end + a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value0 <= 3'd7; + end + a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value1 <= 3'd7; + end + a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value0 <= 3'd7; + end + a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value1 <= 3'd7; + end + a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value0 <= 3'd7; + end + a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value1 <= 3'd7; + end + a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value0 <= 3'd7; + end + a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value1 <= 3'd7; + end + a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value0 <= 3'd7; + end + a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value1 <= 3'd7; + end + a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value0 <= 3'd7; + end + a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value1 <= 3'd7; + end + a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value0 <= 3'd7; + end + a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value1 <= 3'd7; + end + a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; + a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); + a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; + a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; + a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; + a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; + a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; + a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; + a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; + a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); + a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; + a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; + if (sdram_inti_p0_rddata_valid) begin + sdram_phaseinjector0_rddata_status <= sdram_inti_p0_rddata; + end + if (sdram_inti_p1_rddata_valid) begin + sdram_phaseinjector1_rddata_status <= sdram_inti_p1_rddata; + end + if (sdram_inti_p2_rddata_valid) begin + sdram_phaseinjector2_rddata_status <= sdram_inti_p2_rddata; + end + if (sdram_inti_p3_rddata_valid) begin + sdram_phaseinjector3_rddata_status <= sdram_inti_p3_rddata; + end + if ((sdram_timer_wait & (~sdram_timer_done0))) begin + sdram_timer_count1 <= (sdram_timer_count1 - 1'd1); + end else begin + sdram_timer_count1 <= 10'd624; + end + sdram_postponer_req_o <= 1'd0; + if (sdram_postponer_req_i) begin + sdram_postponer_count <= (sdram_postponer_count - 1'd1); + if ((sdram_postponer_count == 1'd0)) begin + sdram_postponer_count <= 1'd0; + sdram_postponer_req_o <= 1'd1; + end + end + if (sdram_sequencer_start0) begin + sdram_sequencer_count <= 1'd0; + end else begin + if (sdram_sequencer_done1) begin + if ((sdram_sequencer_count != 1'd0)) begin + sdram_sequencer_count <= (sdram_sequencer_count - 1'd1); + end + end + end + sdram_cmd_payload_a <= 1'd0; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd0; + sdram_cmd_payload_we <= 1'd0; + sdram_sequencer_done1 <= 1'd0; + if ((sdram_sequencer_start1 & (sdram_sequencer_counter == 1'd0))) begin + sdram_cmd_payload_a <= 11'd1024; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd1; + sdram_cmd_payload_we <= 1'd1; + end + if ((sdram_sequencer_counter == 2'd2)) begin + sdram_cmd_payload_a <= 1'd0; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd1; + sdram_cmd_payload_ras <= 1'd1; + sdram_cmd_payload_we <= 1'd0; + end + if ((sdram_sequencer_counter == 6'd34)) begin + sdram_cmd_payload_a <= 1'd0; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd0; + sdram_cmd_payload_we <= 1'd0; + sdram_sequencer_done1 <= 1'd1; + end + if ((sdram_sequencer_counter == 6'd34)) begin + sdram_sequencer_counter <= 1'd0; + end else begin + if ((sdram_sequencer_counter != 1'd0)) begin + sdram_sequencer_counter <= (sdram_sequencer_counter + 1'd1); + end else begin + if (sdram_sequencer_start1) begin + sdram_sequencer_counter <= 1'd1; + end + end + end + if ((sdram_zqcs_timer_wait & (~sdram_zqcs_timer_done0))) begin + sdram_zqcs_timer_count1 <= (sdram_zqcs_timer_count1 - 1'd1); + end else begin + sdram_zqcs_timer_count1 <= 27'd79999999; + end + sdram_zqcs_executer_done <= 1'd0; + if ((sdram_zqcs_executer_start & (sdram_zqcs_executer_counter == 1'd0))) begin + sdram_cmd_payload_a <= 11'd1024; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd1; + sdram_cmd_payload_we <= 1'd1; + end + if ((sdram_zqcs_executer_counter == 2'd2)) begin + sdram_cmd_payload_a <= 1'd0; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd0; + sdram_cmd_payload_we <= 1'd1; + end + if ((sdram_zqcs_executer_counter == 5'd18)) begin + sdram_cmd_payload_a <= 1'd0; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd0; + sdram_cmd_payload_we <= 1'd0; + sdram_zqcs_executer_done <= 1'd1; + end + if ((sdram_zqcs_executer_counter == 5'd18)) begin + sdram_zqcs_executer_counter <= 1'd0; + end else begin + if ((sdram_zqcs_executer_counter != 1'd0)) begin + sdram_zqcs_executer_counter <= (sdram_zqcs_executer_counter + 1'd1); + end else begin + if (sdram_zqcs_executer_start) begin + sdram_zqcs_executer_counter <= 1'd1; + end + end + end + subfragments_refresher_state <= subfragments_refresher_next_state; + if (sdram_bankmachine0_row_close) begin + sdram_bankmachine0_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine0_row_open) begin + sdram_bankmachine0_row_opened <= 1'd1; + sdram_bankmachine0_row <= sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine0_cmd_buffer_lookahead_produce <= (sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine0_cmd_buffer_lookahead_consume <= (sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready)) begin + sdram_bankmachine0_cmd_buffer_source_valid <= sdram_bankmachine0_cmd_buffer_sink_valid; + sdram_bankmachine0_cmd_buffer_source_first <= sdram_bankmachine0_cmd_buffer_sink_first; + sdram_bankmachine0_cmd_buffer_source_last <= sdram_bankmachine0_cmd_buffer_sink_last; + sdram_bankmachine0_cmd_buffer_source_payload_we <= sdram_bankmachine0_cmd_buffer_sink_payload_we; + sdram_bankmachine0_cmd_buffer_source_payload_addr <= sdram_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine0_twtpcon_valid) begin + sdram_bankmachine0_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine0_twtpcon_ready)) begin + sdram_bankmachine0_twtpcon_count <= (sdram_bankmachine0_twtpcon_count - 1'd1); + if ((sdram_bankmachine0_twtpcon_count == 1'd1)) begin + sdram_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine0_trccon_valid) begin + sdram_bankmachine0_trccon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine0_trccon_ready <= 1'd1; + end else begin + sdram_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine0_trccon_ready)) begin + sdram_bankmachine0_trccon_count <= (sdram_bankmachine0_trccon_count - 1'd1); + if ((sdram_bankmachine0_trccon_count == 1'd1)) begin + sdram_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine0_trascon_valid) begin + sdram_bankmachine0_trascon_count <= 2'd3; + if (1'd0) begin + sdram_bankmachine0_trascon_ready <= 1'd1; + end else begin + sdram_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine0_trascon_ready)) begin + sdram_bankmachine0_trascon_count <= (sdram_bankmachine0_trascon_count - 1'd1); + if ((sdram_bankmachine0_trascon_count == 1'd1)) begin + sdram_bankmachine0_trascon_ready <= 1'd1; + end + end + end + subfragments_bankmachine0_state <= subfragments_bankmachine0_next_state; + if (sdram_bankmachine1_row_close) begin + sdram_bankmachine1_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine1_row_open) begin + sdram_bankmachine1_row_opened <= 1'd1; + sdram_bankmachine1_row <= sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine1_cmd_buffer_lookahead_produce <= (sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine1_cmd_buffer_lookahead_consume <= (sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready)) begin + sdram_bankmachine1_cmd_buffer_source_valid <= sdram_bankmachine1_cmd_buffer_sink_valid; + sdram_bankmachine1_cmd_buffer_source_first <= sdram_bankmachine1_cmd_buffer_sink_first; + sdram_bankmachine1_cmd_buffer_source_last <= sdram_bankmachine1_cmd_buffer_sink_last; + sdram_bankmachine1_cmd_buffer_source_payload_we <= sdram_bankmachine1_cmd_buffer_sink_payload_we; + sdram_bankmachine1_cmd_buffer_source_payload_addr <= sdram_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine1_twtpcon_valid) begin + sdram_bankmachine1_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine1_twtpcon_ready)) begin + sdram_bankmachine1_twtpcon_count <= (sdram_bankmachine1_twtpcon_count - 1'd1); + if ((sdram_bankmachine1_twtpcon_count == 1'd1)) begin + sdram_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine1_trccon_valid) begin + sdram_bankmachine1_trccon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine1_trccon_ready <= 1'd1; + end else begin + sdram_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine1_trccon_ready)) begin + sdram_bankmachine1_trccon_count <= (sdram_bankmachine1_trccon_count - 1'd1); + if ((sdram_bankmachine1_trccon_count == 1'd1)) begin + sdram_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine1_trascon_valid) begin + sdram_bankmachine1_trascon_count <= 2'd3; + if (1'd0) begin + sdram_bankmachine1_trascon_ready <= 1'd1; + end else begin + sdram_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine1_trascon_ready)) begin + sdram_bankmachine1_trascon_count <= (sdram_bankmachine1_trascon_count - 1'd1); + if ((sdram_bankmachine1_trascon_count == 1'd1)) begin + sdram_bankmachine1_trascon_ready <= 1'd1; + end + end + end + subfragments_bankmachine1_state <= subfragments_bankmachine1_next_state; + if (sdram_bankmachine2_row_close) begin + sdram_bankmachine2_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine2_row_open) begin + sdram_bankmachine2_row_opened <= 1'd1; + sdram_bankmachine2_row <= sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine2_cmd_buffer_lookahead_produce <= (sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine2_cmd_buffer_lookahead_consume <= (sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready)) begin + sdram_bankmachine2_cmd_buffer_source_valid <= sdram_bankmachine2_cmd_buffer_sink_valid; + sdram_bankmachine2_cmd_buffer_source_first <= sdram_bankmachine2_cmd_buffer_sink_first; + sdram_bankmachine2_cmd_buffer_source_last <= sdram_bankmachine2_cmd_buffer_sink_last; + sdram_bankmachine2_cmd_buffer_source_payload_we <= sdram_bankmachine2_cmd_buffer_sink_payload_we; + sdram_bankmachine2_cmd_buffer_source_payload_addr <= sdram_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine2_twtpcon_valid) begin + sdram_bankmachine2_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine2_twtpcon_ready)) begin + sdram_bankmachine2_twtpcon_count <= (sdram_bankmachine2_twtpcon_count - 1'd1); + if ((sdram_bankmachine2_twtpcon_count == 1'd1)) begin + sdram_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine2_trccon_valid) begin + sdram_bankmachine2_trccon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine2_trccon_ready <= 1'd1; + end else begin + sdram_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine2_trccon_ready)) begin + sdram_bankmachine2_trccon_count <= (sdram_bankmachine2_trccon_count - 1'd1); + if ((sdram_bankmachine2_trccon_count == 1'd1)) begin + sdram_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine2_trascon_valid) begin + sdram_bankmachine2_trascon_count <= 2'd3; + if (1'd0) begin + sdram_bankmachine2_trascon_ready <= 1'd1; + end else begin + sdram_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine2_trascon_ready)) begin + sdram_bankmachine2_trascon_count <= (sdram_bankmachine2_trascon_count - 1'd1); + if ((sdram_bankmachine2_trascon_count == 1'd1)) begin + sdram_bankmachine2_trascon_ready <= 1'd1; + end + end + end + subfragments_bankmachine2_state <= subfragments_bankmachine2_next_state; + if (sdram_bankmachine3_row_close) begin + sdram_bankmachine3_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine3_row_open) begin + sdram_bankmachine3_row_opened <= 1'd1; + sdram_bankmachine3_row <= sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine3_cmd_buffer_lookahead_produce <= (sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine3_cmd_buffer_lookahead_consume <= (sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready)) begin + sdram_bankmachine3_cmd_buffer_source_valid <= sdram_bankmachine3_cmd_buffer_sink_valid; + sdram_bankmachine3_cmd_buffer_source_first <= sdram_bankmachine3_cmd_buffer_sink_first; + sdram_bankmachine3_cmd_buffer_source_last <= sdram_bankmachine3_cmd_buffer_sink_last; + sdram_bankmachine3_cmd_buffer_source_payload_we <= sdram_bankmachine3_cmd_buffer_sink_payload_we; + sdram_bankmachine3_cmd_buffer_source_payload_addr <= sdram_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine3_twtpcon_valid) begin + sdram_bankmachine3_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine3_twtpcon_ready)) begin + sdram_bankmachine3_twtpcon_count <= (sdram_bankmachine3_twtpcon_count - 1'd1); + if ((sdram_bankmachine3_twtpcon_count == 1'd1)) begin + sdram_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine3_trccon_valid) begin + sdram_bankmachine3_trccon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine3_trccon_ready <= 1'd1; + end else begin + sdram_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine3_trccon_ready)) begin + sdram_bankmachine3_trccon_count <= (sdram_bankmachine3_trccon_count - 1'd1); + if ((sdram_bankmachine3_trccon_count == 1'd1)) begin + sdram_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine3_trascon_valid) begin + sdram_bankmachine3_trascon_count <= 2'd3; + if (1'd0) begin + sdram_bankmachine3_trascon_ready <= 1'd1; + end else begin + sdram_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine3_trascon_ready)) begin + sdram_bankmachine3_trascon_count <= (sdram_bankmachine3_trascon_count - 1'd1); + if ((sdram_bankmachine3_trascon_count == 1'd1)) begin + sdram_bankmachine3_trascon_ready <= 1'd1; + end + end + end + subfragments_bankmachine3_state <= subfragments_bankmachine3_next_state; + if (sdram_bankmachine4_row_close) begin + sdram_bankmachine4_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine4_row_open) begin + sdram_bankmachine4_row_opened <= 1'd1; + sdram_bankmachine4_row <= sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine4_cmd_buffer_lookahead_produce <= (sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine4_cmd_buffer_lookahead_consume <= (sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine4_cmd_buffer_lookahead_level <= (sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine4_cmd_buffer_lookahead_level <= (sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine4_cmd_buffer_source_valid) | sdram_bankmachine4_cmd_buffer_source_ready)) begin + sdram_bankmachine4_cmd_buffer_source_valid <= sdram_bankmachine4_cmd_buffer_sink_valid; + sdram_bankmachine4_cmd_buffer_source_first <= sdram_bankmachine4_cmd_buffer_sink_first; + sdram_bankmachine4_cmd_buffer_source_last <= sdram_bankmachine4_cmd_buffer_sink_last; + sdram_bankmachine4_cmd_buffer_source_payload_we <= sdram_bankmachine4_cmd_buffer_sink_payload_we; + sdram_bankmachine4_cmd_buffer_source_payload_addr <= sdram_bankmachine4_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine4_twtpcon_valid) begin + sdram_bankmachine4_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine4_twtpcon_ready)) begin + sdram_bankmachine4_twtpcon_count <= (sdram_bankmachine4_twtpcon_count - 1'd1); + if ((sdram_bankmachine4_twtpcon_count == 1'd1)) begin + sdram_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine4_trccon_valid) begin + sdram_bankmachine4_trccon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine4_trccon_ready <= 1'd1; + end else begin + sdram_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine4_trccon_ready)) begin + sdram_bankmachine4_trccon_count <= (sdram_bankmachine4_trccon_count - 1'd1); + if ((sdram_bankmachine4_trccon_count == 1'd1)) begin + sdram_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine4_trascon_valid) begin + sdram_bankmachine4_trascon_count <= 2'd3; + if (1'd0) begin + sdram_bankmachine4_trascon_ready <= 1'd1; + end else begin + sdram_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine4_trascon_ready)) begin + sdram_bankmachine4_trascon_count <= (sdram_bankmachine4_trascon_count - 1'd1); + if ((sdram_bankmachine4_trascon_count == 1'd1)) begin + sdram_bankmachine4_trascon_ready <= 1'd1; + end + end + end + subfragments_bankmachine4_state <= subfragments_bankmachine4_next_state; + if (sdram_bankmachine5_row_close) begin + sdram_bankmachine5_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine5_row_open) begin + sdram_bankmachine5_row_opened <= 1'd1; + sdram_bankmachine5_row <= sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine5_cmd_buffer_lookahead_produce <= (sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine5_cmd_buffer_lookahead_consume <= (sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine5_cmd_buffer_lookahead_level <= (sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine5_cmd_buffer_lookahead_level <= (sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine5_cmd_buffer_source_valid) | sdram_bankmachine5_cmd_buffer_source_ready)) begin + sdram_bankmachine5_cmd_buffer_source_valid <= sdram_bankmachine5_cmd_buffer_sink_valid; + sdram_bankmachine5_cmd_buffer_source_first <= sdram_bankmachine5_cmd_buffer_sink_first; + sdram_bankmachine5_cmd_buffer_source_last <= sdram_bankmachine5_cmd_buffer_sink_last; + sdram_bankmachine5_cmd_buffer_source_payload_we <= sdram_bankmachine5_cmd_buffer_sink_payload_we; + sdram_bankmachine5_cmd_buffer_source_payload_addr <= sdram_bankmachine5_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine5_twtpcon_valid) begin + sdram_bankmachine5_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine5_twtpcon_ready)) begin + sdram_bankmachine5_twtpcon_count <= (sdram_bankmachine5_twtpcon_count - 1'd1); + if ((sdram_bankmachine5_twtpcon_count == 1'd1)) begin + sdram_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine5_trccon_valid) begin + sdram_bankmachine5_trccon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine5_trccon_ready <= 1'd1; + end else begin + sdram_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine5_trccon_ready)) begin + sdram_bankmachine5_trccon_count <= (sdram_bankmachine5_trccon_count - 1'd1); + if ((sdram_bankmachine5_trccon_count == 1'd1)) begin + sdram_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine5_trascon_valid) begin + sdram_bankmachine5_trascon_count <= 2'd3; + if (1'd0) begin + sdram_bankmachine5_trascon_ready <= 1'd1; + end else begin + sdram_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine5_trascon_ready)) begin + sdram_bankmachine5_trascon_count <= (sdram_bankmachine5_trascon_count - 1'd1); + if ((sdram_bankmachine5_trascon_count == 1'd1)) begin + sdram_bankmachine5_trascon_ready <= 1'd1; + end + end + end + subfragments_bankmachine5_state <= subfragments_bankmachine5_next_state; + if (sdram_bankmachine6_row_close) begin + sdram_bankmachine6_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine6_row_open) begin + sdram_bankmachine6_row_opened <= 1'd1; + sdram_bankmachine6_row <= sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine6_cmd_buffer_lookahead_produce <= (sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine6_cmd_buffer_lookahead_consume <= (sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine6_cmd_buffer_lookahead_level <= (sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine6_cmd_buffer_lookahead_level <= (sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine6_cmd_buffer_source_valid) | sdram_bankmachine6_cmd_buffer_source_ready)) begin + sdram_bankmachine6_cmd_buffer_source_valid <= sdram_bankmachine6_cmd_buffer_sink_valid; + sdram_bankmachine6_cmd_buffer_source_first <= sdram_bankmachine6_cmd_buffer_sink_first; + sdram_bankmachine6_cmd_buffer_source_last <= sdram_bankmachine6_cmd_buffer_sink_last; + sdram_bankmachine6_cmd_buffer_source_payload_we <= sdram_bankmachine6_cmd_buffer_sink_payload_we; + sdram_bankmachine6_cmd_buffer_source_payload_addr <= sdram_bankmachine6_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine6_twtpcon_valid) begin + sdram_bankmachine6_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine6_twtpcon_ready)) begin + sdram_bankmachine6_twtpcon_count <= (sdram_bankmachine6_twtpcon_count - 1'd1); + if ((sdram_bankmachine6_twtpcon_count == 1'd1)) begin + sdram_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine6_trccon_valid) begin + sdram_bankmachine6_trccon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine6_trccon_ready <= 1'd1; + end else begin + sdram_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine6_trccon_ready)) begin + sdram_bankmachine6_trccon_count <= (sdram_bankmachine6_trccon_count - 1'd1); + if ((sdram_bankmachine6_trccon_count == 1'd1)) begin + sdram_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine6_trascon_valid) begin + sdram_bankmachine6_trascon_count <= 2'd3; + if (1'd0) begin + sdram_bankmachine6_trascon_ready <= 1'd1; + end else begin + sdram_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine6_trascon_ready)) begin + sdram_bankmachine6_trascon_count <= (sdram_bankmachine6_trascon_count - 1'd1); + if ((sdram_bankmachine6_trascon_count == 1'd1)) begin + sdram_bankmachine6_trascon_ready <= 1'd1; + end + end + end + subfragments_bankmachine6_state <= subfragments_bankmachine6_next_state; + if (sdram_bankmachine7_row_close) begin + sdram_bankmachine7_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine7_row_open) begin + sdram_bankmachine7_row_opened <= 1'd1; + sdram_bankmachine7_row <= sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine7_cmd_buffer_lookahead_produce <= (sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine7_cmd_buffer_lookahead_consume <= (sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine7_cmd_buffer_lookahead_level <= (sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine7_cmd_buffer_lookahead_level <= (sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine7_cmd_buffer_source_valid) | sdram_bankmachine7_cmd_buffer_source_ready)) begin + sdram_bankmachine7_cmd_buffer_source_valid <= sdram_bankmachine7_cmd_buffer_sink_valid; + sdram_bankmachine7_cmd_buffer_source_first <= sdram_bankmachine7_cmd_buffer_sink_first; + sdram_bankmachine7_cmd_buffer_source_last <= sdram_bankmachine7_cmd_buffer_sink_last; + sdram_bankmachine7_cmd_buffer_source_payload_we <= sdram_bankmachine7_cmd_buffer_sink_payload_we; + sdram_bankmachine7_cmd_buffer_source_payload_addr <= sdram_bankmachine7_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine7_twtpcon_valid) begin + sdram_bankmachine7_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine7_twtpcon_ready)) begin + sdram_bankmachine7_twtpcon_count <= (sdram_bankmachine7_twtpcon_count - 1'd1); + if ((sdram_bankmachine7_twtpcon_count == 1'd1)) begin + sdram_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine7_trccon_valid) begin + sdram_bankmachine7_trccon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine7_trccon_ready <= 1'd1; + end else begin + sdram_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine7_trccon_ready)) begin + sdram_bankmachine7_trccon_count <= (sdram_bankmachine7_trccon_count - 1'd1); + if ((sdram_bankmachine7_trccon_count == 1'd1)) begin + sdram_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (sdram_bankmachine7_trascon_valid) begin + sdram_bankmachine7_trascon_count <= 2'd3; + if (1'd0) begin + sdram_bankmachine7_trascon_ready <= 1'd1; + end else begin + sdram_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine7_trascon_ready)) begin + sdram_bankmachine7_trascon_count <= (sdram_bankmachine7_trascon_count - 1'd1); + if ((sdram_bankmachine7_trascon_count == 1'd1)) begin + sdram_bankmachine7_trascon_ready <= 1'd1; + end + end + end + subfragments_bankmachine7_state <= subfragments_bankmachine7_next_state; + if ((~sdram_en0)) begin + sdram_time0 <= 5'd31; + end else begin + if ((~sdram_max_time0)) begin + sdram_time0 <= (sdram_time0 - 1'd1); + end + end + if ((~sdram_en1)) begin + sdram_time1 <= 4'd15; + end else begin + if ((~sdram_max_time1)) begin + sdram_time1 <= (sdram_time1 - 1'd1); + end + end + if (sdram_choose_cmd_ce) begin + case (sdram_choose_cmd_grant) + 1'd0: begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end else begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end else begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end else begin + if (sdram_choose_cmd_request[4]) begin + sdram_choose_cmd_grant <= 3'd4; + end else begin + if (sdram_choose_cmd_request[5]) begin + sdram_choose_cmd_grant <= 3'd5; + end else begin + if (sdram_choose_cmd_request[6]) begin + sdram_choose_cmd_grant <= 3'd6; + end else begin + if (sdram_choose_cmd_request[7]) begin + sdram_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end else begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end else begin + if (sdram_choose_cmd_request[4]) begin + sdram_choose_cmd_grant <= 3'd4; + end else begin + if (sdram_choose_cmd_request[5]) begin + sdram_choose_cmd_grant <= 3'd5; + end else begin + if (sdram_choose_cmd_request[6]) begin + sdram_choose_cmd_grant <= 3'd6; + end else begin + if (sdram_choose_cmd_request[7]) begin + sdram_choose_cmd_grant <= 3'd7; + end else begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end else begin + if (sdram_choose_cmd_request[4]) begin + sdram_choose_cmd_grant <= 3'd4; + end else begin + if (sdram_choose_cmd_request[5]) begin + sdram_choose_cmd_grant <= 3'd5; + end else begin + if (sdram_choose_cmd_request[6]) begin + sdram_choose_cmd_grant <= 3'd6; + end else begin + if (sdram_choose_cmd_request[7]) begin + sdram_choose_cmd_grant <= 3'd7; + end else begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end else begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (sdram_choose_cmd_request[4]) begin + sdram_choose_cmd_grant <= 3'd4; + end else begin + if (sdram_choose_cmd_request[5]) begin + sdram_choose_cmd_grant <= 3'd5; + end else begin + if (sdram_choose_cmd_request[6]) begin + sdram_choose_cmd_grant <= 3'd6; + end else begin + if (sdram_choose_cmd_request[7]) begin + sdram_choose_cmd_grant <= 3'd7; + end else begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end else begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end else begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (sdram_choose_cmd_request[5]) begin + sdram_choose_cmd_grant <= 3'd5; + end else begin + if (sdram_choose_cmd_request[6]) begin + sdram_choose_cmd_grant <= 3'd6; + end else begin + if (sdram_choose_cmd_request[7]) begin + sdram_choose_cmd_grant <= 3'd7; + end else begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end else begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end else begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end else begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (sdram_choose_cmd_request[6]) begin + sdram_choose_cmd_grant <= 3'd6; + end else begin + if (sdram_choose_cmd_request[7]) begin + sdram_choose_cmd_grant <= 3'd7; + end else begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end else begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end else begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end else begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end else begin + if (sdram_choose_cmd_request[4]) begin + sdram_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (sdram_choose_cmd_request[7]) begin + sdram_choose_cmd_grant <= 3'd7; + end else begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end else begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end else begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end else begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end else begin + if (sdram_choose_cmd_request[4]) begin + sdram_choose_cmd_grant <= 3'd4; + end else begin + if (sdram_choose_cmd_request[5]) begin + sdram_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end else begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end else begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end else begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end else begin + if (sdram_choose_cmd_request[4]) begin + sdram_choose_cmd_grant <= 3'd4; + end else begin + if (sdram_choose_cmd_request[5]) begin + sdram_choose_cmd_grant <= 3'd5; + end else begin + if (sdram_choose_cmd_request[6]) begin + sdram_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (sdram_choose_req_ce) begin + case (sdram_choose_req_grant) + 1'd0: begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end else begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end else begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end else begin + if (sdram_choose_req_request[4]) begin + sdram_choose_req_grant <= 3'd4; + end else begin + if (sdram_choose_req_request[5]) begin + sdram_choose_req_grant <= 3'd5; + end else begin + if (sdram_choose_req_request[6]) begin + sdram_choose_req_grant <= 3'd6; + end else begin + if (sdram_choose_req_request[7]) begin + sdram_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end else begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end else begin + if (sdram_choose_req_request[4]) begin + sdram_choose_req_grant <= 3'd4; + end else begin + if (sdram_choose_req_request[5]) begin + sdram_choose_req_grant <= 3'd5; + end else begin + if (sdram_choose_req_request[6]) begin + sdram_choose_req_grant <= 3'd6; + end else begin + if (sdram_choose_req_request[7]) begin + sdram_choose_req_grant <= 3'd7; + end else begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end else begin + if (sdram_choose_req_request[4]) begin + sdram_choose_req_grant <= 3'd4; + end else begin + if (sdram_choose_req_request[5]) begin + sdram_choose_req_grant <= 3'd5; + end else begin + if (sdram_choose_req_request[6]) begin + sdram_choose_req_grant <= 3'd6; + end else begin + if (sdram_choose_req_request[7]) begin + sdram_choose_req_grant <= 3'd7; + end else begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end else begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (sdram_choose_req_request[4]) begin + sdram_choose_req_grant <= 3'd4; + end else begin + if (sdram_choose_req_request[5]) begin + sdram_choose_req_grant <= 3'd5; + end else begin + if (sdram_choose_req_request[6]) begin + sdram_choose_req_grant <= 3'd6; + end else begin + if (sdram_choose_req_request[7]) begin + sdram_choose_req_grant <= 3'd7; + end else begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end else begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end else begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (sdram_choose_req_request[5]) begin + sdram_choose_req_grant <= 3'd5; + end else begin + if (sdram_choose_req_request[6]) begin + sdram_choose_req_grant <= 3'd6; + end else begin + if (sdram_choose_req_request[7]) begin + sdram_choose_req_grant <= 3'd7; + end else begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end else begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end else begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end else begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (sdram_choose_req_request[6]) begin + sdram_choose_req_grant <= 3'd6; + end else begin + if (sdram_choose_req_request[7]) begin + sdram_choose_req_grant <= 3'd7; + end else begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end else begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end else begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end else begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end else begin + if (sdram_choose_req_request[4]) begin + sdram_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (sdram_choose_req_request[7]) begin + sdram_choose_req_grant <= 3'd7; + end else begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end else begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end else begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end else begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end else begin + if (sdram_choose_req_request[4]) begin + sdram_choose_req_grant <= 3'd4; + end else begin + if (sdram_choose_req_request[5]) begin + sdram_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end else begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end else begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end else begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end else begin + if (sdram_choose_req_request[4]) begin + sdram_choose_req_grant <= 3'd4; + end else begin + if (sdram_choose_req_request[5]) begin + sdram_choose_req_grant <= 3'd5; + end else begin + if (sdram_choose_req_request[6]) begin + sdram_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + sdram_dfi_p0_cs_n <= 1'd0; + sdram_dfi_p0_bank <= array_muxed0; + sdram_dfi_p0_address <= array_muxed1; + sdram_dfi_p0_cas_n <= (~array_muxed2); + sdram_dfi_p0_ras_n <= (~array_muxed3); + sdram_dfi_p0_we_n <= (~array_muxed4); + sdram_dfi_p0_rddata_en <= array_muxed5; + sdram_dfi_p0_wrdata_en <= array_muxed6; + sdram_dfi_p1_cs_n <= 1'd0; + sdram_dfi_p1_bank <= array_muxed7; + sdram_dfi_p1_address <= array_muxed8; + sdram_dfi_p1_cas_n <= (~array_muxed9); + sdram_dfi_p1_ras_n <= (~array_muxed10); + sdram_dfi_p1_we_n <= (~array_muxed11); + sdram_dfi_p1_rddata_en <= array_muxed12; + sdram_dfi_p1_wrdata_en <= array_muxed13; + sdram_dfi_p2_cs_n <= 1'd0; + sdram_dfi_p2_bank <= array_muxed14; + sdram_dfi_p2_address <= array_muxed15; + sdram_dfi_p2_cas_n <= (~array_muxed16); + sdram_dfi_p2_ras_n <= (~array_muxed17); + sdram_dfi_p2_we_n <= (~array_muxed18); + sdram_dfi_p2_rddata_en <= array_muxed19; + sdram_dfi_p2_wrdata_en <= array_muxed20; + sdram_dfi_p3_cs_n <= 1'd0; + sdram_dfi_p3_bank <= array_muxed21; + sdram_dfi_p3_address <= array_muxed22; + sdram_dfi_p3_cas_n <= (~array_muxed23); + sdram_dfi_p3_ras_n <= (~array_muxed24); + sdram_dfi_p3_we_n <= (~array_muxed25); + sdram_dfi_p3_rddata_en <= array_muxed26; + sdram_dfi_p3_wrdata_en <= array_muxed27; + if (sdram_trrdcon_valid) begin + sdram_trrdcon_count <= 1'd1; + if (1'd0) begin + sdram_trrdcon_ready <= 1'd1; + end else begin + sdram_trrdcon_ready <= 1'd0; + end + end else begin + if ((~sdram_trrdcon_ready)) begin + sdram_trrdcon_count <= (sdram_trrdcon_count - 1'd1); + if ((sdram_trrdcon_count == 1'd1)) begin + sdram_trrdcon_ready <= 1'd1; + end + end + end + sdram_tfawcon_window <= {sdram_tfawcon_window, sdram_tfawcon_valid}; + if ((sdram_tfawcon_count < 3'd4)) begin + if ((sdram_tfawcon_count == 2'd3)) begin + sdram_tfawcon_ready <= (~sdram_tfawcon_valid); + end else begin + sdram_tfawcon_ready <= 1'd1; + end + end + if (sdram_tccdcon_valid) begin + sdram_tccdcon_count <= 1'd0; + if (1'd1) begin + sdram_tccdcon_ready <= 1'd1; + end else begin + sdram_tccdcon_ready <= 1'd0; + end + end else begin + if ((~sdram_tccdcon_ready)) begin + sdram_tccdcon_count <= (sdram_tccdcon_count - 1'd1); + if ((sdram_tccdcon_count == 1'd1)) begin + sdram_tccdcon_ready <= 1'd1; + end + end + end + if (sdram_twtrcon_valid) begin + sdram_twtrcon_count <= 3'd4; + if (1'd0) begin + sdram_twtrcon_ready <= 1'd1; + end else begin + sdram_twtrcon_ready <= 1'd0; + end + end else begin + if ((~sdram_twtrcon_ready)) begin + sdram_twtrcon_count <= (sdram_twtrcon_count - 1'd1); + if ((sdram_twtrcon_count == 1'd1)) begin + sdram_twtrcon_ready <= 1'd1; + end + end + end + subfragments_multiplexer_state <= subfragments_multiplexer_next_state; + subfragments_new_master_wdata_ready0 <= ((((((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_wdata_ready)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_wdata_ready)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_wdata_ready)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_wdata_ready)) | ((subfragments_roundrobin4_grant == 1'd0) & sdram_interface_bank4_wdata_ready)) | ((subfragments_roundrobin5_grant == 1'd0) & sdram_interface_bank5_wdata_ready)) | ((subfragments_roundrobin6_grant == 1'd0) & sdram_interface_bank6_wdata_ready)) | ((subfragments_roundrobin7_grant == 1'd0) & sdram_interface_bank7_wdata_ready)); + subfragments_new_master_wdata_ready1 <= subfragments_new_master_wdata_ready0; + subfragments_new_master_rdata_valid0 <= ((((((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_rdata_valid)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_rdata_valid)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_rdata_valid)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_rdata_valid)) | ((subfragments_roundrobin4_grant == 1'd0) & sdram_interface_bank4_rdata_valid)) | ((subfragments_roundrobin5_grant == 1'd0) & sdram_interface_bank5_rdata_valid)) | ((subfragments_roundrobin6_grant == 1'd0) & sdram_interface_bank6_rdata_valid)) | ((subfragments_roundrobin7_grant == 1'd0) & sdram_interface_bank7_rdata_valid)); + subfragments_new_master_rdata_valid1 <= subfragments_new_master_rdata_valid0; + subfragments_new_master_rdata_valid2 <= subfragments_new_master_rdata_valid1; + subfragments_new_master_rdata_valid3 <= subfragments_new_master_rdata_valid2; + subfragments_new_master_rdata_valid4 <= subfragments_new_master_rdata_valid3; + subfragments_new_master_rdata_valid5 <= subfragments_new_master_rdata_valid4; + subfragments_new_master_rdata_valid6 <= subfragments_new_master_rdata_valid5; + subfragments_new_master_rdata_valid7 <= subfragments_new_master_rdata_valid6; + subfragments_new_master_rdata_valid8 <= subfragments_new_master_rdata_valid7; + adr_offset_r <= wb_sdram_adr[1:0]; + subfragments_fullmemorywe_state <= subfragments_fullmemorywe_next_state; + if (interface_ack) begin + cmd_consumed <= 1'd0; + wdata_consumed <= 1'd0; + end else begin + if ((port_cmd_valid & port_cmd_ready)) begin + cmd_consumed <= 1'd1; + end + if ((port_wdata_valid & port_wdata_ready)) begin + wdata_consumed <= 1'd1; + end + end + a7litesataphy_tx_init_gttxreset0 <= a7litesataphy_tx_init_gttxreset1; + a7litesataphy_tx_init_gttxpd0 <= a7litesataphy_tx_init_gttxpd1; + a7litesataphy_tx_init_txdlysreset0 <= a7litesataphy_tx_init_txdlysreset1; + a7litesataphy_tx_init_txphinit0 <= a7litesataphy_tx_init_txphinit1; + a7litesataphy_tx_init_txphalign0 <= a7litesataphy_tx_init_txphalign1; + a7litesataphy_tx_init_txdlyen0 <= a7litesataphy_tx_init_txdlyen1; + a7litesataphy_tx_init_txuserrdy0 <= a7litesataphy_tx_init_txuserrdy1; + a7litesataphy_tx_init_txphaligndone_r <= a7litesataphy_tx_init_txphaligndone1; + subfragments_litesataphy_gtptxinit_state <= subfragments_litesataphy_gtptxinit_next_state; + if (a7litesataphy_tx_init_reset) begin + subfragments_litesataphy_gtptxinit_state <= 4'd0; + end + if (a7litesataphy_tx_init_init_delay_wait) begin + if ((~a7litesataphy_tx_init_init_delay_done)) begin + a7litesataphy_tx_init_init_delay_count <= (a7litesataphy_tx_init_init_delay_count - 1'd1); + end + end else begin + a7litesataphy_tx_init_init_delay_count <= 6'd40; + end + if (a7litesataphy_tx_init_watchdog_wait) begin + if ((~a7litesataphy_tx_init_watchdog_done)) begin + a7litesataphy_tx_init_watchdog_count <= (a7litesataphy_tx_init_watchdog_count - 1'd1); + end + end else begin + a7litesataphy_tx_init_watchdog_count <= 17'd80000; + end + a7litesataphy_rx_init_rxpmaresetdone_r <= a7litesataphy_rx_init_rxpmaresetdone1; + a7litesataphy_rx_init_gtrxreset0 <= a7litesataphy_rx_init_gtrxreset1; + a7litesataphy_rx_init_gtrxpd0 <= a7litesataphy_rx_init_gtrxpd1; + a7litesataphy_rx_init_rxdlysreset0 <= a7litesataphy_rx_init_rxdlysreset1; + a7litesataphy_rx_init_rxphalign0 <= a7litesataphy_rx_init_rxphalign1; + a7litesataphy_rx_init_rxuserrdy0 <= a7litesataphy_rx_init_rxuserrdy1; + subfragments_litesataphy_gtprxinit_state <= subfragments_litesataphy_gtprxinit_next_state; + if (a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value_ce) begin + a7litesataphy_rx_init_drpvalue <= a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value; + end + if (a7litesataphy_rx_init_reset) begin + a7litesataphy_rx_init_drpvalue <= 16'd0; + subfragments_litesataphy_gtprxinit_state <= 4'd0; + end + if (a7litesataphy_rx_init_init_delay_wait) begin + if ((~a7litesataphy_rx_init_init_delay_done)) begin + a7litesataphy_rx_init_init_delay_count <= (a7litesataphy_rx_init_init_delay_count - 1'd1); + end + end else begin + a7litesataphy_rx_init_init_delay_count <= 6'd40; + end + if (a7litesataphy_rx_init_watchdog_wait) begin + if ((~a7litesataphy_rx_init_watchdog_done)) begin + a7litesataphy_rx_init_watchdog_count <= (a7litesataphy_rx_init_watchdog_count - 1'd1); + end + end else begin + a7litesataphy_rx_init_watchdog_count <= 19'd320000; + end + a7litesataphy_i_d0 <= a7litesataphy_tx_cominit_stb; + a7litesataphy_i_d1 <= a7litesataphy_tx_comwake_stb; + if (a7litesataphy_pulsesynchronizer0_i) begin + a7litesataphy_pulsesynchronizer0_toggle_i <= (~a7litesataphy_pulsesynchronizer0_toggle_i); + end + if (a7litesataphy_pulsesynchronizer1_i) begin + a7litesataphy_pulsesynchronizer1_toggle_i <= (~a7litesataphy_pulsesynchronizer1_toggle_i); + end + a7litesataphy_pulsesynchronizer2_toggle_o_r <= a7litesataphy_pulsesynchronizer2_toggle_o; + a7litesataphy_tx_idle <= ctrl_tx_idle; + crg_rx_reset <= ctrl_rx_reset; + crg_tx_reset <= ctrl_tx_reset; + if (ctrl_align_timer_wait) begin + if ((~ctrl_align_timer_done)) begin + ctrl_align_timer_count <= (ctrl_align_timer_count - 1'd1); + end + end else begin + ctrl_align_timer_count <= 17'd69840; + end + if (ctrl_retry_timer_wait) begin + if ((~ctrl_retry_timer_done)) begin + ctrl_retry_timer_count <= (ctrl_retry_timer_count - 1'd1); + end + end else begin + ctrl_retry_timer_count <= 20'd800000; + end + subfragments_litesataphy_state <= subfragments_litesataphy_next_state; + if (ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0) begin + ctrl_align_count <= ctrl_align_count_subfragments_litesataphyctrl_next_value0; + end + if (a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1) begin + a7litesataphy_rx_polarity <= a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1; + end + if (a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value_ce2) begin + a7litesataphy_tx_polarity <= a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value2; + end + if (ctrl_reset) begin + a7litesataphy_tx_polarity <= 1'd0; + a7litesataphy_rx_polarity <= 1'd0; + ctrl_align_count <= 4'd0; + subfragments_litesataphy_state <= 4'd0; + end + if (ctrl_stability_timer_wait) begin + if ((~ctrl_stability_timer_done)) begin + ctrl_stability_timer_count <= (ctrl_stability_timer_count - 1'd1); + end + end else begin + ctrl_stability_timer_count <= 19'd400000; + end + datapath_tx_fifo_graycounter0_q_binary <= datapath_tx_fifo_graycounter0_q_next_binary; + datapath_tx_fifo_graycounter0_q <= datapath_tx_fifo_graycounter0_q_next; + datapath_rx_fifo_graycounter1_q_binary <= datapath_rx_fifo_graycounter1_q_next_binary; + datapath_rx_fifo_graycounter1_q <= datapath_rx_fifo_graycounter1_q_next; + if (datapath_align_timer_wait) begin + if ((~datapath_align_timer_done)) begin + datapath_align_timer_count <= (datapath_align_timer_count - 1'd1); + end + end else begin + datapath_align_timer_count <= 13'd4096; + end + if ((~(link_litesatalinktx_fsm_is_ongoing0 | link_litesatalinktx_fsm_is_ongoing1))) begin + link_litesatalinktx_error <= (link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive == 32'd3048576380)); + end + if (link_litesatalinktx_crc_ce) begin + link_litesatalinktx_crc_reg_i <= link_litesatalinktx_crc_next; + end + if (link_litesatalinktx_crc_reset) begin + link_litesatalinktx_crc_reg_i <= 32'd1379029042; + end + subfragments_litesatalinktx_litesatacrcinserter_state <= subfragments_litesatalinktx_litesatacrcinserter_next_state; + if (link_litesatalinktx_scrambler_ce) begin + link_litesatalinktx_scrambler_context <= link_litesatalinktx_scrambler_next_value[31:16]; + end + if (link_litesatalinktx_scrambler_reset) begin + link_litesatalinktx_scrambler_context <= 16'd61686; + end + subfragments_litesatalinktx_fsm_state <= subfragments_litesatalinktx_fsm_next_state; + if (((~link_tx_source_valid) | link_tx_source_ready)) begin + link_tx_source_valid <= link_tx_sink_valid; + link_tx_source_first <= link_tx_sink_first; + link_tx_source_last <= link_tx_sink_last; + link_tx_source_payload_data <= link_tx_sink_payload_data; + link_tx_source_payload_charisk <= link_tx_sink_payload_charisk; + end + if ((link_tx_align_source_valid & link_tx_align_source_ready)) begin + link_tx_align_cnt <= (link_tx_align_cnt + 1'd1); + end + if ((link_rx_cont_sink_valid & link_rx_cont_sink_ready)) begin + if (link_rx_cont_is_cont) begin + link_rx_cont_in_cont <= 1'd1; + end else begin + if ((~link_rx_cont_is_data)) begin + link_rx_cont_in_cont <= 1'd0; + end + end + end + if ((link_rx_cont_sink_valid & link_rx_cont_sink_ready)) begin + if (((~link_rx_cont_is_data) & (~link_rx_cont_is_cont))) begin + link_rx_cont_last_primitive <= link_rx_cont_sink_payload_data; + end + end + if (((link_litesatalinkrx_crc_source_source_valid & link_litesatalinkrx_crc_source_source_last) & link_litesatalinkrx_crc_source_source_ready)) begin + link_litesatalinkrx_crc_error <= link_litesatalinkrx_crc_source_source_payload_error; + end + if (link_litesatalinkrx_data_valid) begin + link_litesatalinkrx_descrambler_sink_payload_data <= link_litesatalinkrx_sink_sink_payload_data; + end + if (link_litesatalinkrx_descrambler_ce) begin + link_litesatalinkrx_descrambler_context <= link_litesatalinkrx_descrambler_next_value[31:16]; + end + if (link_litesatalinkrx_descrambler_reset) begin + link_litesatalinkrx_descrambler_context <= 16'd61686; + end + if (link_litesatalinkrx_crc_crc_ce) begin + link_litesatalinkrx_crc_crc_reg_i <= link_litesatalinkrx_crc_crc_next; + end + if (link_litesatalinkrx_crc_crc_reset) begin + link_litesatalinkrx_crc_crc_reg_i <= 32'd1379029042; + end + if (((link_litesatalinkrx_crc_syncfifo_syncfifo_we & link_litesatalinkrx_crc_syncfifo_syncfifo_writable) & (~link_litesatalinkrx_crc_syncfifo_replace))) begin + link_litesatalinkrx_crc_syncfifo_produce <= (link_litesatalinkrx_crc_syncfifo_produce + 1'd1); + end + if (link_litesatalinkrx_crc_syncfifo_do_read) begin + link_litesatalinkrx_crc_syncfifo_consume <= (link_litesatalinkrx_crc_syncfifo_consume + 1'd1); + end + if (((link_litesatalinkrx_crc_syncfifo_syncfifo_we & link_litesatalinkrx_crc_syncfifo_syncfifo_writable) & (~link_litesatalinkrx_crc_syncfifo_replace))) begin + if ((~link_litesatalinkrx_crc_syncfifo_do_read)) begin + link_litesatalinkrx_crc_syncfifo_level <= (link_litesatalinkrx_crc_syncfifo_level + 1'd1); + end + end else begin + if (link_litesatalinkrx_crc_syncfifo_do_read) begin + link_litesatalinkrx_crc_syncfifo_level <= (link_litesatalinkrx_crc_syncfifo_level - 1'd1); + end + end + if (link_litesatalinkrx_crc_fifo_reset) begin + link_litesatalinkrx_crc_syncfifo_level <= 2'd0; + link_litesatalinkrx_crc_syncfifo_produce <= 1'd0; + link_litesatalinkrx_crc_syncfifo_consume <= 1'd0; + end + subfragments_litesatalinkrx_litesatacrcchecker_state <= subfragments_litesatalinkrx_litesatacrcchecker_next_state; + subfragments_litesatalinkrx_fsm_state <= subfragments_litesatalinkrx_fsm_next_state; + if (((~link_rx_source_valid) | link_rx_source_ready)) begin + link_rx_source_valid <= link_rx_sink_valid; + link_rx_source_first <= link_rx_sink_first; + link_rx_source_last <= link_rx_sink_last; + link_rx_source_payload_data <= link_rx_sink_payload_data; + link_rx_source_payload_charisk <= link_rx_sink_payload_charisk; + end + if (((link_rx_buffer_syncfifo_we & link_rx_buffer_syncfifo_writable) & (~link_rx_buffer_replace))) begin + link_rx_buffer_produce <= (link_rx_buffer_produce + 1'd1); + end + if (link_rx_buffer_do_read) begin + link_rx_buffer_consume <= (link_rx_buffer_consume + 1'd1); + end + if (((link_rx_buffer_syncfifo_we & link_rx_buffer_syncfifo_writable) & (~link_rx_buffer_replace))) begin + if ((~link_rx_buffer_do_read)) begin + link_rx_buffer_level <= (link_rx_buffer_level + 1'd1); + end + end else begin + if (link_rx_buffer_do_read) begin + link_rx_buffer_level <= (link_rx_buffer_level - 1'd1); + end + end + if (transport_tx_counter_reset) begin + transport_tx_counter <= 1'd0; + end else begin + if (transport_tx_counter_ce) begin + transport_tx_counter <= (transport_tx_counter + 1'd1); + end + end + if (transport_tx_update_fis_type) begin + transport_tx_fis_type <= link_rx_buffer_source_payload_data[7:0]; + end + subfragments_litesatatransporttx_state <= subfragments_litesatatransporttx_next_state; + if (transport_rx_counter_reset) begin + transport_rx_counter <= 1'd0; + end else begin + if (transport_rx_counter_ce) begin + transport_rx_counter <= (transport_rx_counter + 1'd1); + end + end + if (transport_rx_update_fis_type) begin + transport_rx_fis_type <= link_rx_buffer_source_payload_data[7:0]; + end + if (transport_rx_cmd_receive) begin + case (transport_rx_counter) + 1'd0: begin + transport_rx_encoded_cmd[31:0] <= link_rx_buffer_source_payload_data; + end + 1'd1: begin + transport_rx_encoded_cmd[63:32] <= link_rx_buffer_source_payload_data; + end + 2'd2: begin + transport_rx_encoded_cmd[95:64] <= link_rx_buffer_source_payload_data; + end + 2'd3: begin + transport_rx_encoded_cmd[127:96] <= link_rx_buffer_source_payload_data; + end + 3'd4: begin + transport_rx_encoded_cmd[159:128] <= link_rx_buffer_source_payload_data; + end + endcase + end + subfragments_litesatatransportrx_state <= subfragments_litesatatransportrx_next_state; + if (command_tx_is_ongoing0) begin + command_tx_is_write <= command_tx_sink_param_write; + command_tx_is_read <= command_tx_sink_param_read; + command_tx_is_identify <= command_tx_sink_param_identify; + end + subfragments_litesatacommandtx_state <= subfragments_litesatacommandtx_next_state; + if (command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce) begin + command_tx_dwords_counter <= command_tx_dwords_counter_subfragments_litesatacommandtx_next_value; + end + if (command_rx_from_tx_payload_read) begin + command_rx_read_ndwords <= ((command_rx_from_tx_payload_count * 8'd128) - 1'd1); + end + if (command_rx_clr_d2h_error) begin + command_rx_d2h_error <= 1'd0; + end else begin + if (command_rx_set_d2h_error) begin + command_rx_d2h_error <= 1'd1; + end + end + if (command_rx_clr_read_error) begin + command_rx_read_error <= 1'd0; + end else begin + if (command_rx_set_read_error) begin + command_rx_read_error <= 1'd1; + end + end + if (command_rx_update_d2h) begin + command_rx_d2h_status <= transport_rx_source_param_status; + command_rx_d2h_errors <= transport_rx_source_param_errors; + end + if (command_rx_is_ongoing) begin + command_rx_is_identify <= command_rx_from_tx_payload_identify; + end + subfragments_litesatacommandrx_state <= subfragments_litesatacommandrx_next_state; + if (command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce) begin + command_rx_dwords_counter <= command_rx_dwords_counter_subfragments_litesatacommandrx_next_value; + end + if (subfragments_done0) begin + subfragments_ongoing0 <= 1'd0; + end else begin + if (litesatauserport0_sink_valid) begin + subfragments_ongoing0 <= 1'd1; + end + end + if (subfragments_done1) begin + subfragments_ongoing1 <= 1'd0; + end else begin + if (litesatauserport1_sink_valid) begin + subfragments_ongoing1 <= 1'd1; + end + end + case (subfragments_grant) + 1'd0: begin + if ((~subfragments_request[0])) begin + if (subfragments_request[1]) begin + subfragments_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~subfragments_request[1])) begin + if (subfragments_request[0]) begin + subfragments_grant <= 1'd0; + end + end + end + endcase + if (((sata_sector2mem_buf_syncfifo_we & sata_sector2mem_buf_syncfifo_writable) & (~sata_sector2mem_buf_replace))) begin + sata_sector2mem_buf_produce <= (sata_sector2mem_buf_produce + 1'd1); + end + if (sata_sector2mem_buf_do_read) begin + sata_sector2mem_buf_consume <= (sata_sector2mem_buf_consume + 1'd1); + end + if (((sata_sector2mem_buf_syncfifo_we & sata_sector2mem_buf_syncfifo_writable) & (~sata_sector2mem_buf_replace))) begin + if ((~sata_sector2mem_buf_do_read)) begin + sata_sector2mem_buf_level <= (sata_sector2mem_buf_level + 1'd1); + end + end else begin + if (sata_sector2mem_buf_do_read) begin + sata_sector2mem_buf_level <= (sata_sector2mem_buf_level - 1'd1); + end + end + subfragments_litesatasector2memdma_state <= subfragments_litesatasector2memdma_next_state; + if (sata_sector2mem_count_subfragments_next_value_ce0) begin + sata_sector2mem_count <= sata_sector2mem_count_subfragments_next_value0; + end + if (sata_sector2mem_error_status_subfragments_next_value_ce1) begin + sata_sector2mem_error_status <= sata_sector2mem_error_status_subfragments_next_value1; + end + subfragments_wishbonedmareader_state <= subfragments_wishbonedmareader_next_state; + if (sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value_ce) begin + sata_mem2sector_dma_data <= sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value; + end + if (((sata_mem2sector_buf_syncfifo_we & sata_mem2sector_buf_syncfifo_writable) & (~sata_mem2sector_buf_replace))) begin + sata_mem2sector_buf_produce <= (sata_mem2sector_buf_produce + 1'd1); + end + if (sata_mem2sector_buf_do_read) begin + sata_mem2sector_buf_consume <= (sata_mem2sector_buf_consume + 1'd1); + end + if (((sata_mem2sector_buf_syncfifo_we & sata_mem2sector_buf_syncfifo_writable) & (~sata_mem2sector_buf_replace))) begin + if ((~sata_mem2sector_buf_do_read)) begin + sata_mem2sector_buf_level <= (sata_mem2sector_buf_level + 1'd1); + end + end else begin + if (sata_mem2sector_buf_do_read) begin + sata_mem2sector_buf_level <= (sata_mem2sector_buf_level - 1'd1); + end + end + subfragments_fsm_state <= subfragments_fsm_next_state; + if (sata_mem2sector_count_subfragments_fsm_next_value_ce0) begin + sata_mem2sector_count <= sata_mem2sector_count_subfragments_fsm_next_value0; + end + if (sata_mem2sector_error_status_subfragments_fsm_next_value_ce1) begin + sata_mem2sector_error_status <= sata_mem2sector_error_status_subfragments_fsm_next_value1; + end + if (done) begin + chaser <= {chaser, (~chaser[7])}; + end + if (re) begin + mode <= 1'd1; + end + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); + end + end else begin + count <= 23'd5000000; + end + basesoc_state <= basesoc_next_state; + if (basesoc_basesoc_dat_w_basesoc_next_value_ce0) begin + basesoc_basesoc_dat_w <= basesoc_basesoc_dat_w_basesoc_next_value0; + end + if (basesoc_basesoc_adr_basesoc_next_value_ce1) begin + basesoc_basesoc_adr <= basesoc_basesoc_adr_basesoc_next_value1; + end + if (basesoc_basesoc_we_basesoc_next_value_ce2) begin + basesoc_basesoc_we <= basesoc_basesoc_we_basesoc_next_value2; + end + case (basesoc_grant) + 1'd0: begin + if ((~basesoc_request[0])) begin + if (basesoc_request[1]) begin + basesoc_grant <= 1'd1; + end else begin + if (basesoc_request[2]) begin + basesoc_grant <= 2'd2; + end else begin + if (basesoc_request[3]) begin + basesoc_grant <= 2'd3; + end + end + end + end + end + 1'd1: begin + if ((~basesoc_request[1])) begin + if (basesoc_request[2]) begin + basesoc_grant <= 2'd2; + end else begin + if (basesoc_request[3]) begin + basesoc_grant <= 2'd3; + end else begin + if (basesoc_request[0]) begin + basesoc_grant <= 1'd0; + end + end + end + end + end + 2'd2: begin + if ((~basesoc_request[2])) begin + if (basesoc_request[3]) begin + basesoc_grant <= 2'd3; + end else begin + if (basesoc_request[0]) begin + basesoc_grant <= 1'd0; + end else begin + if (basesoc_request[1]) begin + basesoc_grant <= 1'd1; + end + end + end + end + end + 2'd3: begin + if ((~basesoc_request[3])) begin + if (basesoc_request[0]) begin + basesoc_grant <= 1'd0; + end else begin + if (basesoc_request[1]) begin + basesoc_grant <= 1'd1; + end else begin + if (basesoc_request[2]) begin + basesoc_grant <= 2'd2; + end + end + end + end + end + endcase + basesoc_slave_sel_r <= basesoc_slave_sel; + if (basesoc_wait) begin + if ((~basesoc_done)) begin + basesoc_count <= (basesoc_count - 1'd1); + end + end else begin + basesoc_count <= 20'd1000000; + end + basesoc_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank0_sel) begin + case (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0]) + 1'd0: begin + basesoc_csr_bankarray_interface0_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank0_reset0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface0_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank0_scratch0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface0_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank0_bus_errors_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank0_reset0_re) begin + soccontroller_reset_storage <= basesoc_csr_bankarray_csrbank0_reset0_r; + end + soccontroller_reset_re <= basesoc_csr_bankarray_csrbank0_reset0_re; + if (basesoc_csr_bankarray_csrbank0_scratch0_re) begin + soccontroller_scratch_storage[31:0] <= basesoc_csr_bankarray_csrbank0_scratch0_r; + end + soccontroller_scratch_re <= basesoc_csr_bankarray_csrbank0_scratch0_re; + soccontroller_bus_errors_re <= basesoc_csr_bankarray_csrbank0_bus_errors_re; + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank1_sel) begin + case (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0]) + 1'd0: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_rst0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_wlevel_en0_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_dly_sel0_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + end + 3'd7: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd8: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + end + 4'd9: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + end + 4'd10: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + end + 4'd11: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_rdphase0_w; + end + 4'd12: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_wrphase0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank1_rst0_re) begin + a7ddrphy_rst_storage <= basesoc_csr_bankarray_csrbank1_rst0_r; + end + a7ddrphy_rst_re <= basesoc_csr_bankarray_csrbank1_rst0_re; + if (basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_re) begin + a7ddrphy_half_sys8x_taps_storage[4:0] <= basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_r; + end + a7ddrphy_half_sys8x_taps_re <= basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_re; + if (basesoc_csr_bankarray_csrbank1_wlevel_en0_re) begin + a7ddrphy_wlevel_en_storage <= basesoc_csr_bankarray_csrbank1_wlevel_en0_r; + end + a7ddrphy_wlevel_en_re <= basesoc_csr_bankarray_csrbank1_wlevel_en0_re; + if (basesoc_csr_bankarray_csrbank1_dly_sel0_re) begin + a7ddrphy_dly_sel_storage[1:0] <= basesoc_csr_bankarray_csrbank1_dly_sel0_r; + end + a7ddrphy_dly_sel_re <= basesoc_csr_bankarray_csrbank1_dly_sel0_re; + if (basesoc_csr_bankarray_csrbank1_rdphase0_re) begin + a7ddrphy_rdphase_storage[1:0] <= basesoc_csr_bankarray_csrbank1_rdphase0_r; + end + a7ddrphy_rdphase_re <= basesoc_csr_bankarray_csrbank1_rdphase0_re; + if (basesoc_csr_bankarray_csrbank1_wrphase0_re) begin + a7ddrphy_wrphase_storage[1:0] <= basesoc_csr_bankarray_csrbank1_wrphase0_r; + end + a7ddrphy_wrphase_re <= basesoc_csr_bankarray_csrbank1_wrphase0_re; + basesoc_csr_bankarray_sel_r <= basesoc_csr_bankarray_sel; + basesoc_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank2_sel) begin + case (basesoc_csr_bankarray_interface2_bank_bus_adr[0]) + 1'd0: begin + basesoc_csr_bankarray_interface2_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank2_out0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank2_out0_re) begin + storage[7:0] <= basesoc_csr_bankarray_csrbank2_out0_r; + end + re <= basesoc_csr_bankarray_csrbank2_out0_re; + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank3_sel) begin + case (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0]) + 1'd0: begin + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_sector1_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_sector0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_base1_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_base0_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= sata_mem2sector_start_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_done_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_error_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank3_sector1_re) begin + sata_mem2sector_sector_storage[47:32] <= basesoc_csr_bankarray_csrbank3_sector1_r; + end + if (basesoc_csr_bankarray_csrbank3_sector0_re) begin + sata_mem2sector_sector_storage[31:0] <= basesoc_csr_bankarray_csrbank3_sector0_r; + end + sata_mem2sector_sector_re <= basesoc_csr_bankarray_csrbank3_sector0_re; + if (basesoc_csr_bankarray_csrbank3_base1_re) begin + sata_mem2sector_base_storage[63:32] <= basesoc_csr_bankarray_csrbank3_base1_r; + end + if (basesoc_csr_bankarray_csrbank3_base0_re) begin + sata_mem2sector_base_storage[31:0] <= basesoc_csr_bankarray_csrbank3_base0_r; + end + sata_mem2sector_base_re <= basesoc_csr_bankarray_csrbank3_base0_re; + sata_mem2sector_done_re <= basesoc_csr_bankarray_csrbank3_done_re; + sata_mem2sector_error_re <= basesoc_csr_bankarray_csrbank3_error_re; + basesoc_csr_bankarray_interface4_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank4_sel) begin + case (basesoc_csr_bankarray_interface4_bank_bus_adr[0]) + 1'd0: begin + basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_enable0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_status_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank4_enable0_re) begin + litesataphy_enable_storage <= basesoc_csr_bankarray_csrbank4_enable0_r; + end + litesataphy_enable_re <= basesoc_csr_bankarray_csrbank4_enable0_re; + litesataphy_status_re <= basesoc_csr_bankarray_csrbank4_status_re; + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank5_sel) begin + case (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0]) + 1'd0: begin + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_sector1_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_sector0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_base1_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_base0_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= sata_sector2mem_start_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_done_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_error_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank5_sector1_re) begin + sata_sector2mem_sector_storage[47:32] <= basesoc_csr_bankarray_csrbank5_sector1_r; + end + if (basesoc_csr_bankarray_csrbank5_sector0_re) begin + sata_sector2mem_sector_storage[31:0] <= basesoc_csr_bankarray_csrbank5_sector0_r; + end + sata_sector2mem_sector_re <= basesoc_csr_bankarray_csrbank5_sector0_re; + if (basesoc_csr_bankarray_csrbank5_base1_re) begin + sata_sector2mem_base_storage[63:32] <= basesoc_csr_bankarray_csrbank5_base1_r; + end + if (basesoc_csr_bankarray_csrbank5_base0_re) begin + sata_sector2mem_base_storage[31:0] <= basesoc_csr_bankarray_csrbank5_base0_r; + end + sata_sector2mem_base_re <= basesoc_csr_bankarray_csrbank5_base0_re; + sata_sector2mem_done_re <= basesoc_csr_bankarray_csrbank5_done_re; + sata_sector2mem_error_re <= basesoc_csr_bankarray_csrbank5_error_re; + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank6_sel) begin + case (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0]) + 1'd0: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_control0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= sdram_phaseinjector0_command_issue_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_w; + end + 3'd7: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_w; + end + 4'd8: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= sdram_phaseinjector1_command_issue_w; + end + 4'd9: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_w; + end + 4'd10: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_w; + end + 4'd11: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_w; + end + 4'd12: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_w; + end + 4'd13: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_w; + end + 4'd14: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= sdram_phaseinjector2_command_issue_w; + end + 4'd15: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_w; + end + 5'd16: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_w; + end + 5'd17: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_w; + end + 5'd18: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_w; + end + 5'd19: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_w; + end + 5'd20: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= sdram_phaseinjector3_command_issue_w; + end + 5'd21: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_w; + end + 5'd22: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_w; + end + 5'd23: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_w; + end + 5'd24: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank6_dfii_control0_re) begin + sdram_storage[3:0] <= basesoc_csr_bankarray_csrbank6_dfii_control0_r; + end + sdram_re <= basesoc_csr_bankarray_csrbank6_dfii_control0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_re) begin + sdram_phaseinjector0_command_storage[5:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_r; + end + sdram_phaseinjector0_command_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_re) begin + sdram_phaseinjector0_address_storage[13:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_r; + end + sdram_phaseinjector0_address_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_re) begin + sdram_phaseinjector0_baddress_storage[2:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_r; + end + sdram_phaseinjector0_baddress_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_re) begin + sdram_phaseinjector0_wrdata_storage[31:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_r; + end + sdram_phaseinjector0_wrdata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_re; + sdram_phaseinjector0_rddata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_re) begin + sdram_phaseinjector1_command_storage[5:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_r; + end + sdram_phaseinjector1_command_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_re) begin + sdram_phaseinjector1_address_storage[13:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_r; + end + sdram_phaseinjector1_address_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_re) begin + sdram_phaseinjector1_baddress_storage[2:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_r; + end + sdram_phaseinjector1_baddress_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_re) begin + sdram_phaseinjector1_wrdata_storage[31:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_r; + end + sdram_phaseinjector1_wrdata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_re; + sdram_phaseinjector1_rddata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_re) begin + sdram_phaseinjector2_command_storage[5:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_r; + end + sdram_phaseinjector2_command_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_re) begin + sdram_phaseinjector2_address_storage[13:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_r; + end + sdram_phaseinjector2_address_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_re) begin + sdram_phaseinjector2_baddress_storage[2:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_r; + end + sdram_phaseinjector2_baddress_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_re) begin + sdram_phaseinjector2_wrdata_storage[31:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_r; + end + sdram_phaseinjector2_wrdata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_re; + sdram_phaseinjector2_rddata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_re) begin + sdram_phaseinjector3_command_storage[5:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_r; + end + sdram_phaseinjector3_command_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_re) begin + sdram_phaseinjector3_address_storage[13:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_r; + end + sdram_phaseinjector3_address_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_re) begin + sdram_phaseinjector3_baddress_storage[2:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_r; + end + sdram_phaseinjector3_baddress_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_re; + if (basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_re) begin + sdram_phaseinjector3_wrdata_storage[31:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_r; + end + sdram_phaseinjector3_wrdata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_re; + sdram_phaseinjector3_rddata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_re; + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank7_sel) begin + case (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0]) + 1'd0: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_load0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_reload0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_en0_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_update_value0_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_value_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_status_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_pending_w; + end + 3'd7: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_enable0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank7_load0_re) begin + timer_load_storage[31:0] <= basesoc_csr_bankarray_csrbank7_load0_r; + end + timer_load_re <= basesoc_csr_bankarray_csrbank7_load0_re; + if (basesoc_csr_bankarray_csrbank7_reload0_re) begin + timer_reload_storage[31:0] <= basesoc_csr_bankarray_csrbank7_reload0_r; + end + timer_reload_re <= basesoc_csr_bankarray_csrbank7_reload0_re; + if (basesoc_csr_bankarray_csrbank7_en0_re) begin + timer_en_storage <= basesoc_csr_bankarray_csrbank7_en0_r; + end + timer_en_re <= basesoc_csr_bankarray_csrbank7_en0_re; + if (basesoc_csr_bankarray_csrbank7_update_value0_re) begin + timer_update_value_storage <= basesoc_csr_bankarray_csrbank7_update_value0_r; + end + timer_update_value_re <= basesoc_csr_bankarray_csrbank7_update_value0_re; + timer_value_re <= basesoc_csr_bankarray_csrbank7_value_re; + timer_status_re <= basesoc_csr_bankarray_csrbank7_ev_status_re; + if (basesoc_csr_bankarray_csrbank7_ev_pending_re) begin + timer_pending_r <= basesoc_csr_bankarray_csrbank7_ev_pending_r; + end + timer_pending_re <= basesoc_csr_bankarray_csrbank7_ev_pending_re; + if (basesoc_csr_bankarray_csrbank7_ev_enable0_re) begin + timer_enable_storage <= basesoc_csr_bankarray_csrbank7_ev_enable0_r; + end + timer_enable_re <= basesoc_csr_bankarray_csrbank7_ev_enable0_re; + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank8_sel) begin + case (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0]) + 1'd0: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= uart_rxtx_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_txfull_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_rxempty_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_ev_status_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_ev_pending_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_ev_enable0_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_txempty_w; + end + 3'd7: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_rxfull_w; + end + endcase + end + uart_txfull_re <= basesoc_csr_bankarray_csrbank8_txfull_re; + uart_rxempty_re <= basesoc_csr_bankarray_csrbank8_rxempty_re; + uart_status_re <= basesoc_csr_bankarray_csrbank8_ev_status_re; + if (basesoc_csr_bankarray_csrbank8_ev_pending_re) begin + uart_pending_r[1:0] <= basesoc_csr_bankarray_csrbank8_ev_pending_r; + end + uart_pending_re <= basesoc_csr_bankarray_csrbank8_ev_pending_re; + if (basesoc_csr_bankarray_csrbank8_ev_enable0_re) begin + uart_enable_storage[1:0] <= basesoc_csr_bankarray_csrbank8_ev_enable0_r; + end + uart_enable_re <= basesoc_csr_bankarray_csrbank8_ev_enable0_re; + uart_txempty_re <= basesoc_csr_bankarray_csrbank8_txempty_re; + uart_rxfull_re <= basesoc_csr_bankarray_csrbank8_rxfull_re; + basesoc_csr_bankarray_interface9_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank9_sel) begin + case (basesoc_csr_bankarray_interface9_bank_bus_adr[0]) + 1'd0: begin + basesoc_csr_bankarray_interface9_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank9_tuning_word0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank9_tuning_word0_re) begin + uart_phy_storage[31:0] <= basesoc_csr_bankarray_csrbank9_tuning_word0_r; + end + uart_phy_re <= basesoc_csr_bankarray_csrbank9_tuning_word0_re; + if (sys_rst) begin + soccontroller_reset_storage <= 1'd0; + soccontroller_reset_re <= 1'd0; + soccontroller_scratch_storage <= 32'd305419896; + soccontroller_scratch_re <= 1'd0; + soccontroller_bus_errors_re <= 1'd0; + soccontroller_bus_errors <= 32'd0; + basesoc_ram_bus_ack <= 1'd0; + ram_bus_ram_bus_ack <= 1'd0; + serial_tx <= 1'd1; + uart_phy_storage <= 32'd6184752; + uart_phy_re <= 1'd0; + uart_phy_sink_ready <= 1'd0; + uart_phy_tx_clken <= 1'd0; + uart_phy_tx_busy <= 1'd0; + uart_phy_source_valid <= 1'd0; + uart_phy_source_payload_data <= 8'd0; + uart_phy_rx_clken <= 1'd0; + uart_phy_rx_r <= 1'd0; + uart_phy_rx_busy <= 1'd0; + uart_txfull_re <= 1'd0; + uart_rxempty_re <= 1'd0; + uart_tx_pending <= 1'd0; + uart_tx_old_trigger <= 1'd0; + uart_rx_pending <= 1'd0; + uart_rx_old_trigger <= 1'd0; + uart_status_re <= 1'd0; + uart_pending_re <= 1'd0; + uart_pending_r <= 2'd0; + uart_enable_storage <= 2'd0; + uart_enable_re <= 1'd0; + uart_txempty_re <= 1'd0; + uart_rxfull_re <= 1'd0; + uart_tx_fifo_readable <= 1'd0; + uart_tx_fifo_level0 <= 5'd0; + uart_tx_fifo_produce <= 4'd0; + uart_tx_fifo_consume <= 4'd0; + uart_rx_fifo_readable <= 1'd0; + uart_rx_fifo_level0 <= 5'd0; + uart_rx_fifo_produce <= 4'd0; + uart_rx_fifo_consume <= 4'd0; + timer_load_storage <= 32'd0; + timer_load_re <= 1'd0; + timer_reload_storage <= 32'd0; + timer_reload_re <= 1'd0; + timer_en_storage <= 1'd0; + timer_en_re <= 1'd0; + timer_update_value_storage <= 1'd0; + timer_update_value_re <= 1'd0; + timer_value_status <= 32'd0; + timer_value_re <= 1'd0; + timer_zero_pending <= 1'd0; + timer_zero_old_trigger <= 1'd0; + timer_status_re <= 1'd0; + timer_pending_re <= 1'd0; + timer_pending_r <= 1'd0; + timer_enable_storage <= 1'd0; + timer_enable_re <= 1'd0; + timer_value <= 32'd0; + a7ddrphy_rst_storage <= 1'd0; + a7ddrphy_rst_re <= 1'd0; + a7ddrphy_half_sys8x_taps_storage <= 5'd10; + a7ddrphy_half_sys8x_taps_re <= 1'd0; + a7ddrphy_wlevel_en_storage <= 1'd0; + a7ddrphy_wlevel_en_re <= 1'd0; + a7ddrphy_dly_sel_storage <= 2'd0; + a7ddrphy_dly_sel_re <= 1'd0; + a7ddrphy_rdphase_storage <= 2'd2; + a7ddrphy_rdphase_re <= 1'd0; + a7ddrphy_wrphase_storage <= 2'd3; + a7ddrphy_wrphase_re <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_dqspattern_o1 <= 8'd0; + a7ddrphy_bitslip0_value0 <= 3'd7; + a7ddrphy_bitslip1_value0 <= 3'd7; + a7ddrphy_bitslip0_value1 <= 3'd7; + a7ddrphy_bitslip1_value1 <= 3'd7; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_bitslip0_value2 <= 3'd7; + a7ddrphy_bitslip0_value3 <= 3'd7; + a7ddrphy_bitslip1_value2 <= 3'd7; + a7ddrphy_bitslip1_value3 <= 3'd7; + a7ddrphy_bitslip2_value0 <= 3'd7; + a7ddrphy_bitslip2_value1 <= 3'd7; + a7ddrphy_bitslip3_value0 <= 3'd7; + a7ddrphy_bitslip3_value1 <= 3'd7; + a7ddrphy_bitslip4_value0 <= 3'd7; + a7ddrphy_bitslip4_value1 <= 3'd7; + a7ddrphy_bitslip5_value0 <= 3'd7; + a7ddrphy_bitslip5_value1 <= 3'd7; + a7ddrphy_bitslip6_value0 <= 3'd7; + a7ddrphy_bitslip6_value1 <= 3'd7; + a7ddrphy_bitslip7_value0 <= 3'd7; + a7ddrphy_bitslip7_value1 <= 3'd7; + a7ddrphy_bitslip8_value0 <= 3'd7; + a7ddrphy_bitslip8_value1 <= 3'd7; + a7ddrphy_bitslip9_value0 <= 3'd7; + a7ddrphy_bitslip9_value1 <= 3'd7; + a7ddrphy_bitslip10_value0 <= 3'd7; + a7ddrphy_bitslip10_value1 <= 3'd7; + a7ddrphy_bitslip11_value0 <= 3'd7; + a7ddrphy_bitslip11_value1 <= 3'd7; + a7ddrphy_bitslip12_value0 <= 3'd7; + a7ddrphy_bitslip12_value1 <= 3'd7; + a7ddrphy_bitslip13_value0 <= 3'd7; + a7ddrphy_bitslip13_value1 <= 3'd7; + a7ddrphy_bitslip14_value0 <= 3'd7; + a7ddrphy_bitslip14_value1 <= 3'd7; + a7ddrphy_bitslip15_value0 <= 3'd7; + a7ddrphy_bitslip15_value1 <= 3'd7; + a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + sdram_storage <= 4'd1; + sdram_re <= 1'd0; + sdram_phaseinjector0_command_storage <= 6'd0; + sdram_phaseinjector0_command_re <= 1'd0; + sdram_phaseinjector0_address_re <= 1'd0; + sdram_phaseinjector0_baddress_re <= 1'd0; + sdram_phaseinjector0_wrdata_re <= 1'd0; + sdram_phaseinjector0_rddata_status <= 32'd0; + sdram_phaseinjector0_rddata_re <= 1'd0; + sdram_phaseinjector1_command_storage <= 6'd0; + sdram_phaseinjector1_command_re <= 1'd0; + sdram_phaseinjector1_address_re <= 1'd0; + sdram_phaseinjector1_baddress_re <= 1'd0; + sdram_phaseinjector1_wrdata_re <= 1'd0; + sdram_phaseinjector1_rddata_status <= 32'd0; + sdram_phaseinjector1_rddata_re <= 1'd0; + sdram_phaseinjector2_command_storage <= 6'd0; + sdram_phaseinjector2_command_re <= 1'd0; + sdram_phaseinjector2_address_re <= 1'd0; + sdram_phaseinjector2_baddress_re <= 1'd0; + sdram_phaseinjector2_wrdata_re <= 1'd0; + sdram_phaseinjector2_rddata_status <= 32'd0; + sdram_phaseinjector2_rddata_re <= 1'd0; + sdram_phaseinjector3_command_storage <= 6'd0; + sdram_phaseinjector3_command_re <= 1'd0; + sdram_phaseinjector3_address_re <= 1'd0; + sdram_phaseinjector3_baddress_re <= 1'd0; + sdram_phaseinjector3_wrdata_re <= 1'd0; + sdram_phaseinjector3_rddata_status <= 32'd0; + sdram_phaseinjector3_rddata_re <= 1'd0; + sdram_dfi_p0_address <= 14'd0; + sdram_dfi_p0_bank <= 3'd0; + sdram_dfi_p0_cas_n <= 1'd1; + sdram_dfi_p0_cs_n <= 1'd1; + sdram_dfi_p0_ras_n <= 1'd1; + sdram_dfi_p0_we_n <= 1'd1; + sdram_dfi_p0_wrdata_en <= 1'd0; + sdram_dfi_p0_rddata_en <= 1'd0; + sdram_dfi_p1_address <= 14'd0; + sdram_dfi_p1_bank <= 3'd0; + sdram_dfi_p1_cas_n <= 1'd1; + sdram_dfi_p1_cs_n <= 1'd1; + sdram_dfi_p1_ras_n <= 1'd1; + sdram_dfi_p1_we_n <= 1'd1; + sdram_dfi_p1_wrdata_en <= 1'd0; + sdram_dfi_p1_rddata_en <= 1'd0; + sdram_dfi_p2_address <= 14'd0; + sdram_dfi_p2_bank <= 3'd0; + sdram_dfi_p2_cas_n <= 1'd1; + sdram_dfi_p2_cs_n <= 1'd1; + sdram_dfi_p2_ras_n <= 1'd1; + sdram_dfi_p2_we_n <= 1'd1; + sdram_dfi_p2_wrdata_en <= 1'd0; + sdram_dfi_p2_rddata_en <= 1'd0; + sdram_dfi_p3_address <= 14'd0; + sdram_dfi_p3_bank <= 3'd0; + sdram_dfi_p3_cas_n <= 1'd1; + sdram_dfi_p3_cs_n <= 1'd1; + sdram_dfi_p3_ras_n <= 1'd1; + sdram_dfi_p3_we_n <= 1'd1; + sdram_dfi_p3_wrdata_en <= 1'd0; + sdram_dfi_p3_rddata_en <= 1'd0; + sdram_cmd_payload_a <= 14'd0; + sdram_cmd_payload_ba <= 3'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd0; + sdram_cmd_payload_we <= 1'd0; + sdram_timer_count1 <= 10'd624; + sdram_postponer_req_o <= 1'd0; + sdram_postponer_count <= 1'd0; + sdram_sequencer_done1 <= 1'd0; + sdram_sequencer_counter <= 6'd0; + sdram_sequencer_count <= 1'd0; + sdram_zqcs_timer_count1 <= 27'd79999999; + sdram_zqcs_executer_done <= 1'd0; + sdram_zqcs_executer_counter <= 5'd0; + sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; + sdram_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0; + sdram_bankmachine0_row <= 14'd0; + sdram_bankmachine0_row_opened <= 1'd0; + sdram_bankmachine0_twtpcon_ready <= 1'd0; + sdram_bankmachine0_twtpcon_count <= 3'd0; + sdram_bankmachine0_trccon_ready <= 1'd0; + sdram_bankmachine0_trccon_count <= 3'd0; + sdram_bankmachine0_trascon_ready <= 1'd0; + sdram_bankmachine0_trascon_count <= 2'd0; + sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; + sdram_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0; + sdram_bankmachine1_row <= 14'd0; + sdram_bankmachine1_row_opened <= 1'd0; + sdram_bankmachine1_twtpcon_ready <= 1'd0; + sdram_bankmachine1_twtpcon_count <= 3'd0; + sdram_bankmachine1_trccon_ready <= 1'd0; + sdram_bankmachine1_trccon_count <= 3'd0; + sdram_bankmachine1_trascon_ready <= 1'd0; + sdram_bankmachine1_trascon_count <= 2'd0; + sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; + sdram_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0; + sdram_bankmachine2_row <= 14'd0; + sdram_bankmachine2_row_opened <= 1'd0; + sdram_bankmachine2_twtpcon_ready <= 1'd0; + sdram_bankmachine2_twtpcon_count <= 3'd0; + sdram_bankmachine2_trccon_ready <= 1'd0; + sdram_bankmachine2_trccon_count <= 3'd0; + sdram_bankmachine2_trascon_ready <= 1'd0; + sdram_bankmachine2_trascon_count <= 2'd0; + sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; + sdram_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0; + sdram_bankmachine3_row <= 14'd0; + sdram_bankmachine3_row_opened <= 1'd0; + sdram_bankmachine3_twtpcon_ready <= 1'd0; + sdram_bankmachine3_twtpcon_count <= 3'd0; + sdram_bankmachine3_trccon_ready <= 1'd0; + sdram_bankmachine3_trccon_count <= 3'd0; + sdram_bankmachine3_trascon_ready <= 1'd0; + sdram_bankmachine3_trascon_count <= 2'd0; + sdram_bankmachine4_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine4_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine4_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; + sdram_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0; + sdram_bankmachine4_row <= 14'd0; + sdram_bankmachine4_row_opened <= 1'd0; + sdram_bankmachine4_twtpcon_ready <= 1'd0; + sdram_bankmachine4_twtpcon_count <= 3'd0; + sdram_bankmachine4_trccon_ready <= 1'd0; + sdram_bankmachine4_trccon_count <= 3'd0; + sdram_bankmachine4_trascon_ready <= 1'd0; + sdram_bankmachine4_trascon_count <= 2'd0; + sdram_bankmachine5_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine5_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine5_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; + sdram_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0; + sdram_bankmachine5_row <= 14'd0; + sdram_bankmachine5_row_opened <= 1'd0; + sdram_bankmachine5_twtpcon_ready <= 1'd0; + sdram_bankmachine5_twtpcon_count <= 3'd0; + sdram_bankmachine5_trccon_ready <= 1'd0; + sdram_bankmachine5_trccon_count <= 3'd0; + sdram_bankmachine5_trascon_ready <= 1'd0; + sdram_bankmachine5_trascon_count <= 2'd0; + sdram_bankmachine6_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine6_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine6_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; + sdram_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0; + sdram_bankmachine6_row <= 14'd0; + sdram_bankmachine6_row_opened <= 1'd0; + sdram_bankmachine6_twtpcon_ready <= 1'd0; + sdram_bankmachine6_twtpcon_count <= 3'd0; + sdram_bankmachine6_trccon_ready <= 1'd0; + sdram_bankmachine6_trccon_count <= 3'd0; + sdram_bankmachine6_trascon_ready <= 1'd0; + sdram_bankmachine6_trascon_count <= 2'd0; + sdram_bankmachine7_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine7_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine7_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; + sdram_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0; + sdram_bankmachine7_row <= 14'd0; + sdram_bankmachine7_row_opened <= 1'd0; + sdram_bankmachine7_twtpcon_ready <= 1'd0; + sdram_bankmachine7_twtpcon_count <= 3'd0; + sdram_bankmachine7_trccon_ready <= 1'd0; + sdram_bankmachine7_trccon_count <= 3'd0; + sdram_bankmachine7_trascon_ready <= 1'd0; + sdram_bankmachine7_trascon_count <= 2'd0; + sdram_choose_cmd_grant <= 3'd0; + sdram_choose_req_grant <= 3'd0; + sdram_trrdcon_ready <= 1'd0; + sdram_trrdcon_count <= 1'd0; + sdram_tfawcon_ready <= 1'd1; + sdram_tfawcon_window <= 4'd0; + sdram_tccdcon_ready <= 1'd0; + sdram_tccdcon_count <= 1'd0; + sdram_twtrcon_ready <= 1'd0; + sdram_twtrcon_count <= 3'd0; + sdram_time0 <= 5'd0; + sdram_time1 <= 4'd0; + cmd_consumed <= 1'd0; + wdata_consumed <= 1'd0; + a7litesataphy_tx_idle <= 1'd0; + a7litesataphy_tx_polarity <= 1'd0; + a7litesataphy_rx_polarity <= 1'd0; + a7litesataphy_tx_init_gttxreset0 <= 1'd0; + a7litesataphy_tx_init_gttxpd0 <= 1'd0; + a7litesataphy_tx_init_txdlysreset0 <= 1'd0; + a7litesataphy_tx_init_txphinit0 <= 1'd0; + a7litesataphy_tx_init_txphalign0 <= 1'd0; + a7litesataphy_tx_init_txdlyen0 <= 1'd0; + a7litesataphy_tx_init_txuserrdy0 <= 1'd0; + a7litesataphy_tx_init_txphaligndone_r <= 1'd1; + a7litesataphy_tx_init_init_delay_count <= 6'd40; + a7litesataphy_tx_init_watchdog_count <= 17'd80000; + a7litesataphy_rx_init_gtrxreset0 <= 1'd0; + a7litesataphy_rx_init_gtrxpd0 <= 1'd0; + a7litesataphy_rx_init_rxdlysreset0 <= 1'd0; + a7litesataphy_rx_init_rxphalign0 <= 1'd0; + a7litesataphy_rx_init_rxuserrdy0 <= 1'd0; + a7litesataphy_rx_init_drpvalue <= 16'd0; + a7litesataphy_rx_init_rxpmaresetdone_r <= 1'd0; + a7litesataphy_rx_init_init_delay_count <= 6'd40; + a7litesataphy_rx_init_watchdog_count <= 19'd320000; + a7litesataphy_i_d0 <= 1'd0; + a7litesataphy_i_d1 <= 1'd0; + crg_tx_reset <= 1'd0; + crg_rx_reset <= 1'd0; + ctrl_retry_timer_count <= 20'd800000; + ctrl_align_timer_count <= 17'd69840; + ctrl_align_count <= 4'd0; + ctrl_stability_timer_count <= 19'd400000; + datapath_tx_fifo_graycounter0_q <= 4'd0; + datapath_tx_fifo_graycounter0_q_binary <= 4'd0; + datapath_rx_fifo_graycounter1_q <= 4'd0; + datapath_rx_fifo_graycounter1_q_binary <= 4'd0; + datapath_align_timer_count <= 13'd4096; + litesataphy_enable_storage <= 1'd1; + litesataphy_enable_re <= 1'd0; + litesataphy_status_re <= 1'd0; + link_litesatalinktx_error <= 1'd0; + link_litesatalinktx_crc_reg_i <= 32'd1379029042; + link_litesatalinktx_scrambler_context <= 16'd61686; + link_tx_source_valid <= 1'd0; + link_tx_source_payload_data <= 32'd0; + link_tx_source_payload_charisk <= 4'd0; + link_tx_align_cnt <= 8'd0; + link_rx_cont_in_cont <= 1'd0; + link_rx_cont_last_primitive <= 32'd0; + link_litesatalinkrx_descrambler_sink_payload_data <= 32'd0; + link_litesatalinkrx_descrambler_context <= 16'd61686; + link_litesatalinkrx_crc_crc_reg_i <= 32'd1379029042; + link_litesatalinkrx_crc_syncfifo_level <= 2'd0; + link_litesatalinkrx_crc_syncfifo_produce <= 1'd0; + link_litesatalinkrx_crc_syncfifo_consume <= 1'd0; + link_litesatalinkrx_crc_error <= 1'd0; + link_rx_source_valid <= 1'd0; + link_rx_source_payload_data <= 32'd0; + link_rx_source_payload_charisk <= 4'd0; + link_rx_buffer_level <= 8'd0; + link_rx_buffer_produce <= 7'd0; + link_rx_buffer_consume <= 7'd0; + transport_tx_counter <= 3'd0; + transport_tx_fis_type <= 8'd0; + transport_rx_encoded_cmd <= 160'd0; + transport_rx_counter <= 3'd0; + transport_rx_fis_type <= 8'd0; + command_tx_is_write <= 1'd0; + command_tx_is_read <= 1'd0; + command_tx_is_identify <= 1'd0; + command_tx_dwords_counter <= 11'd0; + command_rx_d2h_status <= 8'd0; + command_rx_d2h_errors <= 8'd0; + command_rx_is_identify <= 1'd0; + command_rx_read_ndwords <= 23'd0; + command_rx_dwords_counter <= 23'd0; + command_rx_d2h_error <= 1'd0; + command_rx_read_error <= 1'd0; + sata_sector2mem_sector_storage <= 48'd0; + sata_sector2mem_sector_re <= 1'd0; + sata_sector2mem_base_storage <= 64'd0; + sata_sector2mem_base_re <= 1'd0; + sata_sector2mem_done_re <= 1'd0; + sata_sector2mem_error_status <= 1'd0; + sata_sector2mem_error_re <= 1'd0; + sata_sector2mem_count <= 7'd0; + sata_sector2mem_buf_level <= 8'd0; + sata_sector2mem_buf_produce <= 7'd0; + sata_sector2mem_buf_consume <= 7'd0; + sata_mem2sector_sector_storage <= 48'd0; + sata_mem2sector_sector_re <= 1'd0; + sata_mem2sector_base_storage <= 64'd0; + sata_mem2sector_base_re <= 1'd0; + sata_mem2sector_done_re <= 1'd0; + sata_mem2sector_error_status <= 1'd0; + sata_mem2sector_error_re <= 1'd0; + sata_mem2sector_count <= 7'd0; + sata_mem2sector_dma_data <= 32'd0; + sata_mem2sector_buf_level <= 8'd0; + sata_mem2sector_buf_produce <= 7'd0; + sata_mem2sector_buf_consume <= 7'd0; + storage <= 8'd0; + re <= 1'd0; + chaser <= 8'd0; + mode <= 1'd0; + count <= 23'd5000000; + subfragments_refresher_state <= 2'd0; + subfragments_bankmachine0_state <= 3'd0; + subfragments_bankmachine1_state <= 3'd0; + subfragments_bankmachine2_state <= 3'd0; + subfragments_bankmachine3_state <= 3'd0; + subfragments_bankmachine4_state <= 3'd0; + subfragments_bankmachine5_state <= 3'd0; + subfragments_bankmachine6_state <= 3'd0; + subfragments_bankmachine7_state <= 3'd0; + subfragments_multiplexer_state <= 4'd0; + subfragments_new_master_wdata_ready0 <= 1'd0; + subfragments_new_master_wdata_ready1 <= 1'd0; + subfragments_new_master_rdata_valid0 <= 1'd0; + subfragments_new_master_rdata_valid1 <= 1'd0; + subfragments_new_master_rdata_valid2 <= 1'd0; + subfragments_new_master_rdata_valid3 <= 1'd0; + subfragments_new_master_rdata_valid4 <= 1'd0; + subfragments_new_master_rdata_valid5 <= 1'd0; + subfragments_new_master_rdata_valid6 <= 1'd0; + subfragments_new_master_rdata_valid7 <= 1'd0; + subfragments_new_master_rdata_valid8 <= 1'd0; + subfragments_fullmemorywe_state <= 2'd0; + subfragments_litesataphy_gtptxinit_state <= 4'd0; + subfragments_litesataphy_gtprxinit_state <= 4'd0; + subfragments_litesataphy_state <= 4'd0; + subfragments_litesatalinktx_litesatacrcinserter_state <= 2'd0; + subfragments_litesatalinktx_fsm_state <= 3'd0; + subfragments_litesatalinkrx_litesatacrcchecker_state <= 2'd0; + subfragments_litesatalinkrx_fsm_state <= 3'd0; + subfragments_litesatatransporttx_state <= 2'd0; + subfragments_litesatatransportrx_state <= 3'd0; + subfragments_litesatacommandtx_state <= 2'd0; + subfragments_litesatacommandrx_state <= 4'd0; + subfragments_grant <= 1'd0; + subfragments_ongoing0 <= 1'd0; + subfragments_ongoing1 <= 1'd0; + subfragments_litesatasector2memdma_state <= 2'd0; + subfragments_wishbonedmareader_state <= 1'd0; + subfragments_fsm_state <= 2'd0; + basesoc_basesoc_we <= 1'd0; + basesoc_grant <= 2'd0; + basesoc_slave_sel_r <= 4'd0; + basesoc_count <= 20'd1000000; + basesoc_csr_bankarray_sel_r <= 1'd0; + basesoc_state <= 2'd0; + end + xilinxmultiregimpl0_regs0 <= serial_rx; + xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0; + xilinxmultiregimpl1_regs0 <= a7litesataphy_tx_init_plllock0; + xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0; + xilinxmultiregimpl2_regs0 <= a7litesataphy_tx_init_txresetdone0; + xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0; + xilinxmultiregimpl3_regs0 <= a7litesataphy_tx_init_txdlysresetdone0; + xilinxmultiregimpl3_regs1 <= xilinxmultiregimpl3_regs0; + xilinxmultiregimpl4_regs0 <= a7litesataphy_tx_init_txphinitdone0; + xilinxmultiregimpl4_regs1 <= xilinxmultiregimpl4_regs0; + xilinxmultiregimpl5_regs0 <= a7litesataphy_tx_init_txphaligndone0; + xilinxmultiregimpl5_regs1 <= xilinxmultiregimpl5_regs0; + xilinxmultiregimpl6_regs0 <= a7litesataphy_rx_init_rxpmaresetdone0; + xilinxmultiregimpl6_regs1 <= xilinxmultiregimpl6_regs0; + xilinxmultiregimpl7_regs0 <= a7litesataphy_rx_init_plllock0; + xilinxmultiregimpl7_regs1 <= xilinxmultiregimpl7_regs0; + xilinxmultiregimpl8_regs0 <= a7litesataphy_rx_init_rxresetdone0; + xilinxmultiregimpl8_regs1 <= xilinxmultiregimpl8_regs0; + xilinxmultiregimpl9_regs0 <= a7litesataphy_rx_init_rxdlysresetdone0; + xilinxmultiregimpl9_regs1 <= xilinxmultiregimpl9_regs0; + xilinxmultiregimpl10_regs0 <= a7litesataphy_rx_init_rxsyncdone0; + xilinxmultiregimpl10_regs1 <= xilinxmultiregimpl10_regs0; + xilinxmultiregimpl15_regs0 <= a7litesataphy_pulsesynchronizer2_toggle_i; + xilinxmultiregimpl15_regs1 <= xilinxmultiregimpl15_regs0; + xilinxmultiregimpl16_regs0 <= a7litesataphy_rxcominitdet1; + xilinxmultiregimpl16_regs1 <= xilinxmultiregimpl16_regs0; + xilinxmultiregimpl17_regs0 <= a7litesataphy_rxcomwakedet1; + xilinxmultiregimpl17_regs1 <= xilinxmultiregimpl17_regs0; + xilinxmultiregimpl18_regs0 <= a7litesataphy_rxdisperr1; + xilinxmultiregimpl18_regs1 <= xilinxmultiregimpl18_regs0; + xilinxmultiregimpl19_regs0 <= a7litesataphy_rxnotintable1; + xilinxmultiregimpl19_regs1 <= xilinxmultiregimpl19_regs0; + xilinxmultiregimpl21_regs0 <= datapath_tx_fifo_graycounter1_q; + xilinxmultiregimpl21_regs1 <= xilinxmultiregimpl21_regs0; + xilinxmultiregimpl22_regs0 <= datapath_rx_fifo_graycounter0_q; + xilinxmultiregimpl22_regs1 <= xilinxmultiregimpl22_regs0; +end + +reg [31:0] mem[0:16383]; +reg [31:0] memdat; +always @(posedge sys_clk) begin + memdat <= mem[basesoc_adr]; +end + +assign basesoc_dat_r = memdat; + +initial begin + $readmemh("mem.init", mem); +end + +reg [31:0] mem_1[0:2047]; +reg [10:0] memadr; +always @(posedge sys_clk) begin + if (ram_we[0]) + mem_1[ram_adr][7:0] <= ram_dat_w[7:0]; + if (ram_we[1]) + mem_1[ram_adr][15:8] <= ram_dat_w[15:8]; + if (ram_we[2]) + mem_1[ram_adr][23:16] <= ram_dat_w[23:16]; + if (ram_we[3]) + mem_1[ram_adr][31:24] <= ram_dat_w[31:24]; + memadr <= ram_adr; +end + +assign ram_dat_r = mem_1[memadr]; + +initial begin + $readmemh("mem_1.init", mem_1); +end + +reg [7:0] mem_2[0:44]; +reg [5:0] memadr_1; +always @(posedge sys_clk) begin + memadr_1 <= basesoc_csr_bankarray_adr; +end + +assign basesoc_csr_bankarray_dat_r = mem_2[memadr_1]; + +initial begin + $readmemh("mem_2.init", mem_2); +end + +reg [9:0] storage_1[0:15]; +reg [9:0] memdat_1; +reg [9:0] memdat_2; +always @(posedge sys_clk) begin + if (uart_tx_fifo_wrport_we) + storage_1[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w; + memdat_1 <= storage_1[uart_tx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (uart_tx_fifo_rdport_re) + memdat_2 <= storage_1[uart_tx_fifo_rdport_adr]; +end + +assign uart_tx_fifo_wrport_dat_r = memdat_1; +assign uart_tx_fifo_rdport_dat_r = memdat_2; + +reg [9:0] storage_2[0:15]; +reg [9:0] memdat_3; +reg [9:0] memdat_4; +always @(posedge sys_clk) begin + if (uart_rx_fifo_wrport_we) + storage_2[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w; + memdat_3 <= storage_2[uart_rx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (uart_rx_fifo_rdport_re) + memdat_4 <= storage_2[uart_rx_fifo_rdport_adr]; +end + +assign uart_rx_fifo_wrport_dat_r = memdat_3; +assign uart_rx_fifo_rdport_dat_r = memdat_4; + +BUFG BUFG( + .I(crg_clkout0), + .O(crg_clkout_buf0) +); + +BUFG BUFG_1( + .I(crg_clkout1), + .O(crg_clkout_buf1) +); + +BUFG BUFG_2( + .I(crg_clkout2), + .O(crg_clkout_buf2) +); + +BUFG BUFG_3( + .I(crg_clkout3), + .O(crg_clkout_buf3) +); + +BUFG BUFG_4( + .I(crg_clkout4), + .O(crg_clkout_buf4) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(idelay_clk), + .RST(crg_ic_reset) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(1'd0), + .D2(1'd1), + .D3(1'd0), + .D4(1'd1), + .D5(1'd0), + .D6(1'd1), + .D7(1'd0), + .D8(1'd1), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(a7ddrphy_sd_clk_se_nodelay) +); + +OBUFDS OBUFDS( + .I(a7ddrphy_sd_clk_se_nodelay), + .O(ddram_clk_p), + .OB(ddram_clk_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_1 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_reset_n), + .D2(a7ddrphy_dfi_p0_reset_n), + .D3(a7ddrphy_dfi_p1_reset_n), + .D4(a7ddrphy_dfi_p1_reset_n), + .D5(a7ddrphy_dfi_p2_reset_n), + .D6(a7ddrphy_dfi_p2_reset_n), + .D7(a7ddrphy_dfi_p3_reset_n), + .D8(a7ddrphy_dfi_p3_reset_n), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_reset_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[0]), + .D2(a7ddrphy_dfi_p0_address[0]), + .D3(a7ddrphy_dfi_p1_address[0]), + .D4(a7ddrphy_dfi_p1_address[0]), + .D5(a7ddrphy_dfi_p2_address[0]), + .D6(a7ddrphy_dfi_p2_address[0]), + .D7(a7ddrphy_dfi_p3_address[0]), + .D8(a7ddrphy_dfi_p3_address[0]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_3 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[1]), + .D2(a7ddrphy_dfi_p0_address[1]), + .D3(a7ddrphy_dfi_p1_address[1]), + .D4(a7ddrphy_dfi_p1_address[1]), + .D5(a7ddrphy_dfi_p2_address[1]), + .D6(a7ddrphy_dfi_p2_address[1]), + .D7(a7ddrphy_dfi_p3_address[1]), + .D8(a7ddrphy_dfi_p3_address[1]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_4 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[2]), + .D2(a7ddrphy_dfi_p0_address[2]), + .D3(a7ddrphy_dfi_p1_address[2]), + .D4(a7ddrphy_dfi_p1_address[2]), + .D5(a7ddrphy_dfi_p2_address[2]), + .D6(a7ddrphy_dfi_p2_address[2]), + .D7(a7ddrphy_dfi_p3_address[2]), + .D8(a7ddrphy_dfi_p3_address[2]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_5 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[3]), + .D2(a7ddrphy_dfi_p0_address[3]), + .D3(a7ddrphy_dfi_p1_address[3]), + .D4(a7ddrphy_dfi_p1_address[3]), + .D5(a7ddrphy_dfi_p2_address[3]), + .D6(a7ddrphy_dfi_p2_address[3]), + .D7(a7ddrphy_dfi_p3_address[3]), + .D8(a7ddrphy_dfi_p3_address[3]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[3]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_6 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[4]), + .D2(a7ddrphy_dfi_p0_address[4]), + .D3(a7ddrphy_dfi_p1_address[4]), + .D4(a7ddrphy_dfi_p1_address[4]), + .D5(a7ddrphy_dfi_p2_address[4]), + .D6(a7ddrphy_dfi_p2_address[4]), + .D7(a7ddrphy_dfi_p3_address[4]), + .D8(a7ddrphy_dfi_p3_address[4]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[4]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_7 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[5]), + .D2(a7ddrphy_dfi_p0_address[5]), + .D3(a7ddrphy_dfi_p1_address[5]), + .D4(a7ddrphy_dfi_p1_address[5]), + .D5(a7ddrphy_dfi_p2_address[5]), + .D6(a7ddrphy_dfi_p2_address[5]), + .D7(a7ddrphy_dfi_p3_address[5]), + .D8(a7ddrphy_dfi_p3_address[5]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[5]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_8 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[6]), + .D2(a7ddrphy_dfi_p0_address[6]), + .D3(a7ddrphy_dfi_p1_address[6]), + .D4(a7ddrphy_dfi_p1_address[6]), + .D5(a7ddrphy_dfi_p2_address[6]), + .D6(a7ddrphy_dfi_p2_address[6]), + .D7(a7ddrphy_dfi_p3_address[6]), + .D8(a7ddrphy_dfi_p3_address[6]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[6]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_9 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[7]), + .D2(a7ddrphy_dfi_p0_address[7]), + .D3(a7ddrphy_dfi_p1_address[7]), + .D4(a7ddrphy_dfi_p1_address[7]), + .D5(a7ddrphy_dfi_p2_address[7]), + .D6(a7ddrphy_dfi_p2_address[7]), + .D7(a7ddrphy_dfi_p3_address[7]), + .D8(a7ddrphy_dfi_p3_address[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[7]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_10 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[8]), + .D2(a7ddrphy_dfi_p0_address[8]), + .D3(a7ddrphy_dfi_p1_address[8]), + .D4(a7ddrphy_dfi_p1_address[8]), + .D5(a7ddrphy_dfi_p2_address[8]), + .D6(a7ddrphy_dfi_p2_address[8]), + .D7(a7ddrphy_dfi_p3_address[8]), + .D8(a7ddrphy_dfi_p3_address[8]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[8]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_11 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[9]), + .D2(a7ddrphy_dfi_p0_address[9]), + .D3(a7ddrphy_dfi_p1_address[9]), + .D4(a7ddrphy_dfi_p1_address[9]), + .D5(a7ddrphy_dfi_p2_address[9]), + .D6(a7ddrphy_dfi_p2_address[9]), + .D7(a7ddrphy_dfi_p3_address[9]), + .D8(a7ddrphy_dfi_p3_address[9]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[9]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_12 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[10]), + .D2(a7ddrphy_dfi_p0_address[10]), + .D3(a7ddrphy_dfi_p1_address[10]), + .D4(a7ddrphy_dfi_p1_address[10]), + .D5(a7ddrphy_dfi_p2_address[10]), + .D6(a7ddrphy_dfi_p2_address[10]), + .D7(a7ddrphy_dfi_p3_address[10]), + .D8(a7ddrphy_dfi_p3_address[10]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[10]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_13 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[11]), + .D2(a7ddrphy_dfi_p0_address[11]), + .D3(a7ddrphy_dfi_p1_address[11]), + .D4(a7ddrphy_dfi_p1_address[11]), + .D5(a7ddrphy_dfi_p2_address[11]), + .D6(a7ddrphy_dfi_p2_address[11]), + .D7(a7ddrphy_dfi_p3_address[11]), + .D8(a7ddrphy_dfi_p3_address[11]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[11]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_14 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[12]), + .D2(a7ddrphy_dfi_p0_address[12]), + .D3(a7ddrphy_dfi_p1_address[12]), + .D4(a7ddrphy_dfi_p1_address[12]), + .D5(a7ddrphy_dfi_p2_address[12]), + .D6(a7ddrphy_dfi_p2_address[12]), + .D7(a7ddrphy_dfi_p3_address[12]), + .D8(a7ddrphy_dfi_p3_address[12]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[12]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_15 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[13]), + .D2(a7ddrphy_dfi_p0_address[13]), + .D3(a7ddrphy_dfi_p1_address[13]), + .D4(a7ddrphy_dfi_p1_address[13]), + .D5(a7ddrphy_dfi_p2_address[13]), + .D6(a7ddrphy_dfi_p2_address[13]), + .D7(a7ddrphy_dfi_p3_address[13]), + .D8(a7ddrphy_dfi_p3_address[13]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[13]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_16 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_address[14]), + .D2(a7ddrphy_dfi_p0_address[14]), + .D3(a7ddrphy_dfi_p1_address[14]), + .D4(a7ddrphy_dfi_p1_address[14]), + .D5(a7ddrphy_dfi_p2_address[14]), + .D6(a7ddrphy_dfi_p2_address[14]), + .D7(a7ddrphy_dfi_p3_address[14]), + .D8(a7ddrphy_dfi_p3_address[14]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_a[14]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_17 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_bank[0]), + .D2(a7ddrphy_dfi_p0_bank[0]), + .D3(a7ddrphy_dfi_p1_bank[0]), + .D4(a7ddrphy_dfi_p1_bank[0]), + .D5(a7ddrphy_dfi_p2_bank[0]), + .D6(a7ddrphy_dfi_p2_bank[0]), + .D7(a7ddrphy_dfi_p3_bank[0]), + .D8(a7ddrphy_dfi_p3_bank[0]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_ba[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_18 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_bank[1]), + .D2(a7ddrphy_dfi_p0_bank[1]), + .D3(a7ddrphy_dfi_p1_bank[1]), + .D4(a7ddrphy_dfi_p1_bank[1]), + .D5(a7ddrphy_dfi_p2_bank[1]), + .D6(a7ddrphy_dfi_p2_bank[1]), + .D7(a7ddrphy_dfi_p3_bank[1]), + .D8(a7ddrphy_dfi_p3_bank[1]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_ba[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_19 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_bank[2]), + .D2(a7ddrphy_dfi_p0_bank[2]), + .D3(a7ddrphy_dfi_p1_bank[2]), + .D4(a7ddrphy_dfi_p1_bank[2]), + .D5(a7ddrphy_dfi_p2_bank[2]), + .D6(a7ddrphy_dfi_p2_bank[2]), + .D7(a7ddrphy_dfi_p3_bank[2]), + .D8(a7ddrphy_dfi_p3_bank[2]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_ba[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_20 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_ras_n), + .D2(a7ddrphy_dfi_p0_ras_n), + .D3(a7ddrphy_dfi_p1_ras_n), + .D4(a7ddrphy_dfi_p1_ras_n), + .D5(a7ddrphy_dfi_p2_ras_n), + .D6(a7ddrphy_dfi_p2_ras_n), + .D7(a7ddrphy_dfi_p3_ras_n), + .D8(a7ddrphy_dfi_p3_ras_n), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_ras_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_21 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_cas_n), + .D2(a7ddrphy_dfi_p0_cas_n), + .D3(a7ddrphy_dfi_p1_cas_n), + .D4(a7ddrphy_dfi_p1_cas_n), + .D5(a7ddrphy_dfi_p2_cas_n), + .D6(a7ddrphy_dfi_p2_cas_n), + .D7(a7ddrphy_dfi_p3_cas_n), + .D8(a7ddrphy_dfi_p3_cas_n), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_cas_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_22 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_we_n), + .D2(a7ddrphy_dfi_p0_we_n), + .D3(a7ddrphy_dfi_p1_we_n), + .D4(a7ddrphy_dfi_p1_we_n), + .D5(a7ddrphy_dfi_p2_we_n), + .D6(a7ddrphy_dfi_p2_we_n), + .D7(a7ddrphy_dfi_p3_we_n), + .D8(a7ddrphy_dfi_p3_we_n), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_we_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_23 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_cke), + .D2(a7ddrphy_dfi_p0_cke), + .D3(a7ddrphy_dfi_p1_cke), + .D4(a7ddrphy_dfi_p1_cke), + .D5(a7ddrphy_dfi_p2_cke), + .D6(a7ddrphy_dfi_p2_cke), + .D7(a7ddrphy_dfi_p3_cke), + .D8(a7ddrphy_dfi_p3_cke), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_cke) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_24 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_dfi_p0_odt), + .D2(a7ddrphy_dfi_p0_odt), + .D3(a7ddrphy_dfi_p1_odt), + .D4(a7ddrphy_dfi_p1_odt), + .D5(a7ddrphy_dfi_p2_odt), + .D6(a7ddrphy_dfi_p2_odt), + .D7(a7ddrphy_dfi_p3_odt), + .D8(a7ddrphy_dfi_p3_odt), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_odt) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_25 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip00[0]), + .D2(a7ddrphy_bitslip00[1]), + .D3(a7ddrphy_bitslip00[2]), + .D4(a7ddrphy_bitslip00[3]), + .D5(a7ddrphy_bitslip00[4]), + .D6(a7ddrphy_bitslip00[5]), + .D7(a7ddrphy_bitslip00[6]), + .D8(a7ddrphy_bitslip00[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(a7ddrphy0), + .OQ(a7ddrphy_dqs_o_no_delay0), + .TQ(a7ddrphy_dqs_t0) +); + +IOBUFDS IOBUFDS( + .I(a7ddrphy_dqs_o_no_delay0), + .T(a7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_26 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip10[0]), + .D2(a7ddrphy_bitslip10[1]), + .D3(a7ddrphy_bitslip10[2]), + .D4(a7ddrphy_bitslip10[3]), + .D5(a7ddrphy_bitslip10[4]), + .D6(a7ddrphy_bitslip10[5]), + .D7(a7ddrphy_bitslip10[6]), + .D8(a7ddrphy_bitslip10[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OFB(a7ddrphy1), + .OQ(a7ddrphy_dqs_o_no_delay1), + .TQ(a7ddrphy_dqs_t1) +); + +IOBUFDS IOBUFDS_1( + .I(a7ddrphy_dqs_o_no_delay1), + .T(a7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_27 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip01[0]), + .D2(a7ddrphy_bitslip01[1]), + .D3(a7ddrphy_bitslip01[2]), + .D4(a7ddrphy_bitslip01[3]), + .D5(a7ddrphy_bitslip01[4]), + .D6(a7ddrphy_bitslip01[5]), + .D7(a7ddrphy_bitslip01[6]), + .D8(a7ddrphy_bitslip01[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_dm[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_28 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip11[0]), + .D2(a7ddrphy_bitslip11[1]), + .D3(a7ddrphy_bitslip11[2]), + .D4(a7ddrphy_bitslip11[3]), + .D5(a7ddrphy_bitslip11[4]), + .D6(a7ddrphy_bitslip11[5]), + .D7(a7ddrphy_bitslip11[6]), + .D8(a7ddrphy_bitslip11[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .OQ(ddram_dm[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_29 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip02[0]), + .D2(a7ddrphy_bitslip02[1]), + .D3(a7ddrphy_bitslip02[2]), + .D4(a7ddrphy_bitslip02[3]), + .D5(a7ddrphy_bitslip02[4]), + .D6(a7ddrphy_bitslip02[5]), + .D7(a7ddrphy_bitslip02[6]), + .D8(a7ddrphy_bitslip02[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay0), + .TQ(a7ddrphy_dq_t0) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed0), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip03[7]), + .Q2(a7ddrphy_bitslip03[6]), + .Q3(a7ddrphy_bitslip03[5]), + .Q4(a7ddrphy_bitslip03[4]), + .Q5(a7ddrphy_bitslip03[3]), + .Q6(a7ddrphy_bitslip03[2]), + .Q7(a7ddrphy_bitslip03[1]), + .Q8(a7ddrphy_bitslip03[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay0), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed0) +); + +IOBUF IOBUF( + .I(a7ddrphy_dq_o_nodelay0), + .T(a7ddrphy_dq_t0), + .IO(ddram_dq[0]), + .O(a7ddrphy_dq_i_nodelay0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_30 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip12[0]), + .D2(a7ddrphy_bitslip12[1]), + .D3(a7ddrphy_bitslip12[2]), + .D4(a7ddrphy_bitslip12[3]), + .D5(a7ddrphy_bitslip12[4]), + .D6(a7ddrphy_bitslip12[5]), + .D7(a7ddrphy_bitslip12[6]), + .D8(a7ddrphy_bitslip12[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay1), + .TQ(a7ddrphy_dq_t1) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_1 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip13[7]), + .Q2(a7ddrphy_bitslip13[6]), + .Q3(a7ddrphy_bitslip13[5]), + .Q4(a7ddrphy_bitslip13[4]), + .Q5(a7ddrphy_bitslip13[3]), + .Q6(a7ddrphy_bitslip13[2]), + .Q7(a7ddrphy_bitslip13[1]), + .Q8(a7ddrphy_bitslip13[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_1 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay1), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed1) +); + +IOBUF IOBUF_1( + .I(a7ddrphy_dq_o_nodelay1), + .T(a7ddrphy_dq_t1), + .IO(ddram_dq[1]), + .O(a7ddrphy_dq_i_nodelay1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_31 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip20[0]), + .D2(a7ddrphy_bitslip20[1]), + .D3(a7ddrphy_bitslip20[2]), + .D4(a7ddrphy_bitslip20[3]), + .D5(a7ddrphy_bitslip20[4]), + .D6(a7ddrphy_bitslip20[5]), + .D7(a7ddrphy_bitslip20[6]), + .D8(a7ddrphy_bitslip20[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay2), + .TQ(a7ddrphy_dq_t2) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed2), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip21[7]), + .Q2(a7ddrphy_bitslip21[6]), + .Q3(a7ddrphy_bitslip21[5]), + .Q4(a7ddrphy_bitslip21[4]), + .Q5(a7ddrphy_bitslip21[3]), + .Q6(a7ddrphy_bitslip21[2]), + .Q7(a7ddrphy_bitslip21[1]), + .Q8(a7ddrphy_bitslip21[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_2 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay2), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed2) +); + +IOBUF IOBUF_2( + .I(a7ddrphy_dq_o_nodelay2), + .T(a7ddrphy_dq_t2), + .IO(ddram_dq[2]), + .O(a7ddrphy_dq_i_nodelay2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_32 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip30[0]), + .D2(a7ddrphy_bitslip30[1]), + .D3(a7ddrphy_bitslip30[2]), + .D4(a7ddrphy_bitslip30[3]), + .D5(a7ddrphy_bitslip30[4]), + .D6(a7ddrphy_bitslip30[5]), + .D7(a7ddrphy_bitslip30[6]), + .D8(a7ddrphy_bitslip30[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay3), + .TQ(a7ddrphy_dq_t3) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_3 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed3), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip31[7]), + .Q2(a7ddrphy_bitslip31[6]), + .Q3(a7ddrphy_bitslip31[5]), + .Q4(a7ddrphy_bitslip31[4]), + .Q5(a7ddrphy_bitslip31[3]), + .Q6(a7ddrphy_bitslip31[2]), + .Q7(a7ddrphy_bitslip31[1]), + .Q8(a7ddrphy_bitslip31[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_3 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay3), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed3) +); + +IOBUF IOBUF_3( + .I(a7ddrphy_dq_o_nodelay3), + .T(a7ddrphy_dq_t3), + .IO(ddram_dq[3]), + .O(a7ddrphy_dq_i_nodelay3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_33 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip40[0]), + .D2(a7ddrphy_bitslip40[1]), + .D3(a7ddrphy_bitslip40[2]), + .D4(a7ddrphy_bitslip40[3]), + .D5(a7ddrphy_bitslip40[4]), + .D6(a7ddrphy_bitslip40[5]), + .D7(a7ddrphy_bitslip40[6]), + .D8(a7ddrphy_bitslip40[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay4), + .TQ(a7ddrphy_dq_t4) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_4 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed4), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip41[7]), + .Q2(a7ddrphy_bitslip41[6]), + .Q3(a7ddrphy_bitslip41[5]), + .Q4(a7ddrphy_bitslip41[4]), + .Q5(a7ddrphy_bitslip41[3]), + .Q6(a7ddrphy_bitslip41[2]), + .Q7(a7ddrphy_bitslip41[1]), + .Q8(a7ddrphy_bitslip41[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_4 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay4), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed4) +); + +IOBUF IOBUF_4( + .I(a7ddrphy_dq_o_nodelay4), + .T(a7ddrphy_dq_t4), + .IO(ddram_dq[4]), + .O(a7ddrphy_dq_i_nodelay4) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_34 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip50[0]), + .D2(a7ddrphy_bitslip50[1]), + .D3(a7ddrphy_bitslip50[2]), + .D4(a7ddrphy_bitslip50[3]), + .D5(a7ddrphy_bitslip50[4]), + .D6(a7ddrphy_bitslip50[5]), + .D7(a7ddrphy_bitslip50[6]), + .D8(a7ddrphy_bitslip50[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay5), + .TQ(a7ddrphy_dq_t5) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_5 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed5), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip51[7]), + .Q2(a7ddrphy_bitslip51[6]), + .Q3(a7ddrphy_bitslip51[5]), + .Q4(a7ddrphy_bitslip51[4]), + .Q5(a7ddrphy_bitslip51[3]), + .Q6(a7ddrphy_bitslip51[2]), + .Q7(a7ddrphy_bitslip51[1]), + .Q8(a7ddrphy_bitslip51[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_5 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay5), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed5) +); + +IOBUF IOBUF_5( + .I(a7ddrphy_dq_o_nodelay5), + .T(a7ddrphy_dq_t5), + .IO(ddram_dq[5]), + .O(a7ddrphy_dq_i_nodelay5) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_35 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip60[0]), + .D2(a7ddrphy_bitslip60[1]), + .D3(a7ddrphy_bitslip60[2]), + .D4(a7ddrphy_bitslip60[3]), + .D5(a7ddrphy_bitslip60[4]), + .D6(a7ddrphy_bitslip60[5]), + .D7(a7ddrphy_bitslip60[6]), + .D8(a7ddrphy_bitslip60[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay6), + .TQ(a7ddrphy_dq_t6) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_6 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed6), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip61[7]), + .Q2(a7ddrphy_bitslip61[6]), + .Q3(a7ddrphy_bitslip61[5]), + .Q4(a7ddrphy_bitslip61[4]), + .Q5(a7ddrphy_bitslip61[3]), + .Q6(a7ddrphy_bitslip61[2]), + .Q7(a7ddrphy_bitslip61[1]), + .Q8(a7ddrphy_bitslip61[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_6 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay6), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed6) +); + +IOBUF IOBUF_6( + .I(a7ddrphy_dq_o_nodelay6), + .T(a7ddrphy_dq_t6), + .IO(ddram_dq[6]), + .O(a7ddrphy_dq_i_nodelay6) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_36 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip70[0]), + .D2(a7ddrphy_bitslip70[1]), + .D3(a7ddrphy_bitslip70[2]), + .D4(a7ddrphy_bitslip70[3]), + .D5(a7ddrphy_bitslip70[4]), + .D6(a7ddrphy_bitslip70[5]), + .D7(a7ddrphy_bitslip70[6]), + .D8(a7ddrphy_bitslip70[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay7), + .TQ(a7ddrphy_dq_t7) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_7 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed7), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip71[7]), + .Q2(a7ddrphy_bitslip71[6]), + .Q3(a7ddrphy_bitslip71[5]), + .Q4(a7ddrphy_bitslip71[4]), + .Q5(a7ddrphy_bitslip71[3]), + .Q6(a7ddrphy_bitslip71[2]), + .Q7(a7ddrphy_bitslip71[1]), + .Q8(a7ddrphy_bitslip71[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_7 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay7), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed7) +); + +IOBUF IOBUF_7( + .I(a7ddrphy_dq_o_nodelay7), + .T(a7ddrphy_dq_t7), + .IO(ddram_dq[7]), + .O(a7ddrphy_dq_i_nodelay7) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_37 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip80[0]), + .D2(a7ddrphy_bitslip80[1]), + .D3(a7ddrphy_bitslip80[2]), + .D4(a7ddrphy_bitslip80[3]), + .D5(a7ddrphy_bitslip80[4]), + .D6(a7ddrphy_bitslip80[5]), + .D7(a7ddrphy_bitslip80[6]), + .D8(a7ddrphy_bitslip80[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay8), + .TQ(a7ddrphy_dq_t8) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_8 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed8), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip81[7]), + .Q2(a7ddrphy_bitslip81[6]), + .Q3(a7ddrphy_bitslip81[5]), + .Q4(a7ddrphy_bitslip81[4]), + .Q5(a7ddrphy_bitslip81[3]), + .Q6(a7ddrphy_bitslip81[2]), + .Q7(a7ddrphy_bitslip81[1]), + .Q8(a7ddrphy_bitslip81[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_8 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay8), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed8) +); + +IOBUF IOBUF_8( + .I(a7ddrphy_dq_o_nodelay8), + .T(a7ddrphy_dq_t8), + .IO(ddram_dq[8]), + .O(a7ddrphy_dq_i_nodelay8) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_38 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip90[0]), + .D2(a7ddrphy_bitslip90[1]), + .D3(a7ddrphy_bitslip90[2]), + .D4(a7ddrphy_bitslip90[3]), + .D5(a7ddrphy_bitslip90[4]), + .D6(a7ddrphy_bitslip90[5]), + .D7(a7ddrphy_bitslip90[6]), + .D8(a7ddrphy_bitslip90[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay9), + .TQ(a7ddrphy_dq_t9) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_9 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed9), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip91[7]), + .Q2(a7ddrphy_bitslip91[6]), + .Q3(a7ddrphy_bitslip91[5]), + .Q4(a7ddrphy_bitslip91[4]), + .Q5(a7ddrphy_bitslip91[3]), + .Q6(a7ddrphy_bitslip91[2]), + .Q7(a7ddrphy_bitslip91[1]), + .Q8(a7ddrphy_bitslip91[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_9 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay9), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed9) +); + +IOBUF IOBUF_9( + .I(a7ddrphy_dq_o_nodelay9), + .T(a7ddrphy_dq_t9), + .IO(ddram_dq[9]), + .O(a7ddrphy_dq_i_nodelay9) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_39 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip100[0]), + .D2(a7ddrphy_bitslip100[1]), + .D3(a7ddrphy_bitslip100[2]), + .D4(a7ddrphy_bitslip100[3]), + .D5(a7ddrphy_bitslip100[4]), + .D6(a7ddrphy_bitslip100[5]), + .D7(a7ddrphy_bitslip100[6]), + .D8(a7ddrphy_bitslip100[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay10), + .TQ(a7ddrphy_dq_t10) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_10 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed10), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip101[7]), + .Q2(a7ddrphy_bitslip101[6]), + .Q3(a7ddrphy_bitslip101[5]), + .Q4(a7ddrphy_bitslip101[4]), + .Q5(a7ddrphy_bitslip101[3]), + .Q6(a7ddrphy_bitslip101[2]), + .Q7(a7ddrphy_bitslip101[1]), + .Q8(a7ddrphy_bitslip101[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_10 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay10), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed10) +); + +IOBUF IOBUF_10( + .I(a7ddrphy_dq_o_nodelay10), + .T(a7ddrphy_dq_t10), + .IO(ddram_dq[10]), + .O(a7ddrphy_dq_i_nodelay10) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_40 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip110[0]), + .D2(a7ddrphy_bitslip110[1]), + .D3(a7ddrphy_bitslip110[2]), + .D4(a7ddrphy_bitslip110[3]), + .D5(a7ddrphy_bitslip110[4]), + .D6(a7ddrphy_bitslip110[5]), + .D7(a7ddrphy_bitslip110[6]), + .D8(a7ddrphy_bitslip110[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay11), + .TQ(a7ddrphy_dq_t11) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_11 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed11), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip111[7]), + .Q2(a7ddrphy_bitslip111[6]), + .Q3(a7ddrphy_bitslip111[5]), + .Q4(a7ddrphy_bitslip111[4]), + .Q5(a7ddrphy_bitslip111[3]), + .Q6(a7ddrphy_bitslip111[2]), + .Q7(a7ddrphy_bitslip111[1]), + .Q8(a7ddrphy_bitslip111[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_11 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay11), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed11) +); + +IOBUF IOBUF_11( + .I(a7ddrphy_dq_o_nodelay11), + .T(a7ddrphy_dq_t11), + .IO(ddram_dq[11]), + .O(a7ddrphy_dq_i_nodelay11) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_41 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip120[0]), + .D2(a7ddrphy_bitslip120[1]), + .D3(a7ddrphy_bitslip120[2]), + .D4(a7ddrphy_bitslip120[3]), + .D5(a7ddrphy_bitslip120[4]), + .D6(a7ddrphy_bitslip120[5]), + .D7(a7ddrphy_bitslip120[6]), + .D8(a7ddrphy_bitslip120[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay12), + .TQ(a7ddrphy_dq_t12) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_12 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed12), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip121[7]), + .Q2(a7ddrphy_bitslip121[6]), + .Q3(a7ddrphy_bitslip121[5]), + .Q4(a7ddrphy_bitslip121[4]), + .Q5(a7ddrphy_bitslip121[3]), + .Q6(a7ddrphy_bitslip121[2]), + .Q7(a7ddrphy_bitslip121[1]), + .Q8(a7ddrphy_bitslip121[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_12 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay12), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed12) +); + +IOBUF IOBUF_12( + .I(a7ddrphy_dq_o_nodelay12), + .T(a7ddrphy_dq_t12), + .IO(ddram_dq[12]), + .O(a7ddrphy_dq_i_nodelay12) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_42 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip130[0]), + .D2(a7ddrphy_bitslip130[1]), + .D3(a7ddrphy_bitslip130[2]), + .D4(a7ddrphy_bitslip130[3]), + .D5(a7ddrphy_bitslip130[4]), + .D6(a7ddrphy_bitslip130[5]), + .D7(a7ddrphy_bitslip130[6]), + .D8(a7ddrphy_bitslip130[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay13), + .TQ(a7ddrphy_dq_t13) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_13 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed13), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip131[7]), + .Q2(a7ddrphy_bitslip131[6]), + .Q3(a7ddrphy_bitslip131[5]), + .Q4(a7ddrphy_bitslip131[4]), + .Q5(a7ddrphy_bitslip131[3]), + .Q6(a7ddrphy_bitslip131[2]), + .Q7(a7ddrphy_bitslip131[1]), + .Q8(a7ddrphy_bitslip131[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_13 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay13), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed13) +); + +IOBUF IOBUF_13( + .I(a7ddrphy_dq_o_nodelay13), + .T(a7ddrphy_dq_t13), + .IO(ddram_dq[13]), + .O(a7ddrphy_dq_i_nodelay13) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_43 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip140[0]), + .D2(a7ddrphy_bitslip140[1]), + .D3(a7ddrphy_bitslip140[2]), + .D4(a7ddrphy_bitslip140[3]), + .D5(a7ddrphy_bitslip140[4]), + .D6(a7ddrphy_bitslip140[5]), + .D7(a7ddrphy_bitslip140[6]), + .D8(a7ddrphy_bitslip140[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay14), + .TQ(a7ddrphy_dq_t14) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_14 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed14), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip141[7]), + .Q2(a7ddrphy_bitslip141[6]), + .Q3(a7ddrphy_bitslip141[5]), + .Q4(a7ddrphy_bitslip141[4]), + .Q5(a7ddrphy_bitslip141[3]), + .Q6(a7ddrphy_bitslip141[2]), + .Q7(a7ddrphy_bitslip141[1]), + .Q8(a7ddrphy_bitslip141[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_14 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay14), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed14) +); + +IOBUF IOBUF_14( + .I(a7ddrphy_dq_o_nodelay14), + .T(a7ddrphy_dq_t14), + .IO(ddram_dq[14]), + .O(a7ddrphy_dq_i_nodelay14) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_44 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(a7ddrphy_bitslip150[0]), + .D2(a7ddrphy_bitslip150[1]), + .D3(a7ddrphy_bitslip150[2]), + .D4(a7ddrphy_bitslip150[3]), + .D5(a7ddrphy_bitslip150[4]), + .D6(a7ddrphy_bitslip150[5]), + .D7(a7ddrphy_bitslip150[6]), + .D8(a7ddrphy_bitslip150[7]), + .OCE(1'd1), + .RST((sys_rst | a7ddrphy_rst_storage)), + .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), + .TCE(1'd1), + .OQ(a7ddrphy_dq_o_nodelay15), + .TQ(a7ddrphy_dq_t15) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_15 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(a7ddrphy_dq_i_delayed15), + .RST((sys_rst | a7ddrphy_rst_storage)), + .Q1(a7ddrphy_bitslip151[7]), + .Q2(a7ddrphy_bitslip151[6]), + .Q3(a7ddrphy_bitslip151[5]), + .Q4(a7ddrphy_bitslip151[4]), + .Q5(a7ddrphy_bitslip151[3]), + .Q6(a7ddrphy_bitslip151[2]), + .Q7(a7ddrphy_bitslip151[1]), + .Q8(a7ddrphy_bitslip151[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_15 ( + .C(sys_clk), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay15), + .INC(1'd1), + .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), + .LDPIPEEN(1'd0), + .DATAOUT(a7ddrphy_dq_i_delayed15) +); + +IOBUF IOBUF_15( + .I(a7ddrphy_dq_o_nodelay15), + .T(a7ddrphy_dq_t15), + .IO(ddram_dq[15]), + .O(a7ddrphy_dq_i_nodelay15) +); + +reg [23:0] storage_3[0:7]; +reg [23:0] memdat_5; +always @(posedge sys_clk) begin + if (sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage_3[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_3[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_3[sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_4[0:7]; +reg [23:0] memdat_6; +always @(posedge sys_clk) begin + if (sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_4[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_4[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_4[sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_5[0:7]; +reg [23:0] memdat_7; +always @(posedge sys_clk) begin + if (sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_5[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_5[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_5[sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_6[0:7]; +reg [23:0] memdat_8; +always @(posedge sys_clk) begin + if (sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_6[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_8 <= storage_6[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8; +assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_6[sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_7[0:7]; +reg [23:0] memdat_9; +always @(posedge sys_clk) begin + if (sdram_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_7[sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_9 <= storage_7[sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9; +assign sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_7[sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_8[0:7]; +reg [23:0] memdat_10; +always @(posedge sys_clk) begin + if (sdram_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_8[sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_10 <= storage_8[sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10; +assign sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_8[sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_9[0:7]; +reg [23:0] memdat_11; +always @(posedge sys_clk) begin + if (sdram_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_9[sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_11 <= storage_9[sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11; +assign sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_9[sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_10[0:7]; +reg [23:0] memdat_12; +always @(posedge sys_clk) begin + if (sdram_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_10[sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_12 <= storage_10[sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12; +assign sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_10[sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] tag_mem[0:511]; +reg [8:0] memadr_2; +always @(posedge sys_clk) begin + if (tag_port_we) + tag_mem[tag_port_adr] <= tag_port_dat_w; + memadr_2 <= tag_port_adr; +end + +assign tag_port_dat_r = tag_mem[memadr_2]; + +GTPE2_COMMON #( + .PLL0_FBDIV(3'd5), + .PLL0_FBDIV_45(3'd4), + .PLL0_REFCLK_DIV(1'd1) +) GTPE2_COMMON ( + .BGBYPASSB(1'd1), + .BGMONITORENB(1'd1), + .BGPDB(1'd1), + .BGRCALOVRD(5'd31), + .DRPADDR(a7litesataphy_qpll_drp_addr), + .DRPCLK(a7litesataphy_qpll_drp_clk), + .DRPDI(a7litesataphy_qpll_drp_di), + .DRPEN(a7litesataphy_qpll_drp_en), + .DRPWE(a7litesataphy_qpll_drp_we), + // FIXME: The GTREFCLK1 needs to be used for this design. + // Vivado automatically swaps the input accordingly to the IBUFDS placement location + // and this is currently not doable in VPR. For the time being, we can just manually adjust it. + // https://github.com/SymbiFlow/symbiflow-arch-defs/issues/2328 + .GTREFCLK1(a7litesataphy_gtrefclk0), + .PLL0LOCKEN(1'd1), + .PLL0PD(1'd0), + .PLL0REFCLKSEL(1'd1), + .PLL0RESET(a7litesataphy_qpll_reset), + .PLL1PD(1'd1), + .RCALENB(1'd1), + .DRPDO(a7litesataphy_qpll_drp_do), + .DRPRDY(a7litesataphy_qpll_drp_rdy), + .PLL0LOCK(a7litesataphy_qpll_lock), + .PLL0OUTCLK(a7litesataphy_qpll_clk), + .PLL0OUTREFCLK(a7litesataphy_qpll_refclk) +); + +// FIXME: FDPE connected to the IBUFDS clk output need to be in the same clock region, otherwise resulting +// in an unroutable situation. +// https://github.com/SymbiFlow/symbiflow-arch-defs/issues/2327 +(* LOC="SLICE_X51Y227" *) +FDPE #( + .INIT(1'd1) +) FDPE ( + .C(a7litesataphy_gtrefclk0), + .CE(1'd1), + .D((~a7litesataphy_oobclk)), + .PRE(1'd0), + .Q(a7litesataphy_oobclk) +); + +GTPE2_CHANNEL #( + .ACJTAG_DEBUG_MODE(1'd0), + .ACJTAG_MODE(1'd0), + .ACJTAG_RESET(1'd0), + .ADAPT_CFG0(1'd0), + .ALIGN_COMMA_DOUBLE("FALSE"), + .ALIGN_COMMA_ENABLE(10'd1023), + .ALIGN_COMMA_WORD(2'd2), + .ALIGN_MCOMMA_DET("TRUE"), + .ALIGN_MCOMMA_VALUE(10'd643), + .ALIGN_PCOMMA_DET("TRUE"), + .ALIGN_PCOMMA_VALUE(9'd380), + .CBCC_DATA_SOURCE_SEL("DECODED"), + .CFOK_CFG(43'd5016522067584), + .CFOK_CFG2(6'd32), + .CFOK_CFG3(6'd32), + .CFOK_CFG4(1'd0), + .CFOK_CFG5(1'd0), + .CFOK_CFG6(1'd0), + .CHAN_BOND_KEEP_ALIGN("FALSE"), + .CHAN_BOND_MAX_SKEW(1'd1), + .CHAN_BOND_SEQ_1_1(1'd0), + .CHAN_BOND_SEQ_1_2(1'd0), + .CHAN_BOND_SEQ_1_3(1'd0), + .CHAN_BOND_SEQ_1_4(1'd0), + .CHAN_BOND_SEQ_1_ENABLE(4'd15), + .CHAN_BOND_SEQ_2_1(1'd0), + .CHAN_BOND_SEQ_2_2(1'd0), + .CHAN_BOND_SEQ_2_3(1'd0), + .CHAN_BOND_SEQ_2_4(1'd0), + .CHAN_BOND_SEQ_2_ENABLE(4'd15), + .CHAN_BOND_SEQ_2_USE("FALSE"), + .CHAN_BOND_SEQ_LEN(1'd1), + .CLK_COMMON_SWING(1'd0), + .CLK_CORRECT_USE("FALSE"), + .CLK_COR_KEEP_IDLE("FALSE"), + .CLK_COR_MAX_LAT(4'd9), + .CLK_COR_MIN_LAT(3'd7), + .CLK_COR_PRECEDENCE("TRUE"), + .CLK_COR_REPEAT_WAIT(1'd0), + .CLK_COR_SEQ_1_1(9'd256), + .CLK_COR_SEQ_1_2(1'd0), + .CLK_COR_SEQ_1_3(1'd0), + .CLK_COR_SEQ_1_4(1'd0), + .CLK_COR_SEQ_1_ENABLE(4'd15), + .CLK_COR_SEQ_2_1(9'd256), + .CLK_COR_SEQ_2_2(1'd0), + .CLK_COR_SEQ_2_3(1'd0), + .CLK_COR_SEQ_2_4(1'd0), + .CLK_COR_SEQ_2_ENABLE(4'd15), + .CLK_COR_SEQ_2_USE("FALSE"), + .CLK_COR_SEQ_LEN(1'd1), + .DEC_MCOMMA_DETECT("TRUE"), + .DEC_PCOMMA_DETECT("TRUE"), + .DEC_VALID_COMMA_ONLY("TRUE"), + .DMONITOR_CFG(12'd2560), + .ES_CLK_PHASE_SEL(1'd0), + .ES_CONTROL(1'd0), + .ES_ERRDET_EN("FALSE"), + .ES_EYE_SCAN_EN("TRUE"), + .ES_HORZ_OFFSET(5'd16), + .ES_PMA_CFG(1'd0), + .ES_PRESCALE(1'd0), + .ES_QUALIFIER(1'd0), + .ES_QUAL_MASK(1'd0), + .ES_SDATA_MASK(1'd0), + .ES_VERT_OFFSET(1'd0), + .FTS_DESKEW_SEQ_ENABLE(4'd15), + .FTS_LANE_DESKEW_CFG(4'd15), + .FTS_LANE_DESKEW_EN("FALSE"), + .GEARBOX_MODE(1'd0), + .LOOPBACK_CFG(1'd0), + .OUTREFCLK_SEL_INV(2'd3), + .PCS_PCIE_EN("FALSE"), + .PCS_RSVD_ATTR(9'd256), + .PD_TRANS_TIME_FROM_P2(6'd60), + .PD_TRANS_TIME_NONE_P2(6'd60), + .PD_TRANS_TIME_TO_P2(7'd100), + .PMA_LOOPBACK_CFG(1'd0), + .PMA_RSV(10'd819), + .PMA_RSV2(14'd8256), + .PMA_RSV3(1'd0), + .PMA_RSV4(1'd0), + .PMA_RSV5(1'd0), + .PMA_RSV6(1'd0), + .PMA_RSV7(1'd0), + .RXBUFRESET_TIME(1'd1), + .RXBUF_ADDR_MODE("FAST"), + .RXBUF_EIDLE_HI_CNT(4'd8), + .RXBUF_EIDLE_LO_CNT(1'd0), + .RXBUF_EN("FALSE"), + .RXBUF_RESET_ON_CB_CHANGE("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN("FALSE"), + .RXBUF_RESET_ON_EIDLE("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .RXBUF_THRESH_OVFLW(6'd61), + .RXBUF_THRESH_OVRD("FALSE"), + .RXBUF_THRESH_UNDFLW(3'd4), + .RXCDRFREQRESET_TIME(1'd1), + .RXCDRPHRESET_TIME(1'd1), + .RXCDR_CFG(63'd5187619418075041808), + .RXCDR_FR_RESET_ON_EIDLE(1'd0), + .RXCDR_HOLD_DURING_EIDLE(1'd0), + .RXCDR_LOCK_CFG(4'd9), + .RXCDR_PH_RESET_ON_EIDLE(1'd0), + .RXDLY_CFG(5'd31), + .RXDLY_LCFG(6'd48), + .RXDLY_TAP_CFG(1'd0), + .RXGEARBOX_EN("FALSE"), + .RXISCANRESET_TIME(1'd1), + .RXLPMRESET_TIME(4'd15), + .RXLPM_BIAS_STARTUP_DISABLE(1'd0), + .RXLPM_CFG(3'd6), + .RXLPM_CFG1(1'd0), + .RXLPM_CM_CFG(1'd0), + .RXLPM_GC_CFG(9'd482), + .RXLPM_GC_CFG2(1'd1), + .RXLPM_HF_CFG(10'd1008), + .RXLPM_HF_CFG2(4'd10), + .RXLPM_HF_CFG3(1'd0), + .RXLPM_HOLD_DURING_EIDLE(1'd0), + .RXLPM_INCM_CFG(1'd1), + .RXLPM_IPCM_CFG(1'd0), + .RXLPM_LF_CFG(10'd1008), + .RXLPM_LF_CFG2(4'd10), + .RXLPM_OSINT_CFG(3'd4), + .RXOOB_CFG(3'd6), + .RXOOB_CLK_CFG("PMA"), + .RXOSCALRESET_TIME(2'd3), + .RXOSCALRESET_TIMEOUT(1'd0), + .RXOUT_DIV(2'd2), + .RXPCSRESET_TIME(1'd1), + .RXPHDLY_CFG(20'd540704), + .RXPH_CFG(24'd12582914), + .RXPH_MONITOR_SEL(1'd0), + .RXPI_CFG0(1'd0), + .RXPI_CFG1(1'd1), + .RXPI_CFG2(1'd1), + .RXPMARESET_TIME(2'd3), + .RXPRBS_ERR_LOOPBACK(1'd0), + .RXSLIDE_AUTO_WAIT(3'd7), + .RXSLIDE_MODE("PCS"), + .RXSYNC_MULTILANE(1'd0), + .RXSYNC_OVRD(1'd0), + .RXSYNC_SKIP_DA(1'd0), + .RX_BIAS_CFG(12'd3891), + .RX_BUFFER_CFG(1'd0), + .RX_CLK25_DIV(3'd6), + .RX_CLKMUX_EN(1'd1), + .RX_CM_SEL(2'd3), + .RX_CM_TRIM(4'd10), + .RX_DATA_WIDTH(5'd20), + .RX_DDI_SEL(1'd0), + .RX_DEBUG_CFG(1'd0), + .RX_DEFER_RESET_BUF_EN("TRUE"), + .RX_DISPERR_SEQ_MATCH("TRUE"), + .RX_OS_CFG(8'd128), + .RX_SIG_VALID_DLY(4'd10), + .RX_XCLK_SEL("RXUSR"), + .SAS_MAX_COM(7'd64), + .SAS_MIN_COM(6'd36), + .SATA_BURST_SEQ_LEN(3'd5), + .SATA_BURST_VAL(3'd4), + .SATA_EIDLE_VAL(3'd4), + .SATA_MAX_BURST(4'd8), + .SATA_MAX_INIT(5'd21), + .SATA_MAX_WAKE(3'd7), + .SATA_MIN_BURST(3'd4), + .SATA_MIN_INIT(4'd12), + .SATA_MIN_WAKE(3'd4), + .SATA_PLL_CFG("VCO_3000MHZ"), + .SHOW_REALIGN_COMMA("TRUE"), + .SIM_RECEIVER_DETECT_PASS("TRUE"), + .SIM_RESET_SPEEDUP("FALSE"), + .SIM_TX_EIDLE_DRIVE_LEVEL("X"), + .SIM_VERSION("2.0"), + .TERM_RCAL_CFG(15'd16912), + .TERM_RCAL_OVRD(1'd0), + .TRANS_TIME_RATE(4'd14), + .TST_RSV(1'd0), + .TXBUF_EN("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), + .TXDLY_CFG(5'd31), + .TXDLY_LCFG(6'd48), + .TXDLY_TAP_CFG(1'd0), + .TXGEARBOX_EN("FALSE"), + .TXOOB_CFG(1'd0), + .TXOUT_DIV(2'd2), + .TXPCSRESET_TIME(1'd1), + .TXPHDLY_CFG(20'd540704), + .TXPH_CFG(11'd1920), + .TXPH_MONITOR_SEL(1'd0), + .TXPI_CFG0(1'd0), + .TXPI_CFG1(1'd0), + .TXPI_CFG2(1'd0), + .TXPI_CFG3(1'd0), + .TXPI_CFG4(1'd0), + .TXPI_CFG5(1'd0), + .TXPI_GREY_SEL(1'd0), + .TXPI_INVSTROBE_SEL(1'd0), + .TXPI_PPMCLK_SEL("TXUSRCLK2"), + .TXPI_PPM_CFG(1'd0), + .TXPI_SYNFREQ_PPM(1'd1), + .TXPMARESET_TIME(1'd1), + .TXSYNC_MULTILANE(1'd0), + .TXSYNC_OVRD(1'd0), + .TXSYNC_SKIP_DA(1'd0), + .TX_CLK25_DIV(3'd6), + .TX_CLKMUX_EN(1'd1), + .TX_DATA_WIDTH(5'd20), + .TX_DEEMPH0(1'd0), + .TX_DEEMPH1(1'd0), + .TX_DRIVE_MODE("DIRECT"), + .TX_EIDLE_ASSERT_DELAY(3'd6), + .TX_EIDLE_DEASSERT_DELAY(3'd4), + .TX_LOOPBACK_DRIVE_HIZ("FALSE"), + .TX_MAINCURSOR_SEL(1'd0), + .TX_MARGIN_FULL_0(7'd78), + .TX_MARGIN_FULL_1(7'd73), + .TX_MARGIN_FULL_2(7'd69), + .TX_MARGIN_FULL_3(7'd66), + .TX_MARGIN_FULL_4(7'd64), + .TX_MARGIN_LOW_0(7'd70), + .TX_MARGIN_LOW_1(7'd68), + .TX_MARGIN_LOW_2(7'd66), + .TX_MARGIN_LOW_3(7'd64), + .TX_MARGIN_LOW_4(7'd64), + .TX_PREDRIVER_MODE(1'd0), + .TX_RXDETECT_CFG(13'd6194), + .TX_RXDETECT_REF(3'd4), + .TX_XCLK_SEL("TXOUT"), + .UCODEER_CLR(1'd0), + .USE_PCS_CLK_PHASE_SEL(1'd0) +) GTPE2_CHANNEL ( + .CFGRESET(1'd0), + .CLKRSVD0(1'd0), + .CLKRSVD1(1'd0), + .DMONFIFORESET(1'd0), + .DMONITORCLK(1'd0), + .DRPADDR(a7litesataphy_rx_init_drp_addr), + .DRPCLK(a7litesataphy_rx_init_drp_clk), + .DRPDI(a7litesataphy_rx_init_drp_di), + .DRPEN(a7litesataphy_rx_init_drp_en), + .DRPWE(a7litesataphy_rx_init_drp_we), + .EYESCANMODE(1'd0), + .EYESCANRESET(1'd0), + .EYESCANTRIGGER(1'd0), + .GTPRXN(fmc2sata_rx_n), + .GTPRXP(fmc2sata_rx_p), + .GTRESETSEL(1'd0), + .GTRSVD(1'd0), + .GTRXRESET(a7litesataphy_rx_init_gtrxreset0), + .GTTXRESET(a7litesataphy_tx_init_gttxreset0), + .LOOPBACK(1'd0), + .PCSRSVDIN(1'd0), + .PLL0CLK(a7litesataphy_qpll_clk), + .PLL0REFCLK(a7litesataphy_qpll_refclk), + .PLL1CLK(1'd0), + .PLL1REFCLK(1'd0), + .PMARSVDIN0(1'd0), + .PMARSVDIN1(1'd0), + .PMARSVDIN2(1'd0), + .PMARSVDIN3(1'd0), + .PMARSVDIN4(1'd0), + .RESETOVRD(1'd0), + .RX8B10BEN(1'd1), + .RXADAPTSELTEST(1'd0), + .RXBUFRESET(1'd0), + .RXCDRFREQRESET(1'd0), + .RXCDRHOLD(a7litesataphy_rx_cdrhold), + .RXCDROVRDEN(1'd0), + .RXCDRRESET(1'd0), + .RXCDRRESETRSV(1'd0), + .RXCHBONDEN(1'd0), + .RXCHBONDI(1'd0), + .RXCHBONDLEVEL(1'd0), + .RXCHBONDMASTER(1'd0), + .RXCHBONDSLAVE(1'd0), + .RXCOMMADETEN(1'd1), + .RXDDIEN(1'd1), + .RXDFEXYDEN(1'd0), + .RXDLYBYPASS(1'd0), + .RXDLYEN(1'd0), + .RXDLYOVRDEN(1'd0), + .RXDLYSRESET(a7litesataphy_rx_init_rxdlysreset0), + .RXELECIDLEMODE(1'd0), + .RXGEARBOXSLIP(1'd0), + .RXLPMHFHOLD(1'd0), + .RXLPMHFOVRDEN(1'd0), + .RXLPMLFHOLD(1'd0), + .RXLPMLFOVRDEN(1'd0), + .RXLPMOSINTNTRLEN(1'd0), + .RXLPMRESET(1'd0), + .RXMCOMMAALIGNEN(1'd1), + .RXOOBRESET(1'd0), + .RXOSCALRESET(1'd0), + .RXOSHOLD(1'd0), + .RXOSINTCFG(2'd2), + .RXOSINTEN(1'd1), + .RXOSINTHOLD(1'd0), + .RXOSINTID0(1'd0), + .RXOSINTNTRLEN(1'd0), + .RXOSINTOVRDEN(1'd0), + .RXOSINTPD(1'd0), + .RXOSINTSTROBE(1'd0), + .RXOSINTTESTOVRDEN(1'd0), + .RXOSOVRDEN(1'd0), + .RXOUTCLKSEL(2'd2), + .RXPCOMMAALIGNEN(1'd1), + .RXPCSRESET(1'd0), + .RXPD({2{a7litesataphy_rxpd}}), + .RXPHALIGN(1'd0), + .RXPHALIGNEN(1'd0), + .RXPHDLYPD(1'd0), + .RXPHDLYRESET(1'd0), + .RXPHOVRDEN(1'd0), + .RXPMARESET(1'd0), + .RXPOLARITY(a7litesataphy_rx_polarity), + .RXPRBSCNTRESET(1'd0), + .RXPRBSSEL(1'd0), + .RXRATE(1'd0), + .RXRATEMODE(1'd0), + .RXSLIDE(1'd0), + .RXSYNCALLIN(a7litesataphy_rxphaligndone), + .RXSYNCIN(1'd0), + .RXSYNCMODE(1'd1), + .RXSYSCLKSEL(1'd0), + .RXUSERRDY(a7litesataphy_rx_init_rxuserrdy0), + .RXUSRCLK(a7litesataphy_rxusrclk), + .RXUSRCLK2(a7litesataphy_rxusrclk2), + .SETERRSTATUS(1'd0), + .SIGVALIDCLK(a7litesataphy_oobclk), + .TSTIN(20'd1048575), + .TX8B10BBYPASS(1'd0), + .TX8B10BEN(1'd1), + .TXBUFDIFFCTRL(3'd4), + .TXCHARDISPMODE(1'd0), + .TXCHARDISPVAL(1'd0), + .TXCHARISK(a7litesataphy_txcharisk), + .TXCOMINIT(a7litesataphy_txcominit1), + .TXCOMSAS(1'd0), + .TXCOMWAKE(a7litesataphy_txcomwake1), + .TXDATA(a7litesataphy_txdata), + .TXDEEMPH(1'd0), + .TXDETECTRX(1'd0), + .TXDIFFCTRL(4'd8), + .TXDIFFPD(1'd0), + .TXDLYBYPASS(1'd1), + .TXDLYEN(1'd0), + .TXDLYHOLD(1'd0), + .TXDLYOVRDEN(1'd0), + .TXDLYSRESET(a7litesataphy_tx_init_txdlysreset0), + .TXDLYUPDOWN(1'd0), + .TXELECIDLE(a7litesataphy_txelecidle1), + .TXHEADER(1'd0), + .TXINHIBIT(1'd0), + .TXMAINCURSOR(1'd0), + .TXMARGIN(1'd0), + .TXOUTCLKSEL(2'd2), + .TXPCSRESET(1'd0), + .TXPD({2{a7litesataphy_txpd1}}), + .TXPDELECIDLEMODE(1'd0), + .TXPHALIGN(a7litesataphy_tx_init_txphalign0), + .TXPHALIGNEN(1'd0), + .TXPHDLYPD(1'd0), + .TXPHDLYRESET(1'd0), + .TXPHDLYTSTCLK(1'd0), + .TXPHINIT(a7litesataphy_tx_init_txphinit0), + .TXPHOVRDEN(1'd0), + .TXPIPPMEN(1'd0), + .TXPIPPMOVRDEN(1'd0), + .TXPIPPMPD(1'd0), + .TXPIPPMSEL(1'd1), + .TXPIPPMSTEPSIZE(1'd0), + .TXPISOPD(1'd0), + .TXPMARESET(1'd0), + .TXPOLARITY(a7litesataphy_tx_polarity), + .TXPOSTCURSOR(1'd0), + .TXPOSTCURSORINV(1'd0), + .TXPRBSFORCEERR(1'd0), + .TXPRBSSEL(1'd0), + .TXPRECURSOR(1'd0), + .TXPRECURSORINV(1'd0), + .TXRATE(1'd0), + .TXRATEMODE(1'd0), + .TXSEQUENCE(1'd0), + .TXSTARTSEQ(1'd0), + .TXSWING(1'd0), + .TXSYNCALLIN(1'd0), + .TXSYNCIN(1'd0), + .TXSYNCMODE(1'd0), + .TXSYSCLKSEL(1'd0), + .TXUSERRDY(a7litesataphy_tx_init_txuserrdy0), + .TXUSRCLK(a7litesataphy_txusrclk), + .TXUSRCLK2(a7litesataphy_txusrclk2), + .DMONITOROUT(a7litesataphy23), + .DRPDO(a7litesataphy_rx_init_drp_do), + .DRPRDY(a7litesataphy_rx_init_drp_rdy), + .EYESCANDATAERROR(a7litesataphy2), + .GTPTXN(fmc2sata_tx_n), + .GTPTXP(fmc2sata_tx_p), + .PCSRSVDOUT(a7litesataphy34), + .PHYSTATUS(a7litesataphy0), + .PMARSVDOUT0(a7litesataphy9), + .PMARSVDOUT1(a7litesataphy10), + .RXBUFSTATUS(a7litesataphy11), + .RXBYTEISALIGNED(a7litesataphy16), + .RXBYTEREALIGN(a7litesataphy17), + .RXCDRLOCK(a7litesataphy3), + .RXCHANBONDSEQ(a7litesataphy19), + .RXCHANISALIGNED(a7litesataphy21), + .RXCHANREALIGN(a7litesataphy22), + .RXCHARISCOMMA(a7litesataphy8), + .RXCHARISK(a7litesataphy_rxcharisk), + .RXCHBONDO(a7litesataphy20), + .RXCLKCORCNT(a7litesataphy6), + .RXCOMINITDET(a7litesataphy_rxcominitdet1), + .RXCOMMADET(a7litesataphy18), + .RXCOMSASDET(a7litesataphy32), + .RXCOMWAKEDET(a7litesataphy_rxcomwakedet1), + .RXDATA(a7litesataphy_rxdata), + .RXDATAVALID(a7litesataphy28), + .RXDISPERR(a7litesataphy_rxdisperr1), + .RXDLYSRESETDONE(a7litesataphy_rx_init_rxdlysresetdone0), + .RXELECIDLE(a7litesataphy33), + .RXHEADER(a7litesataphy29), + .RXHEADERVALID(a7litesataphy30), + .RXNOTINTABLE(a7litesataphy_rxnotintable1), + .RXOSINTDONE(a7litesataphy4), + .RXOSINTSTROBEDONE(a7litesataphy24), + .RXOSINTSTROBESTARTED(a7litesataphy5), + .RXOUTCLK(a7litesataphy_rxoutclk), + .RXOUTCLKFABRIC(a7litesataphy26), + .RXOUTCLKPCS(a7litesataphy27), + .RXPHALIGNDONE(a7litesataphy_rxphaligndone), + .RXPHMONITOR(a7litesataphy12), + .RXPHSLIPMONITOR(a7litesataphy13), + .RXPMARESETDONE(a7litesataphy_rx_init_rxpmaresetdone0), + .RXPRBSERR(a7litesataphy7), + .RXRATEDONE(a7litesataphy25), + .RXRESETDONE(a7litesataphy_rx_init_rxresetdone0), + .RXSTARTOFSEQ(a7litesataphy31), + .RXSTATUS(a7litesataphy14), + .RXSYNCDONE(a7litesataphy_rx_init_rxsyncdone0), + .RXSYNCOUT(a7litesataphy15), + .RXVALID(a7litesataphy1), + .TXBUFSTATUS(a7litesataphy36), + .TXCOMFINISH(a7litesataphy_txcomfinish1), + .TXDLYSRESETDONE(a7litesataphy_tx_init_txdlysresetdone0), + .TXGEARBOXREADY(a7litesataphy42), + .TXOUTCLK(a7litesataphy_txoutclk), + .TXOUTCLKFABRIC(a7litesataphy39), + .TXOUTCLKPCS(a7litesataphy40), + .TXPHALIGNDONE(a7litesataphy_tx_init_txphaligndone0), + .TXPHINITDONE(a7litesataphy_tx_init_txphinitdone0), + .TXPMARESETDONE(a7litesataphy35), + .TXRATEDONE(a7litesataphy41), + .TXRESETDONE(a7litesataphy_tx_init_txresetdone0), + .TXSYNCDONE(a7litesataphy37), + .TXSYNCOUT(a7litesataphy38) +); + +IBUFDS_GTE2 IBUFDS_GTE2( + .CEB(1'd0), + .I(fmc2sata_clk_p), + .IB(fmc2sata_clk_n), + .O(crg_refclk) +); + +BUFG BUFG_5( + .I(a7litesataphy_txoutclk), + .O(sata_tx_clk) +); + +BUFG BUFG_6( + .I(a7litesataphy_rxoutclk), + .O(sata_rx_clk) +); + +reg [37:0] storage_11[0:7]; +reg [2:0] memadr_3; +reg [2:0] memadr_4; +always @(posedge sys_clk) begin + if (datapath_tx_fifo_wrport_we) + storage_11[datapath_tx_fifo_wrport_adr] <= datapath_tx_fifo_wrport_dat_w; + memadr_3 <= datapath_tx_fifo_wrport_adr; +end + +always @(posedge sata_tx_clk) begin + memadr_4 <= datapath_tx_fifo_rdport_adr; +end + +assign datapath_tx_fifo_wrport_dat_r = storage_11[memadr_3]; +assign datapath_tx_fifo_rdport_dat_r = storage_11[memadr_4]; + +reg [37:0] storage_12[0:7]; +reg [2:0] memadr_5; +reg [2:0] memadr_6; +always @(posedge sata_rx_clk) begin + if (datapath_rx_fifo_wrport_we) + storage_12[datapath_rx_fifo_wrport_adr] <= datapath_rx_fifo_wrport_dat_w; + memadr_5 <= datapath_rx_fifo_wrport_adr; +end + +always @(posedge sys_clk) begin + memadr_6 <= datapath_rx_fifo_rdport_adr; +end + +assign datapath_rx_fifo_wrport_dat_r = storage_12[memadr_5]; +assign datapath_rx_fifo_rdport_dat_r = storage_12[memadr_6]; + +reg [34:0] storage_13[0:1]; +reg [34:0] memdat_13; +always @(posedge sys_clk) begin + if (link_litesatalinkrx_crc_syncfifo_wrport_we) + storage_13[link_litesatalinkrx_crc_syncfifo_wrport_adr] <= link_litesatalinkrx_crc_syncfifo_wrport_dat_w; + memdat_13 <= storage_13[link_litesatalinkrx_crc_syncfifo_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign link_litesatalinkrx_crc_syncfifo_wrport_dat_r = memdat_13; +assign link_litesatalinkrx_crc_syncfifo_rdport_dat_r = storage_13[link_litesatalinkrx_crc_syncfifo_rdport_adr]; + +reg [34:0] storage_14[0:127]; +reg [34:0] memdat_14; +always @(posedge sys_clk) begin + if (link_rx_buffer_wrport_we) + storage_14[link_rx_buffer_wrport_adr] <= link_rx_buffer_wrport_dat_w; + memdat_14 <= storage_14[link_rx_buffer_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign link_rx_buffer_wrport_dat_r = memdat_14; +assign link_rx_buffer_rdport_dat_r = storage_14[link_rx_buffer_rdport_adr]; + +reg [33:0] storage_15[0:127]; +reg [33:0] memdat_15; +always @(posedge sys_clk) begin + if (sata_sector2mem_buf_wrport_we) + storage_15[sata_sector2mem_buf_wrport_adr] <= sata_sector2mem_buf_wrport_dat_w; + memdat_15 <= storage_15[sata_sector2mem_buf_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sata_sector2mem_buf_wrport_dat_r = memdat_15; +assign sata_sector2mem_buf_rdport_dat_r = storage_15[sata_sector2mem_buf_rdport_adr]; + +reg [33:0] storage_16[0:127]; +reg [33:0] memdat_16; +always @(posedge sys_clk) begin + if (sata_mem2sector_buf_wrport_we) + storage_16[sata_mem2sector_buf_wrport_adr] <= sata_mem2sector_buf_wrport_dat_w; + memdat_16 <= storage_16[sata_mem2sector_buf_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sata_mem2sector_buf_wrport_dat_r = memdat_16; +assign sata_mem2sector_buf_rdport_dat_r = storage_16[sata_mem2sector_buf_rdport_adr]; + +VexRiscv VexRiscv( + .clk(sys_clk), + .dBusWishbone_ACK(cpu_dbus_ack), + .dBusWishbone_DAT_MISO(cpu_dbus_dat_r), + .dBusWishbone_ERR(cpu_dbus_err), + .externalInterruptArray(cpu_interrupt), + .externalResetVector(vexriscv), + .iBusWishbone_ACK(cpu_ibus_ack), + .iBusWishbone_DAT_MISO(cpu_ibus_dat_r), + .iBusWishbone_ERR(cpu_ibus_err), + .reset((sys_rst | cpu_reset_1)), + .softwareInterrupt(1'd0), + .timerInterrupt(1'd0), + .dBusWishbone_ADR(cpu_dbus_adr), + .dBusWishbone_BTE(cpu_dbus_bte), + .dBusWishbone_CTI(cpu_dbus_cti), + .dBusWishbone_CYC(cpu_dbus_cyc), + .dBusWishbone_DAT_MOSI(cpu_dbus_dat_w), + .dBusWishbone_SEL(cpu_dbus_sel), + .dBusWishbone_STB(cpu_dbus_stb), + .dBusWishbone_WE(cpu_dbus_we), + .iBusWishbone_ADR(cpu_ibus_adr), + .iBusWishbone_BTE(cpu_ibus_bte), + .iBusWishbone_CTI(cpu_ibus_cti), + .iBusWishbone_CYC(cpu_ibus_cyc), + .iBusWishbone_DAT_MOSI(cpu_ibus_dat_w), + .iBusWishbone_SEL(cpu_ibus_sel), + .iBusWishbone_STB(cpu_ibus_stb), + .iBusWishbone_WE(cpu_ibus_we) +); + +FD FD( + .C(crg_clkin), + .D(crg_reset), + .Q(subfragments_reset0) +); + +FD FD_1( + .C(crg_clkin), + .D(subfragments_reset0), + .Q(subfragments_reset1) +); + +FD FD_2( + .C(crg_clkin), + .D(subfragments_reset1), + .Q(subfragments_reset2) +); + +FD FD_3( + .C(crg_clkin), + .D(subfragments_reset2), + .Q(subfragments_reset3) +); + +FD FD_4( + .C(crg_clkin), + .D(subfragments_reset3), + .Q(subfragments_reset4) +); + +FD FD_5( + .C(crg_clkin), + .D(subfragments_reset4), + .Q(subfragments_reset5) +); + +FD FD_6( + .C(crg_clkin), + .D(subfragments_reset5), + .Q(subfragments_reset6) +); + +FD FD_7( + .C(crg_clkin), + .D(subfragments_reset6), + .Q(subfragments_reset7) +); + +PLLE2_ADV #( + .CLKFBOUT_MULT(5'd16), + .CLKIN1_PERIOD(10.0), + .CLKOUT0_DIVIDE(5'd20), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(3'd5), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(3'd5), + .CLKOUT2_PHASE(7'd90), + .CLKOUT3_DIVIDE(4'd8), + .CLKOUT3_PHASE(1'd0), + .CLKOUT4_DIVIDE(5'd16), + .CLKOUT4_PHASE(1'd0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV ( + .CLKFBIN(subfragments_pll_fb), + .CLKIN1(crg_clkin), + .RST(subfragments_reset7), + .CLKFBOUT(subfragments_pll_fb), + .CLKOUT0(crg_clkout0), + .CLKOUT1(crg_clkout1), + .CLKOUT2(crg_clkout2), + .CLKOUT3(crg_clkout3), + .CLKOUT4(crg_clkout4), + .LOCKED(crg_locked) +); + +reg [7:0] data_mem_grain0[0:511]; +reg [8:0] memadr_7; +always @(posedge sys_clk) begin + if (data_port_we[0]) + data_mem_grain0[data_port_adr] <= data_port_dat_w[7:0]; + memadr_7 <= data_port_adr; +end + +assign data_port_dat_r[7:0] = data_mem_grain0[memadr_7]; + +reg [7:0] data_mem_grain1[0:511]; +reg [8:0] memadr_8; +always @(posedge sys_clk) begin + if (data_port_we[1]) + data_mem_grain1[data_port_adr] <= data_port_dat_w[15:8]; + memadr_8 <= data_port_adr; +end + +assign data_port_dat_r[15:8] = data_mem_grain1[memadr_8]; + +reg [7:0] data_mem_grain2[0:511]; +reg [8:0] memadr_9; +always @(posedge sys_clk) begin + if (data_port_we[2]) + data_mem_grain2[data_port_adr] <= data_port_dat_w[23:16]; + memadr_9 <= data_port_adr; +end + +assign data_port_dat_r[23:16] = data_mem_grain2[memadr_9]; + +reg [7:0] data_mem_grain3[0:511]; +reg [8:0] memadr_10; +always @(posedge sys_clk) begin + if (data_port_we[3]) + data_mem_grain3[data_port_adr] <= data_port_dat_w[31:24]; + memadr_10 <= data_port_adr; +end + +assign data_port_dat_r[31:24] = data_mem_grain3[memadr_10]; + +reg [7:0] data_mem_grain4[0:511]; +reg [8:0] memadr_11; +always @(posedge sys_clk) begin + if (data_port_we[4]) + data_mem_grain4[data_port_adr] <= data_port_dat_w[39:32]; + memadr_11 <= data_port_adr; +end + +assign data_port_dat_r[39:32] = data_mem_grain4[memadr_11]; + +reg [7:0] data_mem_grain5[0:511]; +reg [8:0] memadr_12; +always @(posedge sys_clk) begin + if (data_port_we[5]) + data_mem_grain5[data_port_adr] <= data_port_dat_w[47:40]; + memadr_12 <= data_port_adr; +end + +assign data_port_dat_r[47:40] = data_mem_grain5[memadr_12]; + +reg [7:0] data_mem_grain6[0:511]; +reg [8:0] memadr_13; +always @(posedge sys_clk) begin + if (data_port_we[6]) + data_mem_grain6[data_port_adr] <= data_port_dat_w[55:48]; + memadr_13 <= data_port_adr; +end + +assign data_port_dat_r[55:48] = data_mem_grain6[memadr_13]; + +reg [7:0] data_mem_grain7[0:511]; +reg [8:0] memadr_14; +always @(posedge sys_clk) begin + if (data_port_we[7]) + data_mem_grain7[data_port_adr] <= data_port_dat_w[63:56]; + memadr_14 <= data_port_adr; +end + +assign data_port_dat_r[63:56] = data_mem_grain7[memadr_14]; + +reg [7:0] data_mem_grain8[0:511]; +reg [8:0] memadr_15; +always @(posedge sys_clk) begin + if (data_port_we[8]) + data_mem_grain8[data_port_adr] <= data_port_dat_w[71:64]; + memadr_15 <= data_port_adr; +end + +assign data_port_dat_r[71:64] = data_mem_grain8[memadr_15]; + +reg [7:0] data_mem_grain9[0:511]; +reg [8:0] memadr_16; +always @(posedge sys_clk) begin + if (data_port_we[9]) + data_mem_grain9[data_port_adr] <= data_port_dat_w[79:72]; + memadr_16 <= data_port_adr; +end + +assign data_port_dat_r[79:72] = data_mem_grain9[memadr_16]; + +reg [7:0] data_mem_grain10[0:511]; +reg [8:0] memadr_17; +always @(posedge sys_clk) begin + if (data_port_we[10]) + data_mem_grain10[data_port_adr] <= data_port_dat_w[87:80]; + memadr_17 <= data_port_adr; +end + +assign data_port_dat_r[87:80] = data_mem_grain10[memadr_17]; + +reg [7:0] data_mem_grain11[0:511]; +reg [8:0] memadr_18; +always @(posedge sys_clk) begin + if (data_port_we[11]) + data_mem_grain11[data_port_adr] <= data_port_dat_w[95:88]; + memadr_18 <= data_port_adr; +end + +assign data_port_dat_r[95:88] = data_mem_grain11[memadr_18]; + +reg [7:0] data_mem_grain12[0:511]; +reg [8:0] memadr_19; +always @(posedge sys_clk) begin + if (data_port_we[12]) + data_mem_grain12[data_port_adr] <= data_port_dat_w[103:96]; + memadr_19 <= data_port_adr; +end + +assign data_port_dat_r[103:96] = data_mem_grain12[memadr_19]; + +reg [7:0] data_mem_grain13[0:511]; +reg [8:0] memadr_20; +always @(posedge sys_clk) begin + if (data_port_we[13]) + data_mem_grain13[data_port_adr] <= data_port_dat_w[111:104]; + memadr_20 <= data_port_adr; +end + +assign data_port_dat_r[111:104] = data_mem_grain13[memadr_20]; + +reg [7:0] data_mem_grain14[0:511]; +reg [8:0] memadr_21; +always @(posedge sys_clk) begin + if (data_port_we[14]) + data_mem_grain14[data_port_adr] <= data_port_dat_w[119:112]; + memadr_21 <= data_port_adr; +end + +assign data_port_dat_r[119:112] = data_mem_grain14[memadr_21]; + +reg [7:0] data_mem_grain15[0:511]; +reg [8:0] memadr_22; +always @(posedge sys_clk) begin + if (data_port_we[15]) + data_mem_grain15[data_port_adr] <= data_port_dat_w[127:120]; + memadr_22 <= data_port_adr; +end + +assign data_port_dat_r[127:120] = data_mem_grain15[memadr_22]; + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys4x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(sys4x_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_6 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_7 ( + .C(idelay_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl3), + .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_8 ( + .C(idelay_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl3), + .Q(idelay_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_9 ( + .C(clk100_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl4), + .Q(xilinxasyncresetsynchronizerimpl4_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_10 ( + .C(clk100_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl4_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl4), + .Q(clk100_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_11 ( + .C(sata_tx_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl5), + .Q(xilinxasyncresetsynchronizerimpl5_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_12 ( + .C(sata_tx_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl5_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl5), + .Q(sata_tx_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_13 ( + .C(sata_rx_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl6), + .Q(xilinxasyncresetsynchronizerimpl6_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_14 ( + .C(sata_rx_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl6_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl6), + .Q(sata_rx_rst) +); + +endmodule diff --git a/xc7/litex_sata_demo/mem.init b/xc7/litex_sata_demo/mem.init new file mode 100644 index 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+31 +30 +3a +31 +32 +3a +31 +37 +0 diff --git a/xc7/litex_sata_demo/nexys_video.xdc b/xc7/litex_sata_demo/nexys_video.xdc new file mode 100644 index 0000000..09a6c52 --- /dev/null +++ b/xc7/litex_sata_demo/nexys_video.xdc @@ -0,0 +1,340 @@ +################################################################################ +# IO constraints +################################################################################ +# serial:0.tx +set_property LOC AA19 [get_ports {serial_tx}] +set_property IOSTANDARD LVCMOS33 [get_ports {serial_tx}] + +# serial:0.rx +set_property LOC V18 [get_ports {serial_rx}] +set_property IOSTANDARD LVCMOS33 [get_ports {serial_rx}] + +# cpu_reset:0 +set_property LOC G4 [get_ports {cpu_reset}] +set_property IOSTANDARD LVCMOS15 [get_ports {cpu_reset}] + +# clk100:0 +set_property LOC R4 [get_ports {clk100}] +set_property IOSTANDARD LVCMOS33 [get_ports {clk100}] + +# ddram:0.a +set_property LOC M2 [get_ports {ddram_a[0]}] +set_property SLEW FAST [get_ports {ddram_a[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}] + +# ddram:0.a +set_property LOC M5 [get_ports {ddram_a[1]}] +set_property SLEW FAST [get_ports {ddram_a[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}] + +# ddram:0.a +set_property LOC M3 [get_ports {ddram_a[2]}] +set_property SLEW FAST [get_ports {ddram_a[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}] + +# ddram:0.a +set_property LOC M1 [get_ports {ddram_a[3]}] +set_property SLEW FAST [get_ports {ddram_a[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}] + +# ddram:0.a +set_property LOC L6 [get_ports {ddram_a[4]}] +set_property SLEW FAST [get_ports {ddram_a[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}] + +# ddram:0.a +set_property LOC P1 [get_ports {ddram_a[5]}] +set_property SLEW FAST [get_ports {ddram_a[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}] + +# ddram:0.a +set_property LOC N3 [get_ports {ddram_a[6]}] +set_property SLEW FAST [get_ports {ddram_a[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}] + +# ddram:0.a +set_property LOC N2 [get_ports {ddram_a[7]}] +set_property SLEW FAST [get_ports {ddram_a[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}] + +# ddram:0.a +set_property LOC M6 [get_ports {ddram_a[8]}] +set_property SLEW FAST [get_ports {ddram_a[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}] + +# ddram:0.a +set_property LOC R1 [get_ports {ddram_a[9]}] +set_property SLEW FAST [get_ports {ddram_a[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}] + +# ddram:0.a +set_property LOC L5 [get_ports {ddram_a[10]}] +set_property SLEW FAST [get_ports {ddram_a[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}] + +# ddram:0.a +set_property LOC N5 [get_ports {ddram_a[11]}] +set_property SLEW FAST [get_ports {ddram_a[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}] + +# ddram:0.a +set_property LOC N4 [get_ports {ddram_a[12]}] +set_property SLEW FAST [get_ports {ddram_a[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}] + +# ddram:0.a +set_property LOC P2 [get_ports {ddram_a[13]}] +set_property SLEW FAST [get_ports {ddram_a[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}] + +# ddram:0.a +set_property LOC P6 [get_ports {ddram_a[14]}] +set_property SLEW FAST [get_ports {ddram_a[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}] + +# ddram:0.ba +set_property LOC L3 [get_ports {ddram_ba[0]}] +set_property SLEW FAST [get_ports {ddram_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}] + +# ddram:0.ba +set_property LOC K6 [get_ports {ddram_ba[1]}] +set_property SLEW FAST [get_ports {ddram_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}] + +# ddram:0.ba +set_property LOC L4 [get_ports {ddram_ba[2]}] +set_property SLEW FAST [get_ports {ddram_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}] + +# ddram:0.ras_n +set_property LOC J4 [get_ports {ddram_ras_n}] +set_property SLEW FAST [get_ports {ddram_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}] + +# ddram:0.cas_n +set_property LOC K3 [get_ports {ddram_cas_n}] +set_property SLEW FAST [get_ports {ddram_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}] + +# ddram:0.we_n +set_property LOC L1 [get_ports {ddram_we_n}] +set_property SLEW FAST [get_ports {ddram_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}] + +# ddram:0.dm +set_property LOC G3 [get_ports {ddram_dm[0]}] +set_property SLEW FAST [get_ports {ddram_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}] + +# ddram:0.dm +set_property LOC F1 [get_ports {ddram_dm[1]}] +set_property SLEW FAST [get_ports {ddram_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}] + +# ddram:0.dq +set_property LOC G2 [get_ports {ddram_dq[0]}] +set_property SLEW FAST [get_ports {ddram_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}] + +# ddram:0.dq +set_property LOC H4 [get_ports {ddram_dq[1]}] +set_property SLEW FAST [get_ports {ddram_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}] + +# ddram:0.dq +set_property LOC H5 [get_ports {ddram_dq[2]}] +set_property SLEW FAST [get_ports {ddram_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}] + +# ddram:0.dq +set_property LOC J1 [get_ports {ddram_dq[3]}] +set_property SLEW FAST [get_ports {ddram_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}] + +# ddram:0.dq +set_property LOC K1 [get_ports {ddram_dq[4]}] +set_property SLEW FAST [get_ports {ddram_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}] + +# ddram:0.dq +set_property LOC H3 [get_ports {ddram_dq[5]}] +set_property SLEW FAST [get_ports {ddram_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}] + +# ddram:0.dq +set_property LOC H2 [get_ports {ddram_dq[6]}] +set_property SLEW FAST [get_ports {ddram_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}] + +# ddram:0.dq +set_property LOC J5 [get_ports {ddram_dq[7]}] +set_property SLEW FAST [get_ports {ddram_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}] + +# ddram:0.dq +set_property LOC E3 [get_ports {ddram_dq[8]}] +set_property SLEW FAST [get_ports {ddram_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}] + +# ddram:0.dq +set_property LOC B2 [get_ports {ddram_dq[9]}] +set_property SLEW FAST [get_ports {ddram_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}] + +# ddram:0.dq +set_property LOC F3 [get_ports {ddram_dq[10]}] +set_property SLEW FAST [get_ports {ddram_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}] + +# ddram:0.dq +set_property LOC D2 [get_ports {ddram_dq[11]}] +set_property SLEW FAST [get_ports {ddram_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}] + +# ddram:0.dq +set_property LOC C2 [get_ports {ddram_dq[12]}] +set_property SLEW FAST [get_ports {ddram_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}] + +# ddram:0.dq +set_property LOC A1 [get_ports {ddram_dq[13]}] +set_property SLEW FAST [get_ports {ddram_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}] + +# ddram:0.dq +set_property LOC E2 [get_ports {ddram_dq[14]}] +set_property SLEW FAST [get_ports {ddram_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}] + +# ddram:0.dq +set_property LOC B1 [get_ports {ddram_dq[15]}] +set_property SLEW FAST [get_ports {ddram_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}] + +# ddram:0.dqs_p +set_property LOC K2 [get_ports {ddram_dqs_p[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}] + +# ddram:0.dqs_p +set_property LOC E1 [get_ports {ddram_dqs_p[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}] + +# ddram:0.dqs_n +set_property LOC J2 [get_ports {ddram_dqs_n[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}] + +# ddram:0.dqs_n +set_property LOC D1 [get_ports {ddram_dqs_n[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}] + +# ddram:0.clk_p +set_property LOC P5 [get_ports {ddram_clk_p}] +set_property SLEW FAST [get_ports {ddram_clk_p}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}] + +# ddram:0.clk_n +set_property LOC P4 [get_ports {ddram_clk_n}] +set_property SLEW FAST [get_ports {ddram_clk_n}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}] + +# ddram:0.cke +set_property LOC J6 [get_ports {ddram_cke}] +set_property SLEW FAST [get_ports {ddram_cke}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}] + +# ddram:0.odt +set_property LOC K4 [get_ports {ddram_odt}] +set_property SLEW FAST [get_ports {ddram_odt}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}] + +# ddram:0.reset_n +set_property LOC G1 [get_ports {ddram_reset_n}] +set_property SLEW FAST [get_ports {ddram_reset_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_reset_n}] + +# fmc2sata:0.clk_p +set_property LOC F10 [get_ports {fmc2sata_clk_p}] + +# fmc2sata:0.clk_n +set_property LOC E10 [get_ports {fmc2sata_clk_n}] + +# fmc2sata:0.tx_p +set_property LOC D7 [get_ports {fmc2sata_tx_p}] + +# fmc2sata:0.tx_n +set_property LOC C7 [get_ports {fmc2sata_tx_n}] + +# fmc2sata:0.rx_p +set_property LOC D9 [get_ports {fmc2sata_rx_p}] + +# fmc2sata:0.rx_n +set_property LOC C9 [get_ports {fmc2sata_rx_n}] + +# user_led:0 +set_property LOC T14 [get_ports {user_led0}] +set_property IOSTANDARD LVCMOS25 [get_ports {user_led0}] + +# user_led:1 +set_property LOC T15 [get_ports {user_led1}] +set_property IOSTANDARD LVCMOS25 [get_ports {user_led1}] + +# user_led:2 +set_property LOC T16 [get_ports {user_led2}] +set_property IOSTANDARD LVCMOS25 [get_ports {user_led2}] + +# user_led:3 +set_property LOC U16 [get_ports {user_led3}] +set_property IOSTANDARD LVCMOS25 [get_ports {user_led3}] + +# user_led:4 +set_property LOC V15 [get_ports {user_led4}] +set_property IOSTANDARD LVCMOS25 [get_ports {user_led4}] + +# user_led:5 +set_property LOC W16 [get_ports {user_led5}] +set_property IOSTANDARD LVCMOS25 [get_ports {user_led5}] + +# user_led:6 +set_property LOC W15 [get_ports {user_led6}] +set_property IOSTANDARD LVCMOS25 [get_ports {user_led6}] + +# user_led:7 +set_property LOC Y13 [get_ports {user_led7}] +set_property IOSTANDARD LVCMOS25 [get_ports {user_led7}] + +# vadj:0 +set_property LOC AA13 [get_ports {vadj[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {vadj[0]}] + +# vadj:1 +set_property LOC AB17 [get_ports {vadj[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {vadj[1]}] + +################################################################################ +# Design constraints +################################################################################ + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] + +################################################################################