Raname to F4PGA

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

.github/scripts/generate_job_matrix.py

@@ -18,7 +18,7 @@
 
 from sys import argv as sys_argv
 
-isFork = len(sys_argv)>1 and sys_argv[1] != 'SymbiFlow/symbiflow-examples'
+isFork = len(sys_argv)>1 and sys_argv[1] != 'chipsalliance/f4pga-examples'
 
 runs_on = (
     'ubuntu-latest'

.github/scripts/install-toolchain.sh

@@ -25,7 +25,7 @@ source ${CURRENT_DIR}/common.sh
 
 function help() {
    echo
-   echo "Install the SymbiFlow toolchain as described in the sphinx documentation"
+   echo "Install the F4PGA toolchain as described in the sphinx documentation"
    echo
    echo "Syntax: $0 fpga_family os"
    echo "Arguments:"
@@ -45,4 +45,4 @@ fi
 fpga_family=$1
 os=$2
 
-tuttest_exec docs/getting-symbiflow.rst:install-reqs-$os,wget-conda,conda-install-dir,fpga-fam-$fpga_family,conda-setup,download-arch-def-$fpga_family
+tuttest_exec docs/getting-f4pga.rst:install-reqs-$os,wget-conda,conda-install-dir,fpga-fam-$fpga_family,conda-setup,download-arch-def-$fpga_family

.github/workflows/sphinx-tuttest.yml

@@ -69,7 +69,7 @@ jobs:
           wget https://github.com/antmicro/tuttest/releases/download/v0.2-beta/tuttest -O /usr/bin/tuttest
           chmod a+rx /usr/bin/tuttest
 
-      - name: Install SymbiFlow toolchain
+      - name: Install F4PGA toolchain
         run: bash .github/scripts/install-toolchain.sh ${{matrix.fpga-fam}} ${{matrix.os}}
 
       - name: Build examples
@@ -77,7 +77,7 @@ jobs:
 
       - uses: actions/upload-artifact@v2
         with:
-          name: symbiflow-examples-bitstreams
+          name: f4pga-examples-bitstreams
           path: |
             **/*.bit
             **/plot_*.svg

Makefile

@@ -22,7 +22,7 @@ VERILOG_SRCS=$(shell find . -name "*.v" -not -path "./env/*" -not -path "./symbi
 
 env:
 	conda env create -f environment.yml
-	conda activate symbiflow-examples
+	conda activate f4pga-examples
 
 format:
 	yapf -i ${PYTHON_SRCS}
@@ -36,6 +36,6 @@ format:
 clean::
 	rm -rf env/
 	conda deactivate
-	conda env remove -n symbiflow-examples
+	conda env remove -n f4pga-examples
 
 .PHONY: env format clean

README.rst

@@ -1,19 +1,19 @@
-SymbiFlow examples
+F4PGA examples
-==================
+==============
 
-Please refer to the `project documentation <https://symbiflow-examples.readthedocs.io>`_ 
+Please refer to the `project documentation <https://f4pga-examples.readthedocs.io>`_
-for a proper guide on how to run these examples as well as instructions on how to build and 
+for a proper guide on how to run these examples as well as instructions on how to build and
-compile your own HDL designs using the symbiflow toolchain. 
+compile your own HDL designs using the F4PGA toolchain.
 
-.. image:: https://github.com/symbiflow/symbiflow-examples/workflows/doc-test/badge.svg?branch=master
+.. image:: https://github.com/chipsalliance/f4pga-examples/workflows/doc-test/badge.svg?branch=master
-   :target: https://github.com/SymbiFlow/symbiflow-examples/actions
+   :target: https://github.com/chipsalliance/f4pga-examples/actions
 
-.. image:: https://readthedocs.org/projects/symbiflow-examples/badge/?version=latest
+.. image:: https://readthedocs.org/projects/f4pga-examples/badge/?version=latest
-   :target: https://symbiflow-examples.readthedocs.io/en/latest/?badge=latest
+   :target: https://f4pga-examples.readthedocs.io/en/latest/?badge=latest
    :alt: Documentation Status
 
 This repository provides example FPGA designs that can be built using the
-SymbiFlow open source toolchain. These examples target the Xilinx 7-Series and
+F4PGA open source toolchain. These examples target the Xilinx 7-Series and
 the QuickLogic EOS S3 devices.
 
 The repository includes:
@@ -23,11 +23,11 @@ The repository includes:
   * Verilog code
   * Pin constraints files
   * Timing constraints files
-  * Makefiles for running the SymbiFlow toolchain
+  * Makefiles for running the F4PGA toolchain
-* `docs/ <./docs>`_ - Guide on how to get started with SymbiFlow and build provided examples
+* `docs/ <./docs>`_ - Guide on how to get started with F4PGA and build provided examples
 * `.github/ <./.github>`_ - Directory with CI configuration and scripts
 
-The examples provided by this repository are automatically built by extracting 
+The examples provided by this repository are automatically built by extracting
 necessary code snippets with `tuttest <https://github.com/antmicro/tuttest>`_.
 
 Building those docs

common/common.mk

@@ -78,7 +78,7 @@ download: ${BOARD_BUILDDIR}/${TOP}.bit
 	elif [ $(TARGET)='basys3' ]; then \
 	  openocd -f ~/opt/symbiflow/xc7/conda/envs/xc7/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 ${BOARD_BUILDDIR}/${TOP}.bit; exit"; \
 	else  \
-	  echo "The commands needed to download the bitstreams to the board type specified are not currently supported by the symbiflow makefiles. \
+	  echo "The commands needed to download the bitstreams to the board type specified are not currently supported by the F4PGA makefiles. \
     Please see documentation for more information."; \
 	fi
 

docs/building-examples.rst

@@ -1,4 +1,3 @@
-
 Building example designs
 ========================
 
@@ -8,7 +7,7 @@ set it to earlier, for example:
 .. code-block:: bash
    :name: export-install-dir
 
-   export INSTALL_DIR=~/opt/symbiflow
+   export INSTALL_DIR=~/opt/f4pga
 
 Select your FPGA family:
 

docs/collect_readmes.py

@@ -212,7 +212,7 @@ def get_blocks(text):
 
 def fill_context(text):
     """
-    Creates a jinja context dictionary for a SymbiFlow Toolchain usage example.
+    Creates a jinja context dictionary for a F4PGA Toolchain usage example.
     The dictionary contains all the important information from the example's README.
 
     Args:

docs/conf.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-
 #
-# Copyright (C) 2020  The SymbiFlow Authors.
+# Copyright (C) 2020-2022 F4PGA Authors.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -36,9 +36,9 @@ sys.path.insert(0, os.path.abspath('.'))
 
 # -- Project information -----------------------------------------------------
 
-project = u'SymbiFlow examples'
+project = u'F4PGA examples'
-authors = u'SymbiFlow'
+authors = u'F4PGA Authors'
-copyright = authors + u', 2020'
+copyright = authors + u', 2020 - 2022'
 
 # -- General configuration ---------------------------------------------------
 
@@ -69,7 +69,7 @@ html_show_sourcelink = True
 html_theme = 'sphinx_symbiflow_theme'
 
 html_theme_options = {
-    'github_url' : 'https://github.com/SymbiFlow/symbiflow-examples',
+    'github_url' : 'https://github.com/chipsalliance/F4PGA-examples',
     'globaltoc_collapse': True
 }
 

docs/customizing-makefiles.rst

@@ -5,14 +5,14 @@ A powerful tool in creating your own designs is understanding how to generate yo
 compile projects. This tutorial walks you through how to do that.
 
 If you would like to use methods other than a Makefile to build and compile your designs 
-(such as python or bash scripts) or if you would like to learn more about the various Symbiflow
+(such as python or bash scripts) or if you would like to learn more about the various F4PGA
 commands used by the common Makefile to build and compile designs take a look at the
 `Understanding Toolchain Commands <understanding-commands.html>`_ page.
 
 Example 
 -------
 
-By including Symbiflow's provided common Makefile in your designs, running the commands necessary for building 
+By including F4PGA's provided common Makefile in your designs, running the commands necessary for building 
 your personal projects is incredibly simple. All you have to do is run a few simple commands and set
 a few variables. 
 
@@ -32,7 +32,7 @@ Create a makefile for your project by running ``touch Makefile``, and add the fo
    PCF := ${current_dir}/<name of your xdc file if applicable>
    SDC := ${current_dir}/<name of your sdc file if applicable>
 
-   include <path to symbiflow-examples root directory>/common/common.mk
+   include <path to f4pga-examples root directory>/common/common.mk
 
 Lets talk briefly about each of the commands in the above makefile
 
@@ -72,7 +72,7 @@ above to a ``.sv``.
 
 .. note::
 
-   As of this writing, symbiflow only offers full support for Verilog by default.
+   As of this writing, F4PGAw only offers full support for Verilog by default.
    SystemVerilog can also be run through the toolchain but more complicated 
    designs may not be fully supported. 
 
@@ -109,9 +109,9 @@ your design. The general syntax depends on whether you are using XDC files or a
 A Note on the example designs use of ifeq/else ifeq blocks
 -------------------------------------------------------------
 
-If you look at the Makefiles from the example designs within Symbiflow 
+If you look at the Makefiles from the example designs within F4PGA
 (i.e. counter test, Picosoc, etc.), you will find an ifeq else ifeq block. The following snippet 
-is from lines 9-39 of `the Makefile from counter test <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/counter_test/Makefile>`_:
+is from lines 9-39 of `the Makefile from counter test <https://github.com/chipsalliance/f4pga-examples/blob/master/xc7/counter_test/Makefile>`_:
 
 
 .. code-block:: bash

docs/getting-f4pga.rst

@@ -1,7 +1,7 @@
-Getting SymbiFlow
+Getting F4PGA
-=================
+=============
 
-This section describes how to install SymbiFlow and set up a fully working
+This section describes how to install F4PGA and set up a fully working
 environment to later build example designs.
 
 Prerequisites
@@ -43,18 +43,18 @@ To be able to follow through this tutorial, install the following software:
          dnf install -y findutils git wget which xz
 
 
-Next, clone the SymbiFlow examples repository and enter it:
+Next, clone the F4PGA examples repository and enter it:
 
 .. code-block:: bash
-   :name: get-symbiflow
+   :name: get-f4pga
 
-   git clone https://github.com/SymbiFlow/symbiflow-examples
+   git clone https://github.com/F4PGA/f4pga-examples
-   cd symbiflow-examples
+   cd f4pga-examples
 
 Toolchain installation
 ----------------------
 
-Now we are able to install the SymbiFlow toolchain. This procedure is divided
+Now we are able to install the F4PGA toolchain. This procedure is divided
 into three steps:
 
 - installing the Conda package manager,
@@ -64,7 +64,7 @@ into three steps:
 Conda
 ~~~~~
 
-Download Conda installer script into the symbiflow-examples directory:
+Download Conda installer script into the f4pga-examples directory:
 
 .. code-block:: bash
    :name: wget-conda
@@ -75,14 +75,14 @@ Choose the install directory
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The install directory can either be in your home directory
-such as ``~/opt/symbiflow`` or in a system directory such as ``/opt/symbiflow``.
+such as ``~/opt/f4pga`` or in a system directory such as ``/opt/f4pga``.
 If you choose a system directory, you will need root permission to perform the installation,
 and so you will need to add some ``sudo`` commands to the instructions below.
 
 .. code-block:: bash
    :name: conda-install-dir
 
-   export INSTALL_DIR=~/opt/symbiflow
+   export INSTALL_DIR=~/opt/f4pga
 
 Toolchain
 ~~~~~~~~~

docs/index.rst

@@ -1,8 +1,8 @@
-Welcome to SymbiFlow examples!
+Welcome to F4PGA examples!
-==============================
+==========================
 
-This guide explains how to get started with SymbiFlow and build example designs
+This guide explains how to get started with F4PGA and build example designs
-from the `SymbiFlow Examples <https://github.com/symbiflow/symbiflow-examples>`_
+from the `F4PGA Examples <https://github.com/chipsalliance/f4pga-examples>`_
 GitHub repository. It currently focuses on the following FPGA families:
 
 - Artix-7 from Xilinx,
@@ -10,18 +10,18 @@ GitHub repository. It currently focuses on the following FPGA families:
 
 Follow this guide to:
 
-- :doc:`install SymbiFlow <getting-symbiflow>` and all of its dependencies,
+- :doc:`install F4PGA <getting-symbiflow>` and all of its dependencies,
 - :doc:`build <building-examples>` and :doc:`upload <running-examples>`
   example designs onto the devboard of your choice.
-- compile and run :doc:`your own designs<personal-designs>` using the Symbiflow toolchain.
+- compile and run :doc:`your own designs<personal-designs>` using the F4PGA toolchain.
 - :doc:`customize the Makefile<customizing-makefiles>` for your own designs.
-- gain valuable information about `Understanding Toolchain Commands in Symbiflow <understanding-commands.html>`_
+- gain valuable information about `Understanding Toolchain Commands in F4PGA <understanding-commands.html>`_
 
 
-About SymbiFlow
+About F4PGA
----------------
+-----------
 
-SymbiFlow is a fully open source toolchain for the development of FPGAs,
+F4PGA is a fully open source toolchain for the development of FPGAs,
 currently targeting chips from multiple vendors, e.g.:
 
 - Xilinx 7-Series
@@ -33,7 +33,7 @@ currently targeting chips from multiple vendors, e.g.:
    :maxdepth: 2
    :caption: Sections
 
-   getting-symbiflow
+   getting-f4pga
    building-examples
    running-examples
    personal-designs

docs/personal-designs.rst

@@ -2,10 +2,10 @@ Building Custom Designs
 ========================
 
 This section describes how to compile and download your own designs to an FPGA using only 
-the Symbiflow toolchain.
+the F4PGA toolchain.
 
 Before building any examples, you will need to first install the toolchain. To do this, follow the 
-steps in `Getting Symbiflow <getting-symbiflow.html>`_. After you have downloaded the toolchain, 
+steps in `Getting F4PGA <getting-f4pga.html>`_. After you have downloaded the toolchain, 
 follow the steps in `Building Examples <building-examples.html>`_ by seting the installation 
 directory to match what you set it to earlier, assigning the path and source for 
 your conda environment, and activating your env.
@@ -13,7 +13,7 @@ your conda environment, and activating your env.
 Preparing Your Design 
 ----------------------
 
-Building a design in Symbiflow requires three parts: the HDL files for your design, a constraints
+Building a design in F4PGA requires three parts: the HDL files for your design, a constraints
 file, and a Makefile. For simplicity, all three of these design files should be moved to a single
 directory. The location of the directory does not mater as long as the three design elements are all 
 within it.
@@ -21,7 +21,7 @@ within it.
 HDL Files
 ++++++++++
 
-Symbiflow provides full support for Verilog. Some support for SystemVerilog HDL code is also 
+F4PGA provides full support for Verilog. Some support for SystemVerilog HDL code is also 
 provided, although more complicated designs written in SystemVerilog may not build properly under 
 Yosys. Use whichever method you prefer, and add your design files to the directory of choice. 
 If you are using the provided Makefiles to build your design, the top level module in your HDL 
@@ -33,7 +33,7 @@ your own makefiles or commands, you can specify your top level module name using
 Constraint File
 ++++++++++++++++
 
-The Symbiflow toolchain supports both .XDC and .PCF+.SDC formats for constraints. 
+The F4PGA toolchain supports both .XDC and .PCF+.SDC formats for constraints. 
 You can use XDC to define IOPAD, IOSETTINGS, and clock constraints. SDCs can be used to 
 define clock constraints and PCFs can be used to define IOPAD constraints only. Use whichever 
 method you prefer and add your constraint file(s) to your design directory.

docs/project-f.rst

@@ -1,25 +1,25 @@
-Running Project F designs in Symbiflow
+Running Project F designs in F4PGA
-======================================
+==================================
 
 .. warning::
-   Symbiflow does not currently support the MMCME2_BASE primitive--a key commponent in Project F's 
+   F4PGA does not currently support the MMCME2_BASE primitive--a key commponent in Project F's 
    clock_gen_480p module and all designs involving video output. 
    As such, all of the designs in project F that require a display (all designs in FPGA graphics) will
    fail when run through the toolchain. Only the designs in 
    `Hello Arty <https://github.com/projf/projf-explore/tree/master/hello/hello-arty>`_ are currently 
    officially supported. To track the progress of the MMCME2_BASE see issue 
-   `#153 <https://github.com/SymbiFlow/symbiflow-examples/issues/153>`_ in symbiflow examples and 
+   `#153 <https://github.com/chipsalliance/f4pga-examples/issues/153>`_ in f4pga examples and 
-   issue `#2246 <https://github.com/SymbiFlow/symbiflow-arch-defs/issues/2246>`_ in arch-defs.
+   issue `#2246 <https://github.com/f4pga/f4pga-arch-defs/issues/2246>`_ in arch-defs.
    One user was able to successfully run most of the display designs in project F by replacing the
    MMCM in clock_gen_480p.sv with a PLLE2_ADV. For details on that see issue 
-   `#180 <https://github.com/SymbiFlow/symbiflow-examples/issues/180>`_ in symbiflow-examples.
+   `#180 <https://github.com/chipsalliance/f4pga-examples/issues/180>`_ in f4pga-examples.
 
 Project F is an amazing repository containing many high quality FPGA example designs that show
 some of the more impressive things you can do with an FPGA. You can find detailed documentation on
 the designs and how they work on `the developers blog <https://projectf.io/sitemap/>`_. 
 
-To build the Designs in Project F using symbiflow, first ensure that you have installed the Project F
+To build the Designs in Project F using F4PGA, first ensure that you have installed the Project F
-submodule locally. Enter into the ``symbiflow-examples`` directory and run:
+submodule locally. Enter into the ``f4pga-examples`` directory and run:
 
 .. code-block:: bash
    :name: import-projectf
@@ -39,7 +39,7 @@ For example, to build the first design in project F's hello ary designs:
    TARGET="arty_35" make -C projf-makefiles/hello/hello-arty/A
  
 To download the bitstream to the board run ``make download``. For example to download the first design from 
-hello arty, run the following in symbiflows root directory:
+hello arty, run the following in F4PGA root directory:
 
 .. code-block:: bash
 

docs/understanding-commands.rst

@@ -2,13 +2,13 @@ Understanding Toolchain Commands
 =================================
 
 This section provides valuable information on how each of the commands used to compile and build 
-designs in Symbiflow work. It is especially helpful for debugging or for using methods 
+designs in F4PGA work. It is especially helpful for debugging or for using methods 
 other than a makefile to build your designs, such as a bash or python script. 
 
 The following describes the commands for running each of the steps for a full design flow 
 (synthesis, place and route, and generate bitstream) as well as giving a description of the most
 common flags for those commands. If you would like a more detailed break down of how the design 
-flow for Symbiflow works take a look at the 
+flow for F4PGA works take a look at the 
 `FPGA Design Flow page <https://symbiflow.readthedocs.io/en/latest/toolchain-desc/design-flow.html>`_.
 
 .. note::
@@ -53,8 +53,8 @@ family and uses the xc7a35tcpg236-1 chip.
 
 Synthesis is carried out using the Yosys open source tool. ``symbiflow_synth`` generates 
 an .eblif file, a few verilog netlists that describe the gate level design for your project, and a log
-file. For more information on Yosys and its relation to Symbiflow go to the
+file. For more information on Yosys and its relation to F4PGA go to the
-`Symbiflow-Yosys page <https://symbiflow.readthedocs.io/en/latest/toolchain-desc/yosys.html>`_.
+`F4PGA-Yosys page <https://symbiflow.readthedocs.io/en/latest/toolchain-desc/yosys.html>`_.
 
 .. note::
     The build files generated by the toolchain (for example .eblif from synthesis, .net from 
@@ -69,7 +69,7 @@ Place and Route
 
 The three steps for implementing a design are internally handled by the open source VPR 
 (Versatile Place and Route) tool. For more information go to 
-`the Symbiflow VPR page <https://symbiflow.readthedocs.io/en/latest/vtr-verilog-to-routing/doc/src/vpr/index.html>`_.
+`the F4PGA VPR page <https://symbiflow.readthedocs.io/en/latest/vtr-verilog-to-routing/doc/src/vpr/index.html>`_.
 
 Pack
 +++++

projf-makefiles/hello/hello-arty/A/README.rst

@@ -2,7 +2,7 @@ Part 1 Design A
 ===============
 
 This design allows you to turn the first led on the arty board on and off by toggling switch 0. 
-To build this design run the following command in the main symbiflow directory:
+To build this design run the following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-a

projf-makefiles/hello/hello-arty/B/README.rst

@@ -2,7 +2,7 @@ Part 1 Design B
 ===============
 
 This design allows you to turn four LEDs on and off with switches 0 and 1. Control LEDs 0 and 1 with switch 0 and LEDs
-2 and 3 with switch 1. To build this design run the following in the root symbiflow-example directory:
+2 and 3 with switch 1. To build this design run the following in the root f4pga-example directory:
 
 .. code-block:: bash
    :name: hello-arty-b

projf-makefiles/hello/hello-arty/C/README.rst

@@ -3,7 +3,7 @@ Part 1 Design C
 
 This design has the same functionality in hardware as part C but demonstrates
 the use of conditional operators in System Verilog. To build this design run the 
-following command in the main symbiflow directory:
+following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-c

projf-makefiles/hello/hello-arty/D/README.rst

@@ -2,7 +2,7 @@ Part 1 Design D
 ===============
 
 This design is the fourth design from Part 1 of Hello Arty. To build this design run the following 
-command in the main symbiflow directory:
+command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-d

projf-makefiles/hello/hello-arty/E/README.rst

@@ -2,7 +2,7 @@ Part 2 Design E
 ===============
 
 This is the first design in Hello Arty part 2. This design blinks LED 0. 
-To build this design run the following command in the main symbiflow directory:
+To build this design run the following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-e

projf-makefiles/hello/hello-arty/F/README.rst

@@ -2,7 +2,7 @@ Part 2 Design F
 ===============
 
 This design blinks LEDs 0-3 at different frequencies. 
-To build this design run the following command in the main symbiflow directory:
+To build this design run the following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-f

projf-makefiles/hello/hello-arty/G/README.rst

@@ -2,7 +2,7 @@ Part 2 Design G
 ===============
 
 This design strobes leds 0-3. 
-To build this design run the following command in the main symbiflow directory:
+To build this design run the following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-g

projf-makefiles/hello/hello-arty/H/README.rst

@@ -2,7 +2,7 @@ Part 2 Design H
 ===============
 
 This design controls the brightness of LEDs 0-3 by using a PWM. 
-To build this design run the following command in the main symbiflow directory:
+To build this design run the following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-h

projf-makefiles/hello/hello-arty/I/README.rst

@@ -2,7 +2,7 @@ Part 2 Design I
 ===============
 
 This design allows you to control the brightness of each LED on the arty board using a PWM with different duty cycles. 
-To build this design run the following command in the main symbiflow directory:
+To build this design run the following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-i

projf-makefiles/hello/hello-arty/J/README.rst

@@ -2,7 +2,7 @@ Part 2 Design J
 ===============
 
 This design controls the color of each of the 4 RGB LEDs on the arty using a PWM. 
-To build this design run the following command in the main symbiflow directory:
+To build this design run the following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-j

projf-makefiles/hello/hello-arty/K/README.rst

@@ -2,7 +2,7 @@ Part 3 Design K
 ===============
 
 This is the first part of the traffic light example from project F. 
-To build this design run the following command in the main symbiflow directory:
+To build this design run the following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-k

projf-makefiles/hello/hello-arty/L/README.rst

@@ -2,7 +2,7 @@ Part 3 Design L
 ===============
 
 This is the second part of the traffic light example from project F. 
-To build this design run the following command in the main symbiflow directory:
+To build this design run the following command in the main f4pga directory:
 
 .. code-block:: bash
    :name: hello-arty-l

scripts/make/conda.mk

@@ -25,7 +25,7 @@ DOWNLOADS_DIR     := $(ENV_DIR)/downloads
 CONDA_PYTHON      := $(CONDA_DIR)/bin/python
 CONDA_PKGS_DIR    := $(DOWNLOADS_DIR)/conda-pkgs
 CONDA_PKGS_DEP    := $(CONDA_PKGS_DIR)/urls.txt
-CONDA_ENV_NAME    := symbiflow-examples
+CONDA_ENV_NAME    := f4pga-examples
 CONDA_ENV_PYTHON  := $(CONDA_DIR)/envs/$(CONDA_ENV_NAME)/bin/python
 IN_CONDA_ENV_BASE := source $(CONDA_DIR)/bin/activate &&
 IN_CONDA_ENV      := $(IN_CONDA_ENV_BASE) conda activate $(CONDA_ENV_NAME) &&

xc7/README.rst

@@ -1,5 +1,5 @@
-SymbiFlow Toolchain Examples for Xilinx 7 Series
+F4PGA Toolchain Examples for Xilinx 7 Series
-================================================
+============================================
 
 #. ``counter`` - simple 4-bit counter driving LEDs. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__, the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__, and the `Zybo Z7 board <https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/>`__
 #. ``picosoc`` - `picorv32 <https://github.com/cliffordwolf/picorv32>`__ based SoC. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__.
@@ -10,4 +10,4 @@ The Linux images for the ``linux_litex`` example can be built following the `lin
 The ``linux_litex`` example is already provided with working Linux images.
 
 The detailed description about building the examples is available in the
-`project documentation <https://symbiflow-examples.readthedocs.io/en/latest/building-examples.html#xilinx-7-series>`__.
+`project documentation <https://f4pga-examples.readthedocs.io/en/latest/building-examples.html#xilinx-7-series>`__.

xc7/counter_test/README.rst

@@ -58,7 +58,7 @@ The result should be as follows:
    :align: center
    :width: 50%
 
-For **Zybo**, please follow the `guide on how to load a bitstream from U-boot <https://symbiflow-examples.readthedocs.io/en/latest/running-examples.html#load-bitstream-from-u-boot>`_.
+For **Zybo**, please follow the `guide on how to load a bitstream from U-boot <https://f4pga-examples.readthedocs.io/en/latest/running-examples.html#load-bitstream-from-u-boot>`_.
 
 
 Once the bitstream is loaded, the result should be as follows:

xc7/timer/README.rst

@@ -2,7 +2,7 @@ Timer
 ~~~~~~
 
 This example is built specifically for the basys3 and demonstrates a greater variety of I/O 
-then previous designs. It also demonstrates symbiflow's support for code written in System Verilog 
+then previous designs. It also demonstrates F4PGA's support for code written in System Verilog 
 as well as its support of dictionaries in XDCs. To build this example run the following commands:
 
 .. code-block:: bash
@@ -28,4 +28,4 @@ Press the center button to reset the counter. The following gives a visual examp
 
 .. image:: ../../docs/images/timer.gif
    :align: center
-   :width: 50%
+   :width: 50%