Raname to F4PGA
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
Karol Gugala
parent
3dfe0f7581
commit
f0c5adcb75
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@ -18,7 +18,7 @@
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from sys import argv as sys_argv
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isFork = len(sys_argv)>1 and sys_argv[1] != 'SymbiFlow/symbiflow-examples'
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isFork = len(sys_argv)>1 and sys_argv[1] != 'chipsalliance/f4pga-examples'
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runs_on = (
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'ubuntu-latest'
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@ -25,7 +25,7 @@ source ${CURRENT_DIR}/common.sh
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function help() {
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echo
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echo "Install the SymbiFlow toolchain as described in the sphinx documentation"
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echo "Install the F4PGA toolchain as described in the sphinx documentation"
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echo
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echo "Syntax: $0 fpga_family os"
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echo "Arguments:"
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@ -45,4 +45,4 @@ fi
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fpga_family=$1
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os=$2
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tuttest_exec docs/getting-symbiflow.rst:install-reqs-$os,wget-conda,conda-install-dir,fpga-fam-$fpga_family,conda-setup,download-arch-def-$fpga_family
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tuttest_exec docs/getting-f4pga.rst:install-reqs-$os,wget-conda,conda-install-dir,fpga-fam-$fpga_family,conda-setup,download-arch-def-$fpga_family
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@ -69,7 +69,7 @@ jobs:
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wget https://github.com/antmicro/tuttest/releases/download/v0.2-beta/tuttest -O /usr/bin/tuttest
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chmod a+rx /usr/bin/tuttest
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- name: Install SymbiFlow toolchain
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- name: Install F4PGA toolchain
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run: bash .github/scripts/install-toolchain.sh ${{matrix.fpga-fam}} ${{matrix.os}}
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- name: Build examples
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@ -77,7 +77,7 @@ jobs:
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- uses: actions/upload-artifact@v2
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with:
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name: symbiflow-examples-bitstreams
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name: f4pga-examples-bitstreams
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path: |
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**/*.bit
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**/plot_*.svg
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4
Makefile
4
Makefile
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@ -22,7 +22,7 @@ VERILOG_SRCS=$(shell find . -name "*.v" -not -path "./env/*" -not -path "./symbi
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env:
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conda env create -f environment.yml
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conda activate symbiflow-examples
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conda activate f4pga-examples
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format:
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yapf -i ${PYTHON_SRCS}
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@ -36,6 +36,6 @@ format:
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clean::
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rm -rf env/
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conda deactivate
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conda env remove -n symbiflow-examples
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conda env remove -n f4pga-examples
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.PHONY: env format clean
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26
README.rst
26
README.rst
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@ -1,19 +1,19 @@
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SymbiFlow examples
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==================
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F4PGA examples
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==============
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Please refer to the `project documentation <https://symbiflow-examples.readthedocs.io>`_
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for a proper guide on how to run these examples as well as instructions on how to build and
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compile your own HDL designs using the symbiflow toolchain.
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Please refer to the `project documentation <https://f4pga-examples.readthedocs.io>`_
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for a proper guide on how to run these examples as well as instructions on how to build and
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compile your own HDL designs using the F4PGA toolchain.
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.. image:: https://github.com/symbiflow/symbiflow-examples/workflows/doc-test/badge.svg?branch=master
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:target: https://github.com/SymbiFlow/symbiflow-examples/actions
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.. image:: https://github.com/chipsalliance/f4pga-examples/workflows/doc-test/badge.svg?branch=master
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:target: https://github.com/chipsalliance/f4pga-examples/actions
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.. image:: https://readthedocs.org/projects/symbiflow-examples/badge/?version=latest
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:target: https://symbiflow-examples.readthedocs.io/en/latest/?badge=latest
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.. image:: https://readthedocs.org/projects/f4pga-examples/badge/?version=latest
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:target: https://f4pga-examples.readthedocs.io/en/latest/?badge=latest
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:alt: Documentation Status
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This repository provides example FPGA designs that can be built using the
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SymbiFlow open source toolchain. These examples target the Xilinx 7-Series and
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F4PGA open source toolchain. These examples target the Xilinx 7-Series and
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the QuickLogic EOS S3 devices.
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The repository includes:
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@ -23,11 +23,11 @@ The repository includes:
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* Verilog code
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* Pin constraints files
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* Timing constraints files
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* Makefiles for running the SymbiFlow toolchain
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* `docs/ <./docs>`_ - Guide on how to get started with SymbiFlow and build provided examples
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* Makefiles for running the F4PGA toolchain
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* `docs/ <./docs>`_ - Guide on how to get started with F4PGA and build provided examples
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* `.github/ <./.github>`_ - Directory with CI configuration and scripts
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The examples provided by this repository are automatically built by extracting
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The examples provided by this repository are automatically built by extracting
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necessary code snippets with `tuttest <https://github.com/antmicro/tuttest>`_.
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Building those docs
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@ -78,7 +78,7 @@ download: ${BOARD_BUILDDIR}/${TOP}.bit
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elif [ $(TARGET)='basys3' ]; then \
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openocd -f ~/opt/symbiflow/xc7/conda/envs/xc7/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 ${BOARD_BUILDDIR}/${TOP}.bit; exit"; \
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else \
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echo "The commands needed to download the bitstreams to the board type specified are not currently supported by the symbiflow makefiles. \
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echo "The commands needed to download the bitstreams to the board type specified are not currently supported by the F4PGA makefiles. \
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Please see documentation for more information."; \
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fi
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@ -1,4 +1,3 @@
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Building example designs
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========================
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@ -8,7 +7,7 @@ set it to earlier, for example:
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.. code-block:: bash
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:name: export-install-dir
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export INSTALL_DIR=~/opt/symbiflow
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export INSTALL_DIR=~/opt/f4pga
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Select your FPGA family:
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@ -212,7 +212,7 @@ def get_blocks(text):
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def fill_context(text):
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"""
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Creates a jinja context dictionary for a SymbiFlow Toolchain usage example.
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Creates a jinja context dictionary for a F4PGA Toolchain usage example.
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The dictionary contains all the important information from the example's README.
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Args:
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10
docs/conf.py
10
docs/conf.py
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@ -1,7 +1,7 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2020 The SymbiFlow Authors.
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# Copyright (C) 2020-2022 F4PGA Authors.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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@ -36,9 +36,9 @@ sys.path.insert(0, os.path.abspath('.'))
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# -- Project information -----------------------------------------------------
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project = u'SymbiFlow examples'
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authors = u'SymbiFlow'
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copyright = authors + u', 2020'
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project = u'F4PGA examples'
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authors = u'F4PGA Authors'
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copyright = authors + u', 2020 - 2022'
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# -- General configuration ---------------------------------------------------
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@ -69,7 +69,7 @@ html_show_sourcelink = True
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html_theme = 'sphinx_symbiflow_theme'
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html_theme_options = {
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'github_url' : 'https://github.com/SymbiFlow/symbiflow-examples',
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'github_url' : 'https://github.com/chipsalliance/F4PGA-examples',
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'globaltoc_collapse': True
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}
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@ -5,14 +5,14 @@ A powerful tool in creating your own designs is understanding how to generate yo
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compile projects. This tutorial walks you through how to do that.
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If you would like to use methods other than a Makefile to build and compile your designs
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(such as python or bash scripts) or if you would like to learn more about the various Symbiflow
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(such as python or bash scripts) or if you would like to learn more about the various F4PGA
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commands used by the common Makefile to build and compile designs take a look at the
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`Understanding Toolchain Commands <understanding-commands.html>`_ page.
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Example
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-------
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By including Symbiflow's provided common Makefile in your designs, running the commands necessary for building
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By including F4PGA's provided common Makefile in your designs, running the commands necessary for building
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your personal projects is incredibly simple. All you have to do is run a few simple commands and set
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a few variables.
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@ -32,7 +32,7 @@ Create a makefile for your project by running ``touch Makefile``, and add the fo
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PCF := ${current_dir}/<name of your xdc file if applicable>
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SDC := ${current_dir}/<name of your sdc file if applicable>
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include <path to symbiflow-examples root directory>/common/common.mk
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include <path to f4pga-examples root directory>/common/common.mk
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Lets talk briefly about each of the commands in the above makefile
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@ -72,7 +72,7 @@ above to a ``.sv``.
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.. note::
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As of this writing, symbiflow only offers full support for Verilog by default.
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As of this writing, F4PGAw only offers full support for Verilog by default.
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SystemVerilog can also be run through the toolchain but more complicated
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designs may not be fully supported.
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@ -109,9 +109,9 @@ your design. The general syntax depends on whether you are using XDC files or a
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A Note on the example designs use of ifeq/else ifeq blocks
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-------------------------------------------------------------
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If you look at the Makefiles from the example designs within Symbiflow
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If you look at the Makefiles from the example designs within F4PGA
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(i.e. counter test, Picosoc, etc.), you will find an ifeq else ifeq block. The following snippet
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is from lines 9-39 of `the Makefile from counter test <https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/counter_test/Makefile>`_:
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is from lines 9-39 of `the Makefile from counter test <https://github.com/chipsalliance/f4pga-examples/blob/master/xc7/counter_test/Makefile>`_:
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.. code-block:: bash
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@ -1,7 +1,7 @@
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Getting SymbiFlow
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=================
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Getting F4PGA
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=============
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This section describes how to install SymbiFlow and set up a fully working
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This section describes how to install F4PGA and set up a fully working
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environment to later build example designs.
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Prerequisites
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@ -43,18 +43,18 @@ To be able to follow through this tutorial, install the following software:
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dnf install -y findutils git wget which xz
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Next, clone the SymbiFlow examples repository and enter it:
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Next, clone the F4PGA examples repository and enter it:
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.. code-block:: bash
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:name: get-symbiflow
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:name: get-f4pga
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git clone https://github.com/SymbiFlow/symbiflow-examples
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cd symbiflow-examples
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git clone https://github.com/F4PGA/f4pga-examples
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cd f4pga-examples
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Toolchain installation
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----------------------
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Now we are able to install the SymbiFlow toolchain. This procedure is divided
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Now we are able to install the F4PGA toolchain. This procedure is divided
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into three steps:
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- installing the Conda package manager,
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@ -64,7 +64,7 @@ into three steps:
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Conda
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~~~~~
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Download Conda installer script into the symbiflow-examples directory:
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Download Conda installer script into the f4pga-examples directory:
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.. code-block:: bash
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:name: wget-conda
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@ -75,14 +75,14 @@ Choose the install directory
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The install directory can either be in your home directory
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such as ``~/opt/symbiflow`` or in a system directory such as ``/opt/symbiflow``.
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such as ``~/opt/f4pga`` or in a system directory such as ``/opt/f4pga``.
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If you choose a system directory, you will need root permission to perform the installation,
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and so you will need to add some ``sudo`` commands to the instructions below.
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.. code-block:: bash
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:name: conda-install-dir
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export INSTALL_DIR=~/opt/symbiflow
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export INSTALL_DIR=~/opt/f4pga
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Toolchain
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~~~~~~~~~
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@ -1,8 +1,8 @@
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Welcome to SymbiFlow examples!
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==============================
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Welcome to F4PGA examples!
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==========================
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This guide explains how to get started with SymbiFlow and build example designs
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from the `SymbiFlow Examples <https://github.com/symbiflow/symbiflow-examples>`_
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This guide explains how to get started with F4PGA and build example designs
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from the `F4PGA Examples <https://github.com/chipsalliance/f4pga-examples>`_
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GitHub repository. It currently focuses on the following FPGA families:
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- Artix-7 from Xilinx,
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@ -10,18 +10,18 @@ GitHub repository. It currently focuses on the following FPGA families:
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Follow this guide to:
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- :doc:`install SymbiFlow <getting-symbiflow>` and all of its dependencies,
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- :doc:`install F4PGA <getting-symbiflow>` and all of its dependencies,
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- :doc:`build <building-examples>` and :doc:`upload <running-examples>`
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example designs onto the devboard of your choice.
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- compile and run :doc:`your own designs<personal-designs>` using the Symbiflow toolchain.
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- compile and run :doc:`your own designs<personal-designs>` using the F4PGA toolchain.
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- :doc:`customize the Makefile<customizing-makefiles>` for your own designs.
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- gain valuable information about `Understanding Toolchain Commands in Symbiflow <understanding-commands.html>`_
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- gain valuable information about `Understanding Toolchain Commands in F4PGA <understanding-commands.html>`_
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About SymbiFlow
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---------------
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About F4PGA
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-----------
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SymbiFlow is a fully open source toolchain for the development of FPGAs,
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F4PGA is a fully open source toolchain for the development of FPGAs,
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currently targeting chips from multiple vendors, e.g.:
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- Xilinx 7-Series
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@ -33,7 +33,7 @@ currently targeting chips from multiple vendors, e.g.:
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:maxdepth: 2
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:caption: Sections
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getting-symbiflow
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getting-f4pga
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building-examples
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running-examples
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personal-designs
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|
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@ -2,10 +2,10 @@ Building Custom Designs
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========================
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This section describes how to compile and download your own designs to an FPGA using only
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the Symbiflow toolchain.
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the F4PGA toolchain.
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Before building any examples, you will need to first install the toolchain. To do this, follow the
|
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steps in `Getting Symbiflow <getting-symbiflow.html>`_. After you have downloaded the toolchain,
|
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steps in `Getting F4PGA <getting-f4pga.html>`_. After you have downloaded the toolchain,
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follow the steps in `Building Examples <building-examples.html>`_ by seting the installation
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directory to match what you set it to earlier, assigning the path and source for
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your conda environment, and activating your env.
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@ -13,7 +13,7 @@ your conda environment, and activating your env.
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Preparing Your Design
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----------------------
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Building a design in Symbiflow requires three parts: the HDL files for your design, a constraints
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Building a design in F4PGA requires three parts: the HDL files for your design, a constraints
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file, and a Makefile. For simplicity, all three of these design files should be moved to a single
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directory. The location of the directory does not mater as long as the three design elements are all
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within it.
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@ -21,7 +21,7 @@ within it.
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HDL Files
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||||
++++++++++
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||||
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Symbiflow provides full support for Verilog. Some support for SystemVerilog HDL code is also
|
||||
F4PGA provides full support for Verilog. Some support for SystemVerilog HDL code is also
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||||
provided, although more complicated designs written in SystemVerilog may not build properly under
|
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Yosys. Use whichever method you prefer, and add your design files to the directory of choice.
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If you are using the provided Makefiles to build your design, the top level module in your HDL
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@ -33,7 +33,7 @@ your own makefiles or commands, you can specify your top level module name using
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Constraint File
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++++++++++++++++
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||||
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||||
The Symbiflow toolchain supports both .XDC and .PCF+.SDC formats for constraints.
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The F4PGA toolchain supports both .XDC and .PCF+.SDC formats for constraints.
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You can use XDC to define IOPAD, IOSETTINGS, and clock constraints. SDCs can be used to
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define clock constraints and PCFs can be used to define IOPAD constraints only. Use whichever
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||||
method you prefer and add your constraint file(s) to your design directory.
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|
|
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|
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@ -1,25 +1,25 @@
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Running Project F designs in Symbiflow
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======================================
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Running Project F designs in F4PGA
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||||
==================================
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.. warning::
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Symbiflow does not currently support the MMCME2_BASE primitive--a key commponent in Project F's
|
||||
F4PGA does not currently support the MMCME2_BASE primitive--a key commponent in Project F's
|
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clock_gen_480p module and all designs involving video output.
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As such, all of the designs in project F that require a display (all designs in FPGA graphics) will
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||||
fail when run through the toolchain. Only the designs in
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||||
`Hello Arty <https://github.com/projf/projf-explore/tree/master/hello/hello-arty>`_ are currently
|
||||
officially supported. To track the progress of the MMCME2_BASE see issue
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`#153 <https://github.com/SymbiFlow/symbiflow-examples/issues/153>`_ in symbiflow examples and
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||||
issue `#2246 <https://github.com/SymbiFlow/symbiflow-arch-defs/issues/2246>`_ in arch-defs.
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`#153 <https://github.com/chipsalliance/f4pga-examples/issues/153>`_ in f4pga examples and
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||||
issue `#2246 <https://github.com/f4pga/f4pga-arch-defs/issues/2246>`_ in arch-defs.
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||||
One user was able to successfully run most of the display designs in project F by replacing the
|
||||
MMCM in clock_gen_480p.sv with a PLLE2_ADV. For details on that see issue
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||||
`#180 <https://github.com/SymbiFlow/symbiflow-examples/issues/180>`_ in symbiflow-examples.
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`#180 <https://github.com/chipsalliance/f4pga-examples/issues/180>`_ in f4pga-examples.
|
||||
|
||||
Project F is an amazing repository containing many high quality FPGA example designs that show
|
||||
some of the more impressive things you can do with an FPGA. You can find detailed documentation on
|
||||
the designs and how they work on `the developers blog <https://projectf.io/sitemap/>`_.
|
||||
|
||||
To build the Designs in Project F using symbiflow, first ensure that you have installed the Project F
|
||||
submodule locally. Enter into the ``symbiflow-examples`` directory and run:
|
||||
To build the Designs in Project F using F4PGA, first ensure that you have installed the Project F
|
||||
submodule locally. Enter into the ``f4pga-examples`` directory and run:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: import-projectf
|
||||
|
|
@ -39,7 +39,7 @@ For example, to build the first design in project F's hello ary designs:
|
|||
TARGET="arty_35" make -C projf-makefiles/hello/hello-arty/A
|
||||
|
||||
To download the bitstream to the board run ``make download``. For example to download the first design from
|
||||
hello arty, run the following in symbiflows root directory:
|
||||
hello arty, run the following in F4PGA root directory:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@ Understanding Toolchain Commands
|
|||
=================================
|
||||
|
||||
This section provides valuable information on how each of the commands used to compile and build
|
||||
designs in Symbiflow work. It is especially helpful for debugging or for using methods
|
||||
designs in F4PGA work. It is especially helpful for debugging or for using methods
|
||||
other than a makefile to build your designs, such as a bash or python script.
|
||||
|
||||
The following describes the commands for running each of the steps for a full design flow
|
||||
(synthesis, place and route, and generate bitstream) as well as giving a description of the most
|
||||
common flags for those commands. If you would like a more detailed break down of how the design
|
||||
flow for Symbiflow works take a look at the
|
||||
flow for F4PGA works take a look at the
|
||||
`FPGA Design Flow page <https://symbiflow.readthedocs.io/en/latest/toolchain-desc/design-flow.html>`_.
|
||||
|
||||
.. note::
|
||||
|
|
@ -53,8 +53,8 @@ family and uses the xc7a35tcpg236-1 chip.
|
|||
|
||||
Synthesis is carried out using the Yosys open source tool. ``symbiflow_synth`` generates
|
||||
an .eblif file, a few verilog netlists that describe the gate level design for your project, and a log
|
||||
file. For more information on Yosys and its relation to Symbiflow go to the
|
||||
`Symbiflow-Yosys page <https://symbiflow.readthedocs.io/en/latest/toolchain-desc/yosys.html>`_.
|
||||
file. For more information on Yosys and its relation to F4PGA go to the
|
||||
`F4PGA-Yosys page <https://symbiflow.readthedocs.io/en/latest/toolchain-desc/yosys.html>`_.
|
||||
|
||||
.. note::
|
||||
The build files generated by the toolchain (for example .eblif from synthesis, .net from
|
||||
|
|
@ -69,7 +69,7 @@ Place and Route
|
|||
|
||||
The three steps for implementing a design are internally handled by the open source VPR
|
||||
(Versatile Place and Route) tool. For more information go to
|
||||
`the Symbiflow VPR page <https://symbiflow.readthedocs.io/en/latest/vtr-verilog-to-routing/doc/src/vpr/index.html>`_.
|
||||
`the F4PGA VPR page <https://symbiflow.readthedocs.io/en/latest/vtr-verilog-to-routing/doc/src/vpr/index.html>`_.
|
||||
|
||||
Pack
|
||||
+++++
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 1 Design A
|
|||
===============
|
||||
|
||||
This design allows you to turn the first led on the arty board on and off by toggling switch 0.
|
||||
To build this design run the following command in the main symbiflow directory:
|
||||
To build this design run the following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-a
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 1 Design B
|
|||
===============
|
||||
|
||||
This design allows you to turn four LEDs on and off with switches 0 and 1. Control LEDs 0 and 1 with switch 0 and LEDs
|
||||
2 and 3 with switch 1. To build this design run the following in the root symbiflow-example directory:
|
||||
2 and 3 with switch 1. To build this design run the following in the root f4pga-example directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-b
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ Part 1 Design C
|
|||
|
||||
This design has the same functionality in hardware as part C but demonstrates
|
||||
the use of conditional operators in System Verilog. To build this design run the
|
||||
following command in the main symbiflow directory:
|
||||
following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-c
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 1 Design D
|
|||
===============
|
||||
|
||||
This design is the fourth design from Part 1 of Hello Arty. To build this design run the following
|
||||
command in the main symbiflow directory:
|
||||
command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-d
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 2 Design E
|
|||
===============
|
||||
|
||||
This is the first design in Hello Arty part 2. This design blinks LED 0.
|
||||
To build this design run the following command in the main symbiflow directory:
|
||||
To build this design run the following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-e
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 2 Design F
|
|||
===============
|
||||
|
||||
This design blinks LEDs 0-3 at different frequencies.
|
||||
To build this design run the following command in the main symbiflow directory:
|
||||
To build this design run the following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-f
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 2 Design G
|
|||
===============
|
||||
|
||||
This design strobes leds 0-3.
|
||||
To build this design run the following command in the main symbiflow directory:
|
||||
To build this design run the following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-g
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 2 Design H
|
|||
===============
|
||||
|
||||
This design controls the brightness of LEDs 0-3 by using a PWM.
|
||||
To build this design run the following command in the main symbiflow directory:
|
||||
To build this design run the following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-h
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 2 Design I
|
|||
===============
|
||||
|
||||
This design allows you to control the brightness of each LED on the arty board using a PWM with different duty cycles.
|
||||
To build this design run the following command in the main symbiflow directory:
|
||||
To build this design run the following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-i
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 2 Design J
|
|||
===============
|
||||
|
||||
This design controls the color of each of the 4 RGB LEDs on the arty using a PWM.
|
||||
To build this design run the following command in the main symbiflow directory:
|
||||
To build this design run the following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-j
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 3 Design K
|
|||
===============
|
||||
|
||||
This is the first part of the traffic light example from project F.
|
||||
To build this design run the following command in the main symbiflow directory:
|
||||
To build this design run the following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-k
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Part 3 Design L
|
|||
===============
|
||||
|
||||
This is the second part of the traffic light example from project F.
|
||||
To build this design run the following command in the main symbiflow directory:
|
||||
To build this design run the following command in the main f4pga directory:
|
||||
|
||||
.. code-block:: bash
|
||||
:name: hello-arty-l
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ DOWNLOADS_DIR := $(ENV_DIR)/downloads
|
|||
CONDA_PYTHON := $(CONDA_DIR)/bin/python
|
||||
CONDA_PKGS_DIR := $(DOWNLOADS_DIR)/conda-pkgs
|
||||
CONDA_PKGS_DEP := $(CONDA_PKGS_DIR)/urls.txt
|
||||
CONDA_ENV_NAME := symbiflow-examples
|
||||
CONDA_ENV_NAME := f4pga-examples
|
||||
CONDA_ENV_PYTHON := $(CONDA_DIR)/envs/$(CONDA_ENV_NAME)/bin/python
|
||||
IN_CONDA_ENV_BASE := source $(CONDA_DIR)/bin/activate &&
|
||||
IN_CONDA_ENV := $(IN_CONDA_ENV_BASE) conda activate $(CONDA_ENV_NAME) &&
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
SymbiFlow Toolchain Examples for Xilinx 7 Series
|
||||
================================================
|
||||
F4PGA Toolchain Examples for Xilinx 7 Series
|
||||
============================================
|
||||
|
||||
#. ``counter`` - simple 4-bit counter driving LEDs. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__, the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__, and the `Zybo Z7 board <https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/>`__
|
||||
#. ``picosoc`` - `picorv32 <https://github.com/cliffordwolf/picorv32>`__ based SoC. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__.
|
||||
|
|
@ -10,4 +10,4 @@ The Linux images for the ``linux_litex`` example can be built following the `lin
|
|||
The ``linux_litex`` example is already provided with working Linux images.
|
||||
|
||||
The detailed description about building the examples is available in the
|
||||
`project documentation <https://symbiflow-examples.readthedocs.io/en/latest/building-examples.html#xilinx-7-series>`__.
|
||||
`project documentation <https://f4pga-examples.readthedocs.io/en/latest/building-examples.html#xilinx-7-series>`__.
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ The result should be as follows:
|
|||
:align: center
|
||||
:width: 50%
|
||||
|
||||
For **Zybo**, please follow the `guide on how to load a bitstream from U-boot <https://symbiflow-examples.readthedocs.io/en/latest/running-examples.html#load-bitstream-from-u-boot>`_.
|
||||
For **Zybo**, please follow the `guide on how to load a bitstream from U-boot <https://f4pga-examples.readthedocs.io/en/latest/running-examples.html#load-bitstream-from-u-boot>`_.
|
||||
|
||||
|
||||
Once the bitstream is loaded, the result should be as follows:
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Timer
|
|||
~~~~~~
|
||||
|
||||
This example is built specifically for the basys3 and demonstrates a greater variety of I/O
|
||||
then previous designs. It also demonstrates symbiflow's support for code written in System Verilog
|
||||
then previous designs. It also demonstrates F4PGA's support for code written in System Verilog
|
||||
as well as its support of dictionaries in XDCs. To build this example run the following commands:
|
||||
|
||||
.. code-block:: bash
|
||||
|
|
@ -28,4 +28,4 @@ Press the center button to reset the counter. The following gives a visual examp
|
|||
|
||||
.. image:: ../../docs/images/timer.gif
|
||||
:align: center
|
||||
:width: 50%
|
||||
:width: 50%
|
||||
|
|
|
|||
Loading…
Reference in New Issue