diff --git a/.github/scripts/build-examples.sh b/.github/scripts/build-examples.sh
index 0a21277..49cfec4 100755
--- a/.github/scripts/build-examples.sh
+++ b/.github/scripts/build-examples.sh
@@ -55,6 +55,7 @@ fi
 # activate conda and enter example dir
 
 snippets="docs/building-examples.rst:export-install-dir,fpga-fam-$fpga_family,conda-prep-env-$fpga_family,conda-act-env,enter-dir-$fpga_family"
+additionalDesigns="docs/building-examples.rst:export-install-dir,fpga-fam-$fpga_family,conda-prep-env-$fpga_family,conda-act-env,enter-dir-$fpga_family,additional_examples"
 
 # Xilinx 7-Series examples
 if [ "$fpga_family" = "xc7" ]; then
diff --git a/docs/master_makefile/Makefile b/docs/master_makefile/Makefile
index cd1d444..174b0ae 100644
--- a/docs/master_makefile/Makefile
+++ b/docs/master_makefile/Makefile
@@ -62,4 +62,5 @@ ${BOARD_BUILDDIR}/${TOP}.fasm: ${BOARD_BUILDDIR}/${TOP}.route
 ${BOARD_BUILDDIR}/${TOP}.bit: ${BOARD_BUILDDIR}/${TOP}.fasm
 	cd ${BOARD_BUILDDIR} && symbiflow_write_bitstream -d ${BITSTREAM_DEVICE} -f ${TOP}.fasm -p ${PARTNAME} -b ${TOP}.bit
 
-include ${current_dir}/../../common/Makefile
\ No newline at end of file
+clean:
+	rm -rf ${BUILDDIR}
\ No newline at end of file
diff --git a/xc7/additional_examples/button_controller/display_control.sv b/xc7/additional_examples/button_controller/display_control.sv
index 063f993..f320eb5 100644
--- a/xc7/additional_examples/button_controller/display_control.sv
+++ b/xc7/additional_examples/button_controller/display_control.sv
@@ -10,7 +10,6 @@ module display_control (
     output logic      [ 7:0] segment
 );
 
-<<<<<<< HEAD:xc7/additional_examples/button_controller/display_control.sv
   parameter integer COUNT_BITS = 17;
 
   logic [COUNT_BITS-1:0] count_val;
@@ -23,31 +22,6 @@ module display_control (
     else count_val <= count_val + 1;
   end
 
-=======
-module display_control (
-    input  wire logic        clk,
-    input  wire logic        reset,
-    input  wire logic [15:0] dataIn,
-    input  wire logic [ 3:0] digitDisplay,
-    input  wire logic [ 3:0] digitPoint,
-    output logic      [ 3:0] anode,
-    output logic      [ 7:0] segment
-);
-
-  parameter integer COUNT_BITS = 17;
-
-  logic [COUNT_BITS-1:0] count_val;
-  logic [           1:0] anode_select;
-  logic [           3:0] cur_anode;
-  logic [           3:0] cur_data_in;
-
-
-  always_ff @(posedge clk) begin
-    if (reset) count_val <= 0;
-    else count_val <= count_val + 1;
-  end
-
->>>>>>> Ran PWM and timer through verible formatter and linter:xc7/timer/display_control.sv
   assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2];
 
   assign cur_anode =
@@ -56,10 +30,6 @@ module display_control (
                         (anode_select == 2'b10) ? 4'b1011 :
                         4'b0111;
 
-<<<<<<< HEAD:xc7/additional_examples/button_controller/display_control.sv
-
-=======
->>>>>>> Ran PWM and timer through verible formatter and linter:xc7/timer/display_control.sv
   assign anode = cur_anode | (~digitDisplay);
 
   assign cur_data_in =
diff --git a/xc7/pulse_width_led/Makefile b/xc7/pulse_width_led/Makefile
new file mode 100644
index 0000000..d4069df
--- /dev/null
+++ b/xc7/pulse_width_led/Makefile
@@ -0,0 +1,9 @@
+current_dir := ${CURDIR}
+TARGET := arty_35
+TOP := top
+SOURCES := ${current_dir}/PWM.v
+SOURCES += ${current_dir}/pulse_led.v
+
+XDC := ${current_dir}/arty_35.xdc
+
+include ${current_dir}/../../common/Makefile
\ No newline at end of file
diff --git a/xc7/pulse_width_led/arty_35.xdc b/xc7/pulse_width_led/arty_35.xdc
new file mode 100644
index 0000000..2758008
--- /dev/null
+++ b/xc7/pulse_width_led/arty_35.xdc
@@ -0,0 +1,26 @@
+
+# Clock signal
+set_property PACKAGE_PIN E3  [get_ports { clk }];
+set_property IOSTANDARD LVCMOS33 [get_ports { clk }];
+
+# Switches
+set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }];
+set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }];
+set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }];
+set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }];
+
+
+# RGB LEDs
+set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { pulse_blue }]; 
+set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { pulse_green }]; 
+set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { pulse_red }]; 
+
+# Buttons
+set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; 
+set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; 
+set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; 
+set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; 
+
+
+# CLK constraint
+create_clock -period 10.0 [get_ports {clk}]
\ No newline at end of file
diff --git a/xc7/timer/README.rst b/xc7/timer/README.rst
new file mode 100644
index 0000000..3e81195
--- /dev/null
+++ b/xc7/timer/README.rst
@@ -0,0 +1,31 @@
+Timer
+~~~~~~
+
+This example is built specifically for the basys3 and demonstrates a greater variety of I/O 
+then previous designs. It also demonstrates symbiflow's support for code written in System Verilog 
+as well as its support of dictionaries in XDCs. To build this example run the following commands:
+
+.. code-block:: bash
+   :name: example-watch-basys3
+
+   make -C timer
+
+
+At completion, the bitstream is located in the build directory:
+
+.. code-block:: bash
+
+   cd timer/build/basys3
+
+Now, you can upload the design with:
+
+.. code-block:: bash
+
+   openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
+
+After downloading the bitstream you can start and stop the watch by toggling switch 0 on the board.
+Press the center button to reset the counter. The following gives a visual example:
+
+.. image:: ../../docs/images/timer.gif
+   :align: center
+   :width: 50%
\ No newline at end of file
diff --git a/xc7/timer/basys3.xdc b/xc7/timer/basys3.xdc
new file mode 100644
index 0000000..b415f9a
--- /dev/null
+++ b/xc7/timer/basys3.xdc
@@ -0,0 +1,26 @@
+
+# Clock
+ set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { clk }]; 
+ create_clock -period 10.00 [get_ports {clk}];
+
+# Buttons 
+ set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; 
+
+
+# Switches
+ set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { sw }]; 
+ 
+
+# Seven Segment Display
+ set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { segment[0] }]; 
+ set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { segment[1] }]; 
+ set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { segment[2] }]; 
+ set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { segment[3] }]; 
+ set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { segment[4] }]; 
+ set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { segment[5] }]; 
+ set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { segment[6] }]; 
+ set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { segment[7] }]; 
+ set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports { anode[0] }]; 
+ set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports { anode[1] }]; 
+ set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports { anode[2] }]; 
+ set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports { anode[3] }];
\ No newline at end of file
diff --git a/xc7/timer/display_control.sv b/xc7/timer/display_control.sv
index 063f993..ab0d7a5 100644
--- a/xc7/timer/display_control.sv
+++ b/xc7/timer/display_control.sv
@@ -1,29 +1,6 @@
 `default_nettype none
 
-module display_control (
-    input  wire logic        clk,
-    input  wire logic        reset,
-    input  wire logic [15:0] dataIn,
-    input  wire logic [ 3:0] digitDisplay,
-    input  wire logic [ 3:0] digitPoint,
-    output logic      [ 3:0] anode,
-    output logic      [ 7:0] segment
-);
 
-<<<<<<< HEAD:xc7/additional_examples/button_controller/display_control.sv
-  parameter integer COUNT_BITS = 17;
-
-  logic [COUNT_BITS-1:0] count_val;
-  logic [           1:0] anode_select;
-  logic [           3:0] cur_anode;
-  logic [           3:0] cur_data_in;
-
-  always_ff @(posedge clk) begin
-    if (reset) count_val <= 0;
-    else count_val <= count_val + 1;
-  end
-
-=======
 module display_control (
     input  wire logic        clk,
     input  wire logic        reset,
@@ -47,7 +24,6 @@ module display_control (
     else count_val <= count_val + 1;
   end
 
->>>>>>> Ran PWM and timer through verible formatter and linter:xc7/timer/display_control.sv
   assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2];
 
   assign cur_anode =
@@ -56,10 +32,6 @@ module display_control (
                         (anode_select == 2'b10) ? 4'b1011 :
                         4'b0111;
 
-<<<<<<< HEAD:xc7/additional_examples/button_controller/display_control.sv
-
-=======
->>>>>>> Ran PWM and timer through verible formatter and linter:xc7/timer/display_control.sv
   assign anode = cur_anode | (~digitDisplay);
 
   assign cur_data_in =