From fe5f069ee67067e4a0d4b9f9a87b5c31fcb2c01a Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Tue, 31 May 2022 10:28:01 +0200 Subject: [PATCH] ci: save bitstreams and plots to separated artifacts Signed-off-by: Unai Martinez-Corral --- .github/workflows/sphinx-tuttest.yml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/.github/workflows/sphinx-tuttest.yml b/.github/workflows/sphinx-tuttest.yml index 93ec4a5..5968cae 100644 --- a/.github/workflows/sphinx-tuttest.yml +++ b/.github/workflows/sphinx-tuttest.yml @@ -76,9 +76,12 @@ jobs: - uses: actions/upload-artifact@v3 with: name: f4pga-examples-bitstreams - path: | - **/*.bit - **/plot_*.svg + path: '**/*.bit' + + - uses: actions/upload-artifact@v3 + with: + name: f4pga-examples-plots + path: '**/plot_*.svg' Test-Surelog: @@ -130,6 +133,9 @@ jobs: - uses: actions/upload-artifact@v3 with: name: f4pga-examples-bitstreams-systemverilog-plugin - path: | - **/*.bit - **/plot_*.svg + path: '**/*.bit' + + - uses: actions/upload-artifact@v3 + with: + name: f4pga-examples-plots-systemverilog-plugin + path: '**/plot_*.svg'