From 1e92d9c28892f55725279c9c00ba26fc0bf44eb3 Mon Sep 17 00:00:00 2001
From: Chandler Jearls <cjearls@vt.edu>
Date: Wed, 21 Apr 2021 16:34:26 +0000
Subject: [PATCH 1/3] added support for Nexys4DDR board in counter_test

Signed-off-by: Chandler Jearls <cjearls@vt.edu>
---
 xc7/counter_test/Makefile      |  5 +++++
 xc7/counter_test/nexys4ddr.xdc | 16 ++++++++++++++++
 2 files changed, 21 insertions(+)
 create mode 100644 xc7/counter_test/nexys4ddr.xdc

diff --git a/xc7/counter_test/Makefile b/xc7/counter_test/Makefile
index 6233086..6a8aa87 100644
--- a/xc7/counter_test/Makefile
+++ b/xc7/counter_test/Makefile
@@ -15,6 +15,11 @@ else ifeq ($(TARGET),arty_100)
   XDC:=${current_dir}/arty.xdc
   DEVICE:= xc7a100t_test
   BOARD_BUILDDIR := ${BUILDDIR}/arty_100
+else ifeq ($(TARGET),nexys4ddr)
+  PARTNAME:= xc7a100tcsg324-1
+  XDC:=${current_dir}/nexys4ddr.xdc
+  DEVICE:= xc7a100t_test
+  BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
 else ifeq ($(TARGET),zybo)
   PARTNAME:= xc7z010clg400-1
   XDC:=${current_dir}/zybo.xdc
diff --git a/xc7/counter_test/nexys4ddr.xdc b/xc7/counter_test/nexys4ddr.xdc
new file mode 100644
index 0000000..76c599e
--- /dev/null
+++ b/xc7/counter_test/nexys4ddr.xdc
@@ -0,0 +1,16 @@
+# Clock pin
+set_property PACKAGE_PIN E3 [get_ports {clk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
+
+# LEDs
+set_property PACKAGE_PIN H17  [get_ports {led[0]}]
+set_property PACKAGE_PIN K15  [get_ports {led[1]}]
+set_property PACKAGE_PIN J13  [get_ports {led[2]}]
+set_property PACKAGE_PIN N14  [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+
+# Clock constraints
+create_clock -period 10.0 [get_ports {clk}]
\ No newline at end of file

From 8c67e280e1c8e0663c3784ba4d90c333d90c33e2 Mon Sep 17 00:00:00 2001
From: Chandler Jearls <cjearls@vt.edu>
Date: Wed, 21 Apr 2021 17:48:13 +0000
Subject: [PATCH 2/3] added Nexys4DDR to the documentation

Signed-off-by: Chandler Jearls <cjearls@vt.edu>
---
 docs/collect_readmes.py     | 1 +
 xc7/counter_test/README.rst | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/docs/collect_readmes.py b/docs/collect_readmes.py
index cb989cc..0029852 100644
--- a/docs/collect_readmes.py
+++ b/docs/collect_readmes.py
@@ -5,6 +5,7 @@ from docutils.core import publish_doctree
 full_name_lut = {
     'a35t': 'Arty 35T',
     'a100t': 'Arty 100T',
+    'nexys4DDR': 'Nexys 4 DDR',
     'basys3': 'Basys 3',
     'eos_s3': 'EOS S3',
     'zybo': 'Zybo Z7',
diff --git a/xc7/counter_test/README.rst b/xc7/counter_test/README.rst
index d65d88b..6d1545c 100644
--- a/xc7/counter_test/README.rst
+++ b/xc7/counter_test/README.rst
@@ -16,6 +16,11 @@ counter example, depending on your hardware, run:
    TARGET="arty_100" make -C counter_test
 
 
+.. code-block:: bash
+   :name: example-counter-nexys4ddr-group
+
+   TARGET="nexys4ddr" make -C counter_test
+
 .. code-block:: bash
    :name: example-counter-basys3-group
 

From d2b0747fbe03328f66ee4ed60f69e43a2859e211 Mon Sep 17 00:00:00 2001
From: Chandler Jearls <cjearls@vt.edu>
Date: Wed, 21 Apr 2021 17:52:09 +0000
Subject: [PATCH 3/3] fixed a small typo in collect_readmes.py

Signed-off-by: Chandler Jearls <cjearls@vt.edu>
---
 docs/collect_readmes.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/collect_readmes.py b/docs/collect_readmes.py
index 0029852..99659e5 100644
--- a/docs/collect_readmes.py
+++ b/docs/collect_readmes.py
@@ -5,7 +5,7 @@ from docutils.core import publish_doctree
 full_name_lut = {
     'a35t': 'Arty 35T',
     'a100t': 'Arty 100T',
-    'nexys4DDR': 'Nexys 4 DDR',
+    'nexys4ddr': 'Nexys 4 DDR',
     'basys3': 'Basys 3',
     'eos_s3': 'EOS S3',
     'zybo': 'Zybo Z7',