//-------------------------------------------------------------------------------- // Auto-generated by Migen (c50ecde) & LiteX (95b310ee) on 2021-11-22 10:12:20 //-------------------------------------------------------------------------------- module top( output reg serial_tx, input wire serial_rx, input wire cpu_reset, (* dont_touch = "true" *) input wire clk100, output wire [14:0] ddram_a, output wire [2:0] ddram_ba, output wire ddram_ras_n, output wire ddram_cas_n, output wire ddram_we_n, output wire [1:0] ddram_dm, inout wire [15:0] ddram_dq, inout wire [1:0] ddram_dqs_p, inout wire [1:0] ddram_dqs_n, output wire ddram_clk_p, output wire ddram_clk_n, output wire ddram_cke, output wire ddram_odt, output wire ddram_reset_n, input wire fmc2sata_clk_p, input wire fmc2sata_clk_n, output wire fmc2sata_tx_p, output wire fmc2sata_tx_n, input wire fmc2sata_rx_p, input wire fmc2sata_rx_n, output reg user_led0, output reg user_led1, output reg user_led2, output reg user_led3, output reg user_led4, output reg user_led5, output reg user_led6, output reg user_led7, output wire [1:0] vadj ); // VADJ adjust the output voltage and 3.3V is required for the FMC2SATA adapter board to properly work // A value of 2'b11 provides the necessary 3.3V assign vadj = 2'b11; reg soccontroller_reset_storage = 1'd0; reg soccontroller_reset_re = 1'd0; reg [31:0] soccontroller_scratch_storage = 32'd305419896; reg soccontroller_scratch_re = 1'd0; wire [31:0] soccontroller_bus_errors_status; wire soccontroller_bus_errors_we; reg soccontroller_bus_errors_re = 1'd0; wire soccontroller_reset; wire soccontroller_bus_error; reg [31:0] soccontroller_bus_errors = 32'd0; wire cpu_reset_1; reg [31:0] cpu_interrupt = 32'd0; wire [29:0] cpu_ibus_adr; wire [31:0] cpu_ibus_dat_w; wire [31:0] cpu_ibus_dat_r; wire [3:0] cpu_ibus_sel; wire cpu_ibus_cyc; wire cpu_ibus_stb; wire cpu_ibus_ack; wire cpu_ibus_we; wire [2:0] cpu_ibus_cti; wire [1:0] cpu_ibus_bte; wire cpu_ibus_err; wire [29:0] cpu_dbus_adr; wire [31:0] cpu_dbus_dat_w; wire [31:0] cpu_dbus_dat_r; wire [3:0] cpu_dbus_sel; wire cpu_dbus_cyc; wire cpu_dbus_stb; wire cpu_dbus_ack; wire cpu_dbus_we; wire [2:0] cpu_dbus_cti; wire [1:0] cpu_dbus_bte; wire cpu_dbus_err; reg [31:0] vexriscv = 32'd0; wire [29:0] basesoc_ram_bus_adr; wire [31:0] basesoc_ram_bus_dat_w; wire [31:0] basesoc_ram_bus_dat_r; wire [3:0] basesoc_ram_bus_sel; wire basesoc_ram_bus_cyc; wire basesoc_ram_bus_stb; reg basesoc_ram_bus_ack = 1'd0; wire basesoc_ram_bus_we; wire [2:0] basesoc_ram_bus_cti; wire [1:0] basesoc_ram_bus_bte; reg basesoc_ram_bus_err = 1'd0; wire [13:0] basesoc_adr; wire [31:0] basesoc_dat_r; wire [29:0] ram_bus_ram_bus_adr; wire [31:0] ram_bus_ram_bus_dat_w; wire [31:0] ram_bus_ram_bus_dat_r; wire [3:0] ram_bus_ram_bus_sel; wire ram_bus_ram_bus_cyc; wire ram_bus_ram_bus_stb; reg ram_bus_ram_bus_ack = 1'd0; wire ram_bus_ram_bus_we; wire [2:0] ram_bus_ram_bus_cti; wire [1:0] ram_bus_ram_bus_bte; reg ram_bus_ram_bus_err = 1'd0; wire [10:0] ram_adr; wire [31:0] ram_dat_r; reg [3:0] ram_we = 4'd0; wire [31:0] ram_dat_w; reg [31:0] uart_phy_storage = 32'd6184752; reg uart_phy_re = 1'd0; wire uart_phy_sink_valid; reg uart_phy_sink_ready = 1'd0; wire uart_phy_sink_first; wire uart_phy_sink_last; wire [7:0] uart_phy_sink_payload_data; reg uart_phy_tx_clken = 1'd0; reg [31:0] uart_phy_tx_clkphase = 32'd0; reg [7:0] uart_phy_tx_reg = 8'd0; reg [3:0] uart_phy_tx_bitcount = 4'd0; reg uart_phy_tx_busy = 1'd0; reg uart_phy_source_valid = 1'd0; wire uart_phy_source_ready; reg uart_phy_source_first = 1'd0; reg uart_phy_source_last = 1'd0; reg [7:0] uart_phy_source_payload_data = 8'd0; reg uart_phy_rx_clken = 1'd0; reg [31:0] uart_phy_rx_clkphase = 32'd0; wire uart_phy_rx; reg uart_phy_rx_r = 1'd0; reg [7:0] uart_phy_rx_reg = 8'd0; reg [3:0] uart_phy_rx_bitcount = 4'd0; reg uart_phy_rx_busy = 1'd0; wire uart_rxtx_re; wire [7:0] uart_rxtx_r; wire uart_rxtx_we; wire [7:0] uart_rxtx_w; wire uart_txfull_status; wire uart_txfull_we; reg uart_txfull_re = 1'd0; wire uart_rxempty_status; wire uart_rxempty_we; reg uart_rxempty_re = 1'd0; wire uart_irq; wire uart_tx_status; reg uart_tx_pending = 1'd0; wire uart_tx_trigger; reg uart_tx_clear = 1'd0; reg uart_tx_old_trigger = 1'd0; wire uart_rx_status; reg uart_rx_pending = 1'd0; wire uart_rx_trigger; reg uart_rx_clear = 1'd0; reg uart_rx_old_trigger = 1'd0; wire uart_tx0; wire uart_rx0; reg [1:0] uart_status_status = 2'd0; wire uart_status_we; reg uart_status_re = 1'd0; wire uart_tx1; wire uart_rx1; reg [1:0] uart_pending_status = 2'd0; wire uart_pending_we; reg uart_pending_re = 1'd0; reg [1:0] uart_pending_r = 2'd0; wire uart_tx2; wire uart_rx2; reg [1:0] uart_enable_storage = 2'd0; reg uart_enable_re = 1'd0; wire uart_txempty_status; wire uart_txempty_we; reg uart_txempty_re = 1'd0; wire uart_rxfull_status; wire uart_rxfull_we; reg uart_rxfull_re = 1'd0; wire uart_uart_sink_valid; wire uart_uart_sink_ready; wire uart_uart_sink_first; wire uart_uart_sink_last; wire [7:0] uart_uart_sink_payload_data; wire uart_uart_source_valid; wire uart_uart_source_ready; wire uart_uart_source_first; wire uart_uart_source_last; wire [7:0] uart_uart_source_payload_data; wire uart_tx_fifo_sink_valid; wire uart_tx_fifo_sink_ready; reg uart_tx_fifo_sink_first = 1'd0; reg uart_tx_fifo_sink_last = 1'd0; wire [7:0] uart_tx_fifo_sink_payload_data; wire uart_tx_fifo_source_valid; wire uart_tx_fifo_source_ready; wire uart_tx_fifo_source_first; wire uart_tx_fifo_source_last; wire [7:0] uart_tx_fifo_source_payload_data; wire uart_tx_fifo_re; reg uart_tx_fifo_readable = 1'd0; wire uart_tx_fifo_syncfifo_we; wire uart_tx_fifo_syncfifo_writable; wire uart_tx_fifo_syncfifo_re; wire uart_tx_fifo_syncfifo_readable; wire [9:0] uart_tx_fifo_syncfifo_din; wire [9:0] uart_tx_fifo_syncfifo_dout; reg [4:0] uart_tx_fifo_level0 = 5'd0; reg uart_tx_fifo_replace = 1'd0; reg [3:0] uart_tx_fifo_produce = 4'd0; reg [3:0] uart_tx_fifo_consume = 4'd0; reg [3:0] uart_tx_fifo_wrport_adr = 4'd0; wire [9:0] uart_tx_fifo_wrport_dat_r; wire uart_tx_fifo_wrport_we; wire [9:0] uart_tx_fifo_wrport_dat_w; wire uart_tx_fifo_do_read; wire [3:0] uart_tx_fifo_rdport_adr; wire [9:0] uart_tx_fifo_rdport_dat_r; wire uart_tx_fifo_rdport_re; wire [4:0] uart_tx_fifo_level1; wire [7:0] uart_tx_fifo_fifo_in_payload_data; wire uart_tx_fifo_fifo_in_first; wire uart_tx_fifo_fifo_in_last; wire [7:0] uart_tx_fifo_fifo_out_payload_data; wire uart_tx_fifo_fifo_out_first; wire uart_tx_fifo_fifo_out_last; wire uart_rx_fifo_sink_valid; wire uart_rx_fifo_sink_ready; wire uart_rx_fifo_sink_first; wire uart_rx_fifo_sink_last; wire [7:0] uart_rx_fifo_sink_payload_data; wire uart_rx_fifo_source_valid; wire uart_rx_fifo_source_ready; wire uart_rx_fifo_source_first; wire uart_rx_fifo_source_last; wire [7:0] uart_rx_fifo_source_payload_data; wire uart_rx_fifo_re; reg uart_rx_fifo_readable = 1'd0; wire uart_rx_fifo_syncfifo_we; wire uart_rx_fifo_syncfifo_writable; wire uart_rx_fifo_syncfifo_re; wire uart_rx_fifo_syncfifo_readable; wire [9:0] uart_rx_fifo_syncfifo_din; wire [9:0] uart_rx_fifo_syncfifo_dout; reg [4:0] uart_rx_fifo_level0 = 5'd0; reg uart_rx_fifo_replace = 1'd0; reg [3:0] uart_rx_fifo_produce = 4'd0; reg [3:0] uart_rx_fifo_consume = 4'd0; reg [3:0] uart_rx_fifo_wrport_adr = 4'd0; wire [9:0] uart_rx_fifo_wrport_dat_r; wire uart_rx_fifo_wrport_we; wire [9:0] uart_rx_fifo_wrport_dat_w; wire uart_rx_fifo_do_read; wire [3:0] uart_rx_fifo_rdport_adr; wire [9:0] uart_rx_fifo_rdport_dat_r; wire uart_rx_fifo_rdport_re; wire [4:0] uart_rx_fifo_level1; wire [7:0] uart_rx_fifo_fifo_in_payload_data; wire uart_rx_fifo_fifo_in_first; wire uart_rx_fifo_fifo_in_last; wire [7:0] uart_rx_fifo_fifo_out_payload_data; wire uart_rx_fifo_fifo_out_first; wire uart_rx_fifo_fifo_out_last; reg [31:0] timer_load_storage = 32'd0; reg timer_load_re = 1'd0; reg [31:0] timer_reload_storage = 32'd0; reg timer_reload_re = 1'd0; reg timer_en_storage = 1'd0; reg timer_en_re = 1'd0; reg timer_update_value_storage = 1'd0; reg timer_update_value_re = 1'd0; reg [31:0] timer_value_status = 32'd0; wire timer_value_we; reg timer_value_re = 1'd0; wire timer_irq; wire timer_zero_status; reg timer_zero_pending = 1'd0; wire timer_zero_trigger; reg timer_zero_clear = 1'd0; reg timer_zero_old_trigger = 1'd0; wire timer_zero0; wire timer_status_status; wire timer_status_we; reg timer_status_re = 1'd0; wire timer_zero1; wire timer_pending_status; wire timer_pending_we; reg timer_pending_re = 1'd0; reg timer_pending_r = 1'd0; wire timer_zero2; reg timer_enable_storage = 1'd0; reg timer_enable_re = 1'd0; reg [31:0] timer_value = 32'd0; wire crg_rst; wire sys_clk; wire sys_rst; wire sys4x_clk; wire sys4x_dqs_clk; wire idelay_clk; wire idelay_rst; wire clk100_clk; wire clk100_rst; wire crg_reset; wire crg_locked; wire crg_clkin; wire crg_clkout0; wire crg_clkout_buf0; wire crg_clkout1; wire crg_clkout_buf1; wire crg_clkout2; wire crg_clkout_buf2; wire crg_clkout3; wire crg_clkout_buf3; wire crg_clkout4; wire crg_clkout_buf4; reg [3:0] crg_reset_counter = 4'd15; reg crg_ic_reset = 1'd1; reg a7ddrphy_rst_storage = 1'd0; reg a7ddrphy_rst_re = 1'd0; reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd10; reg a7ddrphy_half_sys8x_taps_re = 1'd0; reg a7ddrphy_wlevel_en_storage = 1'd0; reg a7ddrphy_wlevel_en_re = 1'd0; wire a7ddrphy_wlevel_strobe_re; wire a7ddrphy_wlevel_strobe_r; wire a7ddrphy_wlevel_strobe_we; reg a7ddrphy_wlevel_strobe_w = 1'd0; reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; reg a7ddrphy_dly_sel_re = 1'd0; wire a7ddrphy_rdly_dq_rst_re; wire a7ddrphy_rdly_dq_rst_r; wire a7ddrphy_rdly_dq_rst_we; reg a7ddrphy_rdly_dq_rst_w = 1'd0; wire a7ddrphy_rdly_dq_inc_re; wire a7ddrphy_rdly_dq_inc_r; wire a7ddrphy_rdly_dq_inc_we; reg a7ddrphy_rdly_dq_inc_w = 1'd0; wire a7ddrphy_rdly_dq_bitslip_rst_re; wire a7ddrphy_rdly_dq_bitslip_rst_r; wire a7ddrphy_rdly_dq_bitslip_rst_we; reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; wire a7ddrphy_rdly_dq_bitslip_re; wire a7ddrphy_rdly_dq_bitslip_r; wire a7ddrphy_rdly_dq_bitslip_we; reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; wire a7ddrphy_wdly_dq_bitslip_rst_re; wire a7ddrphy_wdly_dq_bitslip_rst_r; wire a7ddrphy_wdly_dq_bitslip_rst_we; reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; wire a7ddrphy_wdly_dq_bitslip_re; wire a7ddrphy_wdly_dq_bitslip_r; wire a7ddrphy_wdly_dq_bitslip_we; reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; reg [1:0] a7ddrphy_rdphase_storage = 2'd2; reg a7ddrphy_rdphase_re = 1'd0; reg [1:0] a7ddrphy_wrphase_storage = 2'd3; reg a7ddrphy_wrphase_re = 1'd0; wire [14:0] a7ddrphy_dfi_p0_address; wire [2:0] a7ddrphy_dfi_p0_bank; wire a7ddrphy_dfi_p0_cas_n; wire a7ddrphy_dfi_p0_cs_n; wire a7ddrphy_dfi_p0_ras_n; wire a7ddrphy_dfi_p0_we_n; wire a7ddrphy_dfi_p0_cke; wire a7ddrphy_dfi_p0_odt; wire a7ddrphy_dfi_p0_reset_n; wire a7ddrphy_dfi_p0_act_n; wire [31:0] a7ddrphy_dfi_p0_wrdata; wire a7ddrphy_dfi_p0_wrdata_en; wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; wire a7ddrphy_dfi_p0_rddata_en; reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; wire a7ddrphy_dfi_p0_rddata_valid; wire [14:0] a7ddrphy_dfi_p1_address; wire [2:0] a7ddrphy_dfi_p1_bank; wire a7ddrphy_dfi_p1_cas_n; wire a7ddrphy_dfi_p1_cs_n; wire a7ddrphy_dfi_p1_ras_n; wire a7ddrphy_dfi_p1_we_n; wire a7ddrphy_dfi_p1_cke; wire a7ddrphy_dfi_p1_odt; wire a7ddrphy_dfi_p1_reset_n; wire a7ddrphy_dfi_p1_act_n; wire [31:0] a7ddrphy_dfi_p1_wrdata; wire a7ddrphy_dfi_p1_wrdata_en; wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; wire a7ddrphy_dfi_p1_rddata_en; reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; wire a7ddrphy_dfi_p1_rddata_valid; wire [14:0] a7ddrphy_dfi_p2_address; wire [2:0] a7ddrphy_dfi_p2_bank; wire a7ddrphy_dfi_p2_cas_n; wire a7ddrphy_dfi_p2_cs_n; wire a7ddrphy_dfi_p2_ras_n; wire a7ddrphy_dfi_p2_we_n; wire a7ddrphy_dfi_p2_cke; wire a7ddrphy_dfi_p2_odt; wire a7ddrphy_dfi_p2_reset_n; wire a7ddrphy_dfi_p2_act_n; wire [31:0] a7ddrphy_dfi_p2_wrdata; wire a7ddrphy_dfi_p2_wrdata_en; wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; wire a7ddrphy_dfi_p2_rddata_en; reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; wire a7ddrphy_dfi_p2_rddata_valid; wire [14:0] a7ddrphy_dfi_p3_address; wire [2:0] a7ddrphy_dfi_p3_bank; wire a7ddrphy_dfi_p3_cas_n; wire a7ddrphy_dfi_p3_cs_n; wire a7ddrphy_dfi_p3_ras_n; wire a7ddrphy_dfi_p3_we_n; wire a7ddrphy_dfi_p3_cke; wire a7ddrphy_dfi_p3_odt; wire a7ddrphy_dfi_p3_reset_n; wire a7ddrphy_dfi_p3_act_n; wire [31:0] a7ddrphy_dfi_p3_wrdata; wire a7ddrphy_dfi_p3_wrdata_en; wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; wire a7ddrphy_dfi_p3_rddata_en; reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; wire a7ddrphy_dfi_p3_rddata_valid; wire a7ddrphy_sd_clk_se_nodelay; reg a7ddrphy_dqs_oe = 1'd0; wire a7ddrphy_dqs_preamble; wire a7ddrphy_dqs_postamble; wire a7ddrphy_dqs_oe_delay_tappeddelayline; reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; reg a7ddrphy_dqspattern0 = 1'd0; reg a7ddrphy_dqspattern1 = 1'd0; reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; wire a7ddrphy_dqs_o_no_delay0; wire a7ddrphy_dqs_t0; reg [7:0] a7ddrphy_bitslip00 = 8'd0; reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; wire a7ddrphy0; wire a7ddrphy_dqs_o_no_delay1; wire a7ddrphy_dqs_t1; reg [7:0] a7ddrphy_bitslip10 = 8'd0; reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; wire a7ddrphy1; reg [7:0] a7ddrphy_bitslip01 = 8'd0; reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; reg [7:0] a7ddrphy_bitslip11 = 8'd0; reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; wire a7ddrphy_dq_oe; wire a7ddrphy_dq_oe_delay_tappeddelayline; reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; wire a7ddrphy_dq_o_nodelay0; wire a7ddrphy_dq_i_nodelay0; wire a7ddrphy_dq_i_delayed0; wire a7ddrphy_dq_t0; reg [7:0] a7ddrphy_bitslip02 = 8'd0; reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; wire [7:0] a7ddrphy_bitslip03; reg [7:0] a7ddrphy_bitslip04 = 8'd0; reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; wire a7ddrphy_dq_o_nodelay1; wire a7ddrphy_dq_i_nodelay1; wire a7ddrphy_dq_i_delayed1; wire a7ddrphy_dq_t1; reg [7:0] a7ddrphy_bitslip12 = 8'd0; reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; wire [7:0] a7ddrphy_bitslip13; reg [7:0] a7ddrphy_bitslip14 = 8'd0; reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; wire a7ddrphy_dq_o_nodelay2; wire a7ddrphy_dq_i_nodelay2; wire a7ddrphy_dq_i_delayed2; wire a7ddrphy_dq_t2; reg [7:0] a7ddrphy_bitslip20 = 8'd0; reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip21; reg [7:0] a7ddrphy_bitslip22 = 8'd0; reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay3; wire a7ddrphy_dq_i_nodelay3; wire a7ddrphy_dq_i_delayed3; wire a7ddrphy_dq_t3; reg [7:0] a7ddrphy_bitslip30 = 8'd0; reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip31; reg [7:0] a7ddrphy_bitslip32 = 8'd0; reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay4; wire a7ddrphy_dq_i_nodelay4; wire a7ddrphy_dq_i_delayed4; wire a7ddrphy_dq_t4; reg [7:0] a7ddrphy_bitslip40 = 8'd0; reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip41; reg [7:0] a7ddrphy_bitslip42 = 8'd0; reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay5; wire a7ddrphy_dq_i_nodelay5; wire a7ddrphy_dq_i_delayed5; wire a7ddrphy_dq_t5; reg [7:0] a7ddrphy_bitslip50 = 8'd0; reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip51; reg [7:0] a7ddrphy_bitslip52 = 8'd0; reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay6; wire a7ddrphy_dq_i_nodelay6; wire a7ddrphy_dq_i_delayed6; wire a7ddrphy_dq_t6; reg [7:0] a7ddrphy_bitslip60 = 8'd0; reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip61; reg [7:0] a7ddrphy_bitslip62 = 8'd0; reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay7; wire a7ddrphy_dq_i_nodelay7; wire a7ddrphy_dq_i_delayed7; wire a7ddrphy_dq_t7; reg [7:0] a7ddrphy_bitslip70 = 8'd0; reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip71; reg [7:0] a7ddrphy_bitslip72 = 8'd0; reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay8; wire a7ddrphy_dq_i_nodelay8; wire a7ddrphy_dq_i_delayed8; wire a7ddrphy_dq_t8; reg [7:0] a7ddrphy_bitslip80 = 8'd0; reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip81; reg [7:0] a7ddrphy_bitslip82 = 8'd0; reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay9; wire a7ddrphy_dq_i_nodelay9; wire a7ddrphy_dq_i_delayed9; wire a7ddrphy_dq_t9; reg [7:0] a7ddrphy_bitslip90 = 8'd0; reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip91; reg [7:0] a7ddrphy_bitslip92 = 8'd0; reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay10; wire a7ddrphy_dq_i_nodelay10; wire a7ddrphy_dq_i_delayed10; wire a7ddrphy_dq_t10; reg [7:0] a7ddrphy_bitslip100 = 8'd0; reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip101; reg [7:0] a7ddrphy_bitslip102 = 8'd0; reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay11; wire a7ddrphy_dq_i_nodelay11; wire a7ddrphy_dq_i_delayed11; wire a7ddrphy_dq_t11; reg [7:0] a7ddrphy_bitslip110 = 8'd0; reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip111; reg [7:0] a7ddrphy_bitslip112 = 8'd0; reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay12; wire a7ddrphy_dq_i_nodelay12; wire a7ddrphy_dq_i_delayed12; wire a7ddrphy_dq_t12; reg [7:0] a7ddrphy_bitslip120 = 8'd0; reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip121; reg [7:0] a7ddrphy_bitslip122 = 8'd0; reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay13; wire a7ddrphy_dq_i_nodelay13; wire a7ddrphy_dq_i_delayed13; wire a7ddrphy_dq_t13; reg [7:0] a7ddrphy_bitslip130 = 8'd0; reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip131; reg [7:0] a7ddrphy_bitslip132 = 8'd0; reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay14; wire a7ddrphy_dq_i_nodelay14; wire a7ddrphy_dq_i_delayed14; wire a7ddrphy_dq_t14; reg [7:0] a7ddrphy_bitslip140 = 8'd0; reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip141; reg [7:0] a7ddrphy_bitslip142 = 8'd0; reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay15; wire a7ddrphy_dq_i_nodelay15; wire a7ddrphy_dq_i_delayed15; wire a7ddrphy_dq_t15; reg [7:0] a7ddrphy_bitslip150 = 8'd0; reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip151; reg [7:0] a7ddrphy_bitslip152 = 8'd0; reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; wire [13:0] sdram_inti_p0_address; wire [2:0] sdram_inti_p0_bank; reg sdram_inti_p0_cas_n = 1'd1; reg sdram_inti_p0_cs_n = 1'd1; reg sdram_inti_p0_ras_n = 1'd1; reg sdram_inti_p0_we_n = 1'd1; wire sdram_inti_p0_cke; wire sdram_inti_p0_odt; wire sdram_inti_p0_reset_n; reg sdram_inti_p0_act_n = 1'd1; wire [31:0] sdram_inti_p0_wrdata; wire sdram_inti_p0_wrdata_en; wire [3:0] sdram_inti_p0_wrdata_mask; wire sdram_inti_p0_rddata_en; reg [31:0] sdram_inti_p0_rddata = 32'd0; reg sdram_inti_p0_rddata_valid = 1'd0; wire [13:0] sdram_inti_p1_address; wire [2:0] sdram_inti_p1_bank; reg sdram_inti_p1_cas_n = 1'd1; reg sdram_inti_p1_cs_n = 1'd1; reg sdram_inti_p1_ras_n = 1'd1; reg sdram_inti_p1_we_n = 1'd1; wire sdram_inti_p1_cke; wire sdram_inti_p1_odt; wire sdram_inti_p1_reset_n; reg sdram_inti_p1_act_n = 1'd1; wire [31:0] sdram_inti_p1_wrdata; wire sdram_inti_p1_wrdata_en; wire [3:0] sdram_inti_p1_wrdata_mask; wire sdram_inti_p1_rddata_en; reg [31:0] sdram_inti_p1_rddata = 32'd0; reg sdram_inti_p1_rddata_valid = 1'd0; wire [13:0] sdram_inti_p2_address; wire [2:0] sdram_inti_p2_bank; reg sdram_inti_p2_cas_n = 1'd1; reg sdram_inti_p2_cs_n = 1'd1; reg sdram_inti_p2_ras_n = 1'd1; reg sdram_inti_p2_we_n = 1'd1; wire sdram_inti_p2_cke; wire sdram_inti_p2_odt; wire sdram_inti_p2_reset_n; reg sdram_inti_p2_act_n = 1'd1; wire [31:0] sdram_inti_p2_wrdata; wire sdram_inti_p2_wrdata_en; wire [3:0] sdram_inti_p2_wrdata_mask; wire sdram_inti_p2_rddata_en; reg [31:0] sdram_inti_p2_rddata = 32'd0; reg sdram_inti_p2_rddata_valid = 1'd0; wire [13:0] sdram_inti_p3_address; wire [2:0] sdram_inti_p3_bank; reg sdram_inti_p3_cas_n = 1'd1; reg sdram_inti_p3_cs_n = 1'd1; reg sdram_inti_p3_ras_n = 1'd1; reg sdram_inti_p3_we_n = 1'd1; wire sdram_inti_p3_cke; wire sdram_inti_p3_odt; wire sdram_inti_p3_reset_n; reg sdram_inti_p3_act_n = 1'd1; wire [31:0] sdram_inti_p3_wrdata; wire sdram_inti_p3_wrdata_en; wire [3:0] sdram_inti_p3_wrdata_mask; wire sdram_inti_p3_rddata_en; reg [31:0] sdram_inti_p3_rddata = 32'd0; reg sdram_inti_p3_rddata_valid = 1'd0; wire [13:0] sdram_slave_p0_address; wire [2:0] sdram_slave_p0_bank; wire sdram_slave_p0_cas_n; wire sdram_slave_p0_cs_n; wire sdram_slave_p0_ras_n; wire sdram_slave_p0_we_n; wire sdram_slave_p0_cke; wire sdram_slave_p0_odt; wire sdram_slave_p0_reset_n; wire sdram_slave_p0_act_n; wire [31:0] sdram_slave_p0_wrdata; wire sdram_slave_p0_wrdata_en; wire [3:0] sdram_slave_p0_wrdata_mask; wire sdram_slave_p0_rddata_en; reg [31:0] sdram_slave_p0_rddata = 32'd0; reg sdram_slave_p0_rddata_valid = 1'd0; wire [13:0] sdram_slave_p1_address; wire [2:0] sdram_slave_p1_bank; wire sdram_slave_p1_cas_n; wire sdram_slave_p1_cs_n; wire sdram_slave_p1_ras_n; wire sdram_slave_p1_we_n; wire sdram_slave_p1_cke; wire sdram_slave_p1_odt; wire sdram_slave_p1_reset_n; wire sdram_slave_p1_act_n; wire [31:0] sdram_slave_p1_wrdata; wire sdram_slave_p1_wrdata_en; wire [3:0] sdram_slave_p1_wrdata_mask; wire sdram_slave_p1_rddata_en; reg [31:0] sdram_slave_p1_rddata = 32'd0; reg sdram_slave_p1_rddata_valid = 1'd0; wire [13:0] sdram_slave_p2_address; wire [2:0] sdram_slave_p2_bank; wire sdram_slave_p2_cas_n; wire sdram_slave_p2_cs_n; wire sdram_slave_p2_ras_n; wire sdram_slave_p2_we_n; wire sdram_slave_p2_cke; wire sdram_slave_p2_odt; wire sdram_slave_p2_reset_n; wire sdram_slave_p2_act_n; wire [31:0] sdram_slave_p2_wrdata; wire sdram_slave_p2_wrdata_en; wire [3:0] sdram_slave_p2_wrdata_mask; wire sdram_slave_p2_rddata_en; reg [31:0] sdram_slave_p2_rddata = 32'd0; reg sdram_slave_p2_rddata_valid = 1'd0; wire [13:0] sdram_slave_p3_address; wire [2:0] sdram_slave_p3_bank; wire sdram_slave_p3_cas_n; wire sdram_slave_p3_cs_n; wire sdram_slave_p3_ras_n; wire sdram_slave_p3_we_n; wire sdram_slave_p3_cke; wire sdram_slave_p3_odt; wire sdram_slave_p3_reset_n; wire sdram_slave_p3_act_n; wire [31:0] sdram_slave_p3_wrdata; wire sdram_slave_p3_wrdata_en; wire [3:0] sdram_slave_p3_wrdata_mask; wire sdram_slave_p3_rddata_en; reg [31:0] sdram_slave_p3_rddata = 32'd0; reg sdram_slave_p3_rddata_valid = 1'd0; reg [13:0] sdram_master_p0_address = 14'd0; reg [2:0] sdram_master_p0_bank = 3'd0; reg sdram_master_p0_cas_n = 1'd1; reg sdram_master_p0_cs_n = 1'd1; reg sdram_master_p0_ras_n = 1'd1; reg sdram_master_p0_we_n = 1'd1; reg sdram_master_p0_cke = 1'd0; reg sdram_master_p0_odt = 1'd0; reg sdram_master_p0_reset_n = 1'd0; reg sdram_master_p0_act_n = 1'd1; reg [31:0] sdram_master_p0_wrdata = 32'd0; reg sdram_master_p0_wrdata_en = 1'd0; reg [3:0] sdram_master_p0_wrdata_mask = 4'd0; reg sdram_master_p0_rddata_en = 1'd0; wire [31:0] sdram_master_p0_rddata; wire sdram_master_p0_rddata_valid; reg [13:0] sdram_master_p1_address = 14'd0; reg [2:0] sdram_master_p1_bank = 3'd0; reg sdram_master_p1_cas_n = 1'd1; reg sdram_master_p1_cs_n = 1'd1; reg sdram_master_p1_ras_n = 1'd1; reg sdram_master_p1_we_n = 1'd1; reg sdram_master_p1_cke = 1'd0; reg sdram_master_p1_odt = 1'd0; reg sdram_master_p1_reset_n = 1'd0; reg sdram_master_p1_act_n = 1'd1; reg [31:0] sdram_master_p1_wrdata = 32'd0; reg sdram_master_p1_wrdata_en = 1'd0; reg [3:0] sdram_master_p1_wrdata_mask = 4'd0; reg sdram_master_p1_rddata_en = 1'd0; wire [31:0] sdram_master_p1_rddata; wire sdram_master_p1_rddata_valid; reg [13:0] sdram_master_p2_address = 14'd0; reg [2:0] sdram_master_p2_bank = 3'd0; reg sdram_master_p2_cas_n = 1'd1; reg sdram_master_p2_cs_n = 1'd1; reg sdram_master_p2_ras_n = 1'd1; reg sdram_master_p2_we_n = 1'd1; reg sdram_master_p2_cke = 1'd0; reg sdram_master_p2_odt = 1'd0; reg sdram_master_p2_reset_n = 1'd0; reg sdram_master_p2_act_n = 1'd1; reg [31:0] sdram_master_p2_wrdata = 32'd0; reg sdram_master_p2_wrdata_en = 1'd0; reg [3:0] sdram_master_p2_wrdata_mask = 4'd0; reg sdram_master_p2_rddata_en = 1'd0; wire [31:0] sdram_master_p2_rddata; wire sdram_master_p2_rddata_valid; reg [13:0] sdram_master_p3_address = 14'd0; reg [2:0] sdram_master_p3_bank = 3'd0; reg sdram_master_p3_cas_n = 1'd1; reg sdram_master_p3_cs_n = 1'd1; reg sdram_master_p3_ras_n = 1'd1; reg sdram_master_p3_we_n = 1'd1; reg sdram_master_p3_cke = 1'd0; reg sdram_master_p3_odt = 1'd0; reg sdram_master_p3_reset_n = 1'd0; reg sdram_master_p3_act_n = 1'd1; reg [31:0] sdram_master_p3_wrdata = 32'd0; reg sdram_master_p3_wrdata_en = 1'd0; reg [3:0] sdram_master_p3_wrdata_mask = 4'd0; reg sdram_master_p3_rddata_en = 1'd0; wire [31:0] sdram_master_p3_rddata; wire sdram_master_p3_rddata_valid; wire sdram_sel; wire sdram_cke; wire sdram_odt; wire sdram_reset_n; reg [3:0] sdram_storage = 4'd1; reg sdram_re = 1'd0; reg [5:0] sdram_phaseinjector0_command_storage = 6'd0; reg sdram_phaseinjector0_command_re = 1'd0; wire sdram_phaseinjector0_command_issue_re; wire sdram_phaseinjector0_command_issue_r; wire sdram_phaseinjector0_command_issue_we; reg sdram_phaseinjector0_command_issue_w = 1'd0; reg [13:0] sdram_phaseinjector0_address_storage = 14'd0; reg sdram_phaseinjector0_address_re = 1'd0; reg [2:0] sdram_phaseinjector0_baddress_storage = 3'd0; reg sdram_phaseinjector0_baddress_re = 1'd0; reg [31:0] sdram_phaseinjector0_wrdata_storage = 32'd0; reg sdram_phaseinjector0_wrdata_re = 1'd0; reg [31:0] sdram_phaseinjector0_rddata_status = 32'd0; wire sdram_phaseinjector0_rddata_we; reg sdram_phaseinjector0_rddata_re = 1'd0; reg [5:0] sdram_phaseinjector1_command_storage = 6'd0; reg sdram_phaseinjector1_command_re = 1'd0; wire sdram_phaseinjector1_command_issue_re; wire sdram_phaseinjector1_command_issue_r; wire sdram_phaseinjector1_command_issue_we; reg sdram_phaseinjector1_command_issue_w = 1'd0; reg [13:0] sdram_phaseinjector1_address_storage = 14'd0; reg sdram_phaseinjector1_address_re = 1'd0; reg [2:0] sdram_phaseinjector1_baddress_storage = 3'd0; reg sdram_phaseinjector1_baddress_re = 1'd0; reg [31:0] sdram_phaseinjector1_wrdata_storage = 32'd0; reg sdram_phaseinjector1_wrdata_re = 1'd0; reg [31:0] sdram_phaseinjector1_rddata_status = 32'd0; wire sdram_phaseinjector1_rddata_we; reg sdram_phaseinjector1_rddata_re = 1'd0; reg [5:0] sdram_phaseinjector2_command_storage = 6'd0; reg sdram_phaseinjector2_command_re = 1'd0; wire sdram_phaseinjector2_command_issue_re; wire sdram_phaseinjector2_command_issue_r; wire sdram_phaseinjector2_command_issue_we; reg sdram_phaseinjector2_command_issue_w = 1'd0; reg [13:0] sdram_phaseinjector2_address_storage = 14'd0; reg sdram_phaseinjector2_address_re = 1'd0; reg [2:0] sdram_phaseinjector2_baddress_storage = 3'd0; reg sdram_phaseinjector2_baddress_re = 1'd0; reg [31:0] sdram_phaseinjector2_wrdata_storage = 32'd0; reg sdram_phaseinjector2_wrdata_re = 1'd0; reg [31:0] sdram_phaseinjector2_rddata_status = 32'd0; wire sdram_phaseinjector2_rddata_we; reg sdram_phaseinjector2_rddata_re = 1'd0; reg [5:0] sdram_phaseinjector3_command_storage = 6'd0; reg sdram_phaseinjector3_command_re = 1'd0; wire sdram_phaseinjector3_command_issue_re; wire sdram_phaseinjector3_command_issue_r; wire sdram_phaseinjector3_command_issue_we; reg sdram_phaseinjector3_command_issue_w = 1'd0; reg [13:0] sdram_phaseinjector3_address_storage = 14'd0; reg sdram_phaseinjector3_address_re = 1'd0; reg [2:0] sdram_phaseinjector3_baddress_storage = 3'd0; reg sdram_phaseinjector3_baddress_re = 1'd0; reg [31:0] sdram_phaseinjector3_wrdata_storage = 32'd0; reg sdram_phaseinjector3_wrdata_re = 1'd0; reg [31:0] sdram_phaseinjector3_rddata_status = 32'd0; wire sdram_phaseinjector3_rddata_we; reg sdram_phaseinjector3_rddata_re = 1'd0; wire sdram_interface_bank0_valid; wire sdram_interface_bank0_ready; wire sdram_interface_bank0_we; wire [20:0] sdram_interface_bank0_addr; wire sdram_interface_bank0_lock; wire sdram_interface_bank0_wdata_ready; wire sdram_interface_bank0_rdata_valid; wire sdram_interface_bank1_valid; wire sdram_interface_bank1_ready; wire sdram_interface_bank1_we; wire [20:0] sdram_interface_bank1_addr; wire sdram_interface_bank1_lock; wire sdram_interface_bank1_wdata_ready; wire sdram_interface_bank1_rdata_valid; wire sdram_interface_bank2_valid; wire sdram_interface_bank2_ready; wire sdram_interface_bank2_we; wire [20:0] sdram_interface_bank2_addr; wire sdram_interface_bank2_lock; wire sdram_interface_bank2_wdata_ready; wire sdram_interface_bank2_rdata_valid; wire sdram_interface_bank3_valid; wire sdram_interface_bank3_ready; wire sdram_interface_bank3_we; wire [20:0] sdram_interface_bank3_addr; wire sdram_interface_bank3_lock; wire sdram_interface_bank3_wdata_ready; wire sdram_interface_bank3_rdata_valid; wire sdram_interface_bank4_valid; wire sdram_interface_bank4_ready; wire sdram_interface_bank4_we; wire [20:0] sdram_interface_bank4_addr; wire sdram_interface_bank4_lock; wire sdram_interface_bank4_wdata_ready; wire sdram_interface_bank4_rdata_valid; wire sdram_interface_bank5_valid; wire sdram_interface_bank5_ready; wire sdram_interface_bank5_we; wire [20:0] sdram_interface_bank5_addr; wire sdram_interface_bank5_lock; wire sdram_interface_bank5_wdata_ready; wire sdram_interface_bank5_rdata_valid; wire sdram_interface_bank6_valid; wire sdram_interface_bank6_ready; wire sdram_interface_bank6_we; wire [20:0] sdram_interface_bank6_addr; wire sdram_interface_bank6_lock; wire sdram_interface_bank6_wdata_ready; wire sdram_interface_bank6_rdata_valid; wire sdram_interface_bank7_valid; wire sdram_interface_bank7_ready; wire sdram_interface_bank7_we; wire [20:0] sdram_interface_bank7_addr; wire sdram_interface_bank7_lock; wire sdram_interface_bank7_wdata_ready; wire sdram_interface_bank7_rdata_valid; reg [127:0] sdram_interface_wdata = 128'd0; reg [15:0] sdram_interface_wdata_we = 16'd0; wire [127:0] sdram_interface_rdata; reg [13:0] sdram_dfi_p0_address = 14'd0; reg [2:0] sdram_dfi_p0_bank = 3'd0; reg sdram_dfi_p0_cas_n = 1'd1; reg sdram_dfi_p0_cs_n = 1'd1; reg sdram_dfi_p0_ras_n = 1'd1; reg sdram_dfi_p0_we_n = 1'd1; wire sdram_dfi_p0_cke; wire sdram_dfi_p0_odt; wire sdram_dfi_p0_reset_n; reg sdram_dfi_p0_act_n = 1'd1; wire [31:0] sdram_dfi_p0_wrdata; reg sdram_dfi_p0_wrdata_en = 1'd0; wire [3:0] sdram_dfi_p0_wrdata_mask; reg sdram_dfi_p0_rddata_en = 1'd0; wire [31:0] sdram_dfi_p0_rddata; wire sdram_dfi_p0_rddata_valid; reg [13:0] sdram_dfi_p1_address = 14'd0; reg [2:0] sdram_dfi_p1_bank = 3'd0; reg sdram_dfi_p1_cas_n = 1'd1; reg sdram_dfi_p1_cs_n = 1'd1; reg sdram_dfi_p1_ras_n = 1'd1; reg sdram_dfi_p1_we_n = 1'd1; wire sdram_dfi_p1_cke; wire sdram_dfi_p1_odt; wire sdram_dfi_p1_reset_n; reg sdram_dfi_p1_act_n = 1'd1; wire [31:0] sdram_dfi_p1_wrdata; reg sdram_dfi_p1_wrdata_en = 1'd0; wire [3:0] sdram_dfi_p1_wrdata_mask; reg sdram_dfi_p1_rddata_en = 1'd0; wire [31:0] sdram_dfi_p1_rddata; wire sdram_dfi_p1_rddata_valid; reg [13:0] sdram_dfi_p2_address = 14'd0; reg [2:0] sdram_dfi_p2_bank = 3'd0; reg sdram_dfi_p2_cas_n = 1'd1; reg sdram_dfi_p2_cs_n = 1'd1; reg sdram_dfi_p2_ras_n = 1'd1; reg sdram_dfi_p2_we_n = 1'd1; wire sdram_dfi_p2_cke; wire sdram_dfi_p2_odt; wire sdram_dfi_p2_reset_n; reg sdram_dfi_p2_act_n = 1'd1; wire [31:0] sdram_dfi_p2_wrdata; reg sdram_dfi_p2_wrdata_en = 1'd0; wire [3:0] sdram_dfi_p2_wrdata_mask; reg sdram_dfi_p2_rddata_en = 1'd0; wire [31:0] sdram_dfi_p2_rddata; wire sdram_dfi_p2_rddata_valid; reg [13:0] sdram_dfi_p3_address = 14'd0; reg [2:0] sdram_dfi_p3_bank = 3'd0; reg sdram_dfi_p3_cas_n = 1'd1; reg sdram_dfi_p3_cs_n = 1'd1; reg sdram_dfi_p3_ras_n = 1'd1; reg sdram_dfi_p3_we_n = 1'd1; wire sdram_dfi_p3_cke; wire sdram_dfi_p3_odt; wire sdram_dfi_p3_reset_n; reg sdram_dfi_p3_act_n = 1'd1; wire [31:0] sdram_dfi_p3_wrdata; reg sdram_dfi_p3_wrdata_en = 1'd0; wire [3:0] sdram_dfi_p3_wrdata_mask; reg sdram_dfi_p3_rddata_en = 1'd0; wire [31:0] sdram_dfi_p3_rddata; wire sdram_dfi_p3_rddata_valid; reg sdram_cmd_valid = 1'd0; reg sdram_cmd_ready = 1'd0; reg sdram_cmd_last = 1'd0; reg [13:0] sdram_cmd_payload_a = 14'd0; reg [2:0] sdram_cmd_payload_ba = 3'd0; reg sdram_cmd_payload_cas = 1'd0; reg sdram_cmd_payload_ras = 1'd0; reg sdram_cmd_payload_we = 1'd0; reg sdram_cmd_payload_is_read = 1'd0; reg sdram_cmd_payload_is_write = 1'd0; wire sdram_wants_refresh; wire sdram_wants_zqcs; wire sdram_timer_wait; wire sdram_timer_done0; wire [9:0] sdram_timer_count0; wire sdram_timer_done1; reg [9:0] sdram_timer_count1 = 10'd624; wire sdram_postponer_req_i; reg sdram_postponer_req_o = 1'd0; reg sdram_postponer_count = 1'd0; reg sdram_sequencer_start0 = 1'd0; wire sdram_sequencer_done0; wire sdram_sequencer_start1; reg sdram_sequencer_done1 = 1'd0; reg [5:0] sdram_sequencer_counter = 6'd0; reg sdram_sequencer_count = 1'd0; wire sdram_zqcs_timer_wait; wire sdram_zqcs_timer_done0; wire [26:0] sdram_zqcs_timer_count0; wire sdram_zqcs_timer_done1; reg [26:0] sdram_zqcs_timer_count1 = 27'd79999999; reg sdram_zqcs_executer_start = 1'd0; reg sdram_zqcs_executer_done = 1'd0; reg [4:0] sdram_zqcs_executer_counter = 5'd0; wire sdram_bankmachine0_req_valid; wire sdram_bankmachine0_req_ready; wire sdram_bankmachine0_req_we; wire [20:0] sdram_bankmachine0_req_addr; wire sdram_bankmachine0_req_lock; reg sdram_bankmachine0_req_wdata_ready = 1'd0; reg sdram_bankmachine0_req_rdata_valid = 1'd0; wire sdram_bankmachine0_refresh_req; reg sdram_bankmachine0_refresh_gnt = 1'd0; reg sdram_bankmachine0_cmd_valid = 1'd0; reg sdram_bankmachine0_cmd_ready = 1'd0; reg [13:0] sdram_bankmachine0_cmd_payload_a = 14'd0; wire [2:0] sdram_bankmachine0_cmd_payload_ba; reg sdram_bankmachine0_cmd_payload_cas = 1'd0; reg sdram_bankmachine0_cmd_payload_ras = 1'd0; reg sdram_bankmachine0_cmd_payload_we = 1'd0; reg sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine0_cmd_payload_is_read = 1'd0; reg sdram_bankmachine0_cmd_payload_is_write = 1'd0; reg sdram_bankmachine0_auto_precharge = 1'd0; wire sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; wire [20:0] sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine0_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine0_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine0_cmd_buffer_lookahead_source_first; wire sdram_bankmachine0_cmd_buffer_lookahead_source_last; wire sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; wire [20:0] sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine0_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; wire [23:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; wire [20:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; wire [20:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine0_cmd_buffer_sink_valid; wire sdram_bankmachine0_cmd_buffer_sink_ready; wire sdram_bankmachine0_cmd_buffer_sink_first; wire sdram_bankmachine0_cmd_buffer_sink_last; wire sdram_bankmachine0_cmd_buffer_sink_payload_we; wire [20:0] sdram_bankmachine0_cmd_buffer_sink_payload_addr; reg sdram_bankmachine0_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine0_cmd_buffer_source_ready; reg sdram_bankmachine0_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine0_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; reg [20:0] sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; reg [13:0] sdram_bankmachine0_row = 14'd0; reg sdram_bankmachine0_row_opened = 1'd0; wire sdram_bankmachine0_row_hit; reg sdram_bankmachine0_row_open = 1'd0; reg sdram_bankmachine0_row_close = 1'd0; reg sdram_bankmachine0_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine0_twtpcon_valid; (* dont_touch = "true" *) reg sdram_bankmachine0_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine0_twtpcon_count = 3'd0; wire sdram_bankmachine0_trccon_valid; (* dont_touch = "true" *) reg sdram_bankmachine0_trccon_ready = 1'd0; reg [2:0] sdram_bankmachine0_trccon_count = 3'd0; wire sdram_bankmachine0_trascon_valid; (* dont_touch = "true" *) reg sdram_bankmachine0_trascon_ready = 1'd0; reg [1:0] sdram_bankmachine0_trascon_count = 2'd0; wire sdram_bankmachine1_req_valid; wire sdram_bankmachine1_req_ready; wire sdram_bankmachine1_req_we; wire [20:0] sdram_bankmachine1_req_addr; wire sdram_bankmachine1_req_lock; reg sdram_bankmachine1_req_wdata_ready = 1'd0; reg sdram_bankmachine1_req_rdata_valid = 1'd0; wire sdram_bankmachine1_refresh_req; reg sdram_bankmachine1_refresh_gnt = 1'd0; reg sdram_bankmachine1_cmd_valid = 1'd0; reg sdram_bankmachine1_cmd_ready = 1'd0; reg [13:0] sdram_bankmachine1_cmd_payload_a = 14'd0; wire [2:0] sdram_bankmachine1_cmd_payload_ba; reg sdram_bankmachine1_cmd_payload_cas = 1'd0; reg sdram_bankmachine1_cmd_payload_ras = 1'd0; reg sdram_bankmachine1_cmd_payload_we = 1'd0; reg sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine1_cmd_payload_is_read = 1'd0; reg sdram_bankmachine1_cmd_payload_is_write = 1'd0; reg sdram_bankmachine1_auto_precharge = 1'd0; wire sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; wire [20:0] sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine1_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine1_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine1_cmd_buffer_lookahead_source_first; wire sdram_bankmachine1_cmd_buffer_lookahead_source_last; wire sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; wire [20:0] sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; reg [3:0] sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine1_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; wire [23:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; wire [20:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; wire [20:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine1_cmd_buffer_sink_valid; wire sdram_bankmachine1_cmd_buffer_sink_ready; wire sdram_bankmachine1_cmd_buffer_sink_first; wire sdram_bankmachine1_cmd_buffer_sink_last; wire sdram_bankmachine1_cmd_buffer_sink_payload_we; wire [20:0] sdram_bankmachine1_cmd_buffer_sink_payload_addr; reg sdram_bankmachine1_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine1_cmd_buffer_source_ready; reg sdram_bankmachine1_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine1_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; reg [20:0] sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; reg [13:0] sdram_bankmachine1_row = 14'd0; reg sdram_bankmachine1_row_opened = 1'd0; wire sdram_bankmachine1_row_hit; reg sdram_bankmachine1_row_open = 1'd0; reg sdram_bankmachine1_row_close = 1'd0; reg sdram_bankmachine1_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine1_twtpcon_valid; (* dont_touch = "true" *) reg sdram_bankmachine1_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine1_twtpcon_count = 3'd0; wire sdram_bankmachine1_trccon_valid; (* dont_touch = "true" *) reg sdram_bankmachine1_trccon_ready = 1'd0; reg [2:0] sdram_bankmachine1_trccon_count = 3'd0; wire sdram_bankmachine1_trascon_valid; (* dont_touch = "true" *) reg sdram_bankmachine1_trascon_ready = 1'd0; reg [1:0] sdram_bankmachine1_trascon_count = 2'd0; wire sdram_bankmachine2_req_valid; wire sdram_bankmachine2_req_ready; wire sdram_bankmachine2_req_we; wire [20:0] sdram_bankmachine2_req_addr; wire sdram_bankmachine2_req_lock; reg sdram_bankmachine2_req_wdata_ready = 1'd0; reg sdram_bankmachine2_req_rdata_valid = 1'd0; wire sdram_bankmachine2_refresh_req; reg sdram_bankmachine2_refresh_gnt = 1'd0; reg sdram_bankmachine2_cmd_valid = 1'd0; reg sdram_bankmachine2_cmd_ready = 1'd0; reg [13:0] sdram_bankmachine2_cmd_payload_a = 14'd0; wire [2:0] sdram_bankmachine2_cmd_payload_ba; reg sdram_bankmachine2_cmd_payload_cas = 1'd0; reg sdram_bankmachine2_cmd_payload_ras = 1'd0; reg sdram_bankmachine2_cmd_payload_we = 1'd0; reg sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine2_cmd_payload_is_read = 1'd0; reg sdram_bankmachine2_cmd_payload_is_write = 1'd0; reg sdram_bankmachine2_auto_precharge = 1'd0; wire sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; wire [20:0] sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine2_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine2_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine2_cmd_buffer_lookahead_source_first; wire sdram_bankmachine2_cmd_buffer_lookahead_source_last; wire sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; wire [20:0] sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; reg [3:0] sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine2_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; wire [23:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; wire [20:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; wire [20:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine2_cmd_buffer_sink_valid; wire sdram_bankmachine2_cmd_buffer_sink_ready; wire sdram_bankmachine2_cmd_buffer_sink_first; wire sdram_bankmachine2_cmd_buffer_sink_last; wire sdram_bankmachine2_cmd_buffer_sink_payload_we; wire [20:0] sdram_bankmachine2_cmd_buffer_sink_payload_addr; reg sdram_bankmachine2_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine2_cmd_buffer_source_ready; reg sdram_bankmachine2_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine2_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; reg [20:0] sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; reg [13:0] sdram_bankmachine2_row = 14'd0; reg sdram_bankmachine2_row_opened = 1'd0; wire sdram_bankmachine2_row_hit; reg sdram_bankmachine2_row_open = 1'd0; reg sdram_bankmachine2_row_close = 1'd0; reg sdram_bankmachine2_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine2_twtpcon_valid; (* dont_touch = "true" *) reg sdram_bankmachine2_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine2_twtpcon_count = 3'd0; wire sdram_bankmachine2_trccon_valid; (* dont_touch = "true" *) reg sdram_bankmachine2_trccon_ready = 1'd0; reg [2:0] sdram_bankmachine2_trccon_count = 3'd0; wire sdram_bankmachine2_trascon_valid; (* dont_touch = "true" *) reg sdram_bankmachine2_trascon_ready = 1'd0; reg [1:0] sdram_bankmachine2_trascon_count = 2'd0; wire sdram_bankmachine3_req_valid; wire sdram_bankmachine3_req_ready; wire sdram_bankmachine3_req_we; wire [20:0] sdram_bankmachine3_req_addr; wire sdram_bankmachine3_req_lock; reg sdram_bankmachine3_req_wdata_ready = 1'd0; reg sdram_bankmachine3_req_rdata_valid = 1'd0; wire sdram_bankmachine3_refresh_req; reg sdram_bankmachine3_refresh_gnt = 1'd0; reg sdram_bankmachine3_cmd_valid = 1'd0; reg sdram_bankmachine3_cmd_ready = 1'd0; reg [13:0] sdram_bankmachine3_cmd_payload_a = 14'd0; wire [2:0] sdram_bankmachine3_cmd_payload_ba; reg sdram_bankmachine3_cmd_payload_cas = 1'd0; reg sdram_bankmachine3_cmd_payload_ras = 1'd0; reg sdram_bankmachine3_cmd_payload_we = 1'd0; reg sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine3_cmd_payload_is_read = 1'd0; reg sdram_bankmachine3_cmd_payload_is_write = 1'd0; reg sdram_bankmachine3_auto_precharge = 1'd0; wire sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; wire [20:0] sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine3_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine3_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine3_cmd_buffer_lookahead_source_first; wire sdram_bankmachine3_cmd_buffer_lookahead_source_last; wire sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; wire [20:0] sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; reg [3:0] sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine3_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; wire [23:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; wire [20:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; wire [20:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine3_cmd_buffer_sink_valid; wire sdram_bankmachine3_cmd_buffer_sink_ready; wire sdram_bankmachine3_cmd_buffer_sink_first; wire sdram_bankmachine3_cmd_buffer_sink_last; wire sdram_bankmachine3_cmd_buffer_sink_payload_we; wire [20:0] sdram_bankmachine3_cmd_buffer_sink_payload_addr; reg sdram_bankmachine3_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine3_cmd_buffer_source_ready; reg sdram_bankmachine3_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine3_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; reg [20:0] sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; reg [13:0] sdram_bankmachine3_row = 14'd0; reg sdram_bankmachine3_row_opened = 1'd0; wire sdram_bankmachine3_row_hit; reg sdram_bankmachine3_row_open = 1'd0; reg sdram_bankmachine3_row_close = 1'd0; reg sdram_bankmachine3_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine3_twtpcon_valid; (* dont_touch = "true" *) reg sdram_bankmachine3_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine3_twtpcon_count = 3'd0; wire sdram_bankmachine3_trccon_valid; (* dont_touch = "true" *) reg sdram_bankmachine3_trccon_ready = 1'd0; reg [2:0] sdram_bankmachine3_trccon_count = 3'd0; wire sdram_bankmachine3_trascon_valid; (* dont_touch = "true" *) reg sdram_bankmachine3_trascon_ready = 1'd0; reg [1:0] sdram_bankmachine3_trascon_count = 2'd0; wire sdram_bankmachine4_req_valid; wire sdram_bankmachine4_req_ready; wire sdram_bankmachine4_req_we; wire [20:0] sdram_bankmachine4_req_addr; wire sdram_bankmachine4_req_lock; reg sdram_bankmachine4_req_wdata_ready = 1'd0; reg sdram_bankmachine4_req_rdata_valid = 1'd0; wire sdram_bankmachine4_refresh_req; reg sdram_bankmachine4_refresh_gnt = 1'd0; reg sdram_bankmachine4_cmd_valid = 1'd0; reg sdram_bankmachine4_cmd_ready = 1'd0; reg [13:0] sdram_bankmachine4_cmd_payload_a = 14'd0; wire [2:0] sdram_bankmachine4_cmd_payload_ba; reg sdram_bankmachine4_cmd_payload_cas = 1'd0; reg sdram_bankmachine4_cmd_payload_ras = 1'd0; reg sdram_bankmachine4_cmd_payload_we = 1'd0; reg sdram_bankmachine4_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine4_cmd_payload_is_read = 1'd0; reg sdram_bankmachine4_cmd_payload_is_write = 1'd0; reg sdram_bankmachine4_auto_precharge = 1'd0; wire sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; wire [20:0] sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine4_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine4_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine4_cmd_buffer_lookahead_source_first; wire sdram_bankmachine4_cmd_buffer_lookahead_source_last; wire sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; wire [20:0] sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; wire sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; wire sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; wire sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; reg [3:0] sdram_bankmachine4_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine4_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine4_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine4_cmd_buffer_lookahead_wrport_we; wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine4_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr; wire [23:0] sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; wire [20:0] sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; wire [20:0] sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine4_cmd_buffer_sink_valid; wire sdram_bankmachine4_cmd_buffer_sink_ready; wire sdram_bankmachine4_cmd_buffer_sink_first; wire sdram_bankmachine4_cmd_buffer_sink_last; wire sdram_bankmachine4_cmd_buffer_sink_payload_we; wire [20:0] sdram_bankmachine4_cmd_buffer_sink_payload_addr; reg sdram_bankmachine4_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine4_cmd_buffer_source_ready; reg sdram_bankmachine4_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine4_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0; reg [20:0] sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; reg [13:0] sdram_bankmachine4_row = 14'd0; reg sdram_bankmachine4_row_opened = 1'd0; wire sdram_bankmachine4_row_hit; reg sdram_bankmachine4_row_open = 1'd0; reg sdram_bankmachine4_row_close = 1'd0; reg sdram_bankmachine4_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine4_twtpcon_valid; (* dont_touch = "true" *) reg sdram_bankmachine4_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine4_twtpcon_count = 3'd0; wire sdram_bankmachine4_trccon_valid; (* dont_touch = "true" *) reg sdram_bankmachine4_trccon_ready = 1'd0; reg [2:0] sdram_bankmachine4_trccon_count = 3'd0; wire sdram_bankmachine4_trascon_valid; (* dont_touch = "true" *) reg sdram_bankmachine4_trascon_ready = 1'd0; reg [1:0] sdram_bankmachine4_trascon_count = 2'd0; wire sdram_bankmachine5_req_valid; wire sdram_bankmachine5_req_ready; wire sdram_bankmachine5_req_we; wire [20:0] sdram_bankmachine5_req_addr; wire sdram_bankmachine5_req_lock; reg sdram_bankmachine5_req_wdata_ready = 1'd0; reg sdram_bankmachine5_req_rdata_valid = 1'd0; wire sdram_bankmachine5_refresh_req; reg sdram_bankmachine5_refresh_gnt = 1'd0; reg sdram_bankmachine5_cmd_valid = 1'd0; reg sdram_bankmachine5_cmd_ready = 1'd0; reg [13:0] sdram_bankmachine5_cmd_payload_a = 14'd0; wire [2:0] sdram_bankmachine5_cmd_payload_ba; reg sdram_bankmachine5_cmd_payload_cas = 1'd0; reg sdram_bankmachine5_cmd_payload_ras = 1'd0; reg sdram_bankmachine5_cmd_payload_we = 1'd0; reg sdram_bankmachine5_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine5_cmd_payload_is_read = 1'd0; reg sdram_bankmachine5_cmd_payload_is_write = 1'd0; reg sdram_bankmachine5_auto_precharge = 1'd0; wire sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; wire [20:0] sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine5_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine5_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine5_cmd_buffer_lookahead_source_first; wire sdram_bankmachine5_cmd_buffer_lookahead_source_last; wire sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; wire [20:0] sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; wire sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; wire sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; wire sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; reg [3:0] sdram_bankmachine5_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine5_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine5_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine5_cmd_buffer_lookahead_wrport_we; wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine5_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr; wire [23:0] sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; wire [20:0] sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; wire [20:0] sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine5_cmd_buffer_sink_valid; wire sdram_bankmachine5_cmd_buffer_sink_ready; wire sdram_bankmachine5_cmd_buffer_sink_first; wire sdram_bankmachine5_cmd_buffer_sink_last; wire sdram_bankmachine5_cmd_buffer_sink_payload_we; wire [20:0] sdram_bankmachine5_cmd_buffer_sink_payload_addr; reg sdram_bankmachine5_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine5_cmd_buffer_source_ready; reg sdram_bankmachine5_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine5_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0; reg [20:0] sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; reg [13:0] sdram_bankmachine5_row = 14'd0; reg sdram_bankmachine5_row_opened = 1'd0; wire sdram_bankmachine5_row_hit; reg sdram_bankmachine5_row_open = 1'd0; reg sdram_bankmachine5_row_close = 1'd0; reg sdram_bankmachine5_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine5_twtpcon_valid; (* dont_touch = "true" *) reg sdram_bankmachine5_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine5_twtpcon_count = 3'd0; wire sdram_bankmachine5_trccon_valid; (* dont_touch = "true" *) reg sdram_bankmachine5_trccon_ready = 1'd0; reg [2:0] sdram_bankmachine5_trccon_count = 3'd0; wire sdram_bankmachine5_trascon_valid; (* dont_touch = "true" *) reg sdram_bankmachine5_trascon_ready = 1'd0; reg [1:0] sdram_bankmachine5_trascon_count = 2'd0; wire sdram_bankmachine6_req_valid; wire sdram_bankmachine6_req_ready; wire sdram_bankmachine6_req_we; wire [20:0] sdram_bankmachine6_req_addr; wire sdram_bankmachine6_req_lock; reg sdram_bankmachine6_req_wdata_ready = 1'd0; reg sdram_bankmachine6_req_rdata_valid = 1'd0; wire sdram_bankmachine6_refresh_req; reg sdram_bankmachine6_refresh_gnt = 1'd0; reg sdram_bankmachine6_cmd_valid = 1'd0; reg sdram_bankmachine6_cmd_ready = 1'd0; reg [13:0] sdram_bankmachine6_cmd_payload_a = 14'd0; wire [2:0] sdram_bankmachine6_cmd_payload_ba; reg sdram_bankmachine6_cmd_payload_cas = 1'd0; reg sdram_bankmachine6_cmd_payload_ras = 1'd0; reg sdram_bankmachine6_cmd_payload_we = 1'd0; reg sdram_bankmachine6_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine6_cmd_payload_is_read = 1'd0; reg sdram_bankmachine6_cmd_payload_is_write = 1'd0; reg sdram_bankmachine6_auto_precharge = 1'd0; wire sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; wire [20:0] sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine6_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine6_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine6_cmd_buffer_lookahead_source_first; wire sdram_bankmachine6_cmd_buffer_lookahead_source_last; wire sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; wire [20:0] sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; wire sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; wire sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; wire sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; reg [3:0] sdram_bankmachine6_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine6_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine6_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine6_cmd_buffer_lookahead_wrport_we; wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine6_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr; wire [23:0] sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; wire [20:0] sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; wire [20:0] sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine6_cmd_buffer_sink_valid; wire sdram_bankmachine6_cmd_buffer_sink_ready; wire sdram_bankmachine6_cmd_buffer_sink_first; wire sdram_bankmachine6_cmd_buffer_sink_last; wire sdram_bankmachine6_cmd_buffer_sink_payload_we; wire [20:0] sdram_bankmachine6_cmd_buffer_sink_payload_addr; reg sdram_bankmachine6_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine6_cmd_buffer_source_ready; reg sdram_bankmachine6_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine6_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0; reg [20:0] sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; reg [13:0] sdram_bankmachine6_row = 14'd0; reg sdram_bankmachine6_row_opened = 1'd0; wire sdram_bankmachine6_row_hit; reg sdram_bankmachine6_row_open = 1'd0; reg sdram_bankmachine6_row_close = 1'd0; reg sdram_bankmachine6_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine6_twtpcon_valid; (* dont_touch = "true" *) reg sdram_bankmachine6_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine6_twtpcon_count = 3'd0; wire sdram_bankmachine6_trccon_valid; (* dont_touch = "true" *) reg sdram_bankmachine6_trccon_ready = 1'd0; reg [2:0] sdram_bankmachine6_trccon_count = 3'd0; wire sdram_bankmachine6_trascon_valid; (* dont_touch = "true" *) reg sdram_bankmachine6_trascon_ready = 1'd0; reg [1:0] sdram_bankmachine6_trascon_count = 2'd0; wire sdram_bankmachine7_req_valid; wire sdram_bankmachine7_req_ready; wire sdram_bankmachine7_req_we; wire [20:0] sdram_bankmachine7_req_addr; wire sdram_bankmachine7_req_lock; reg sdram_bankmachine7_req_wdata_ready = 1'd0; reg sdram_bankmachine7_req_rdata_valid = 1'd0; wire sdram_bankmachine7_refresh_req; reg sdram_bankmachine7_refresh_gnt = 1'd0; reg sdram_bankmachine7_cmd_valid = 1'd0; reg sdram_bankmachine7_cmd_ready = 1'd0; reg [13:0] sdram_bankmachine7_cmd_payload_a = 14'd0; wire [2:0] sdram_bankmachine7_cmd_payload_ba; reg sdram_bankmachine7_cmd_payload_cas = 1'd0; reg sdram_bankmachine7_cmd_payload_ras = 1'd0; reg sdram_bankmachine7_cmd_payload_we = 1'd0; reg sdram_bankmachine7_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine7_cmd_payload_is_read = 1'd0; reg sdram_bankmachine7_cmd_payload_is_write = 1'd0; reg sdram_bankmachine7_auto_precharge = 1'd0; wire sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; wire [20:0] sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine7_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine7_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine7_cmd_buffer_lookahead_source_first; wire sdram_bankmachine7_cmd_buffer_lookahead_source_last; wire sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; wire [20:0] sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; wire sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; wire sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; wire sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; reg [3:0] sdram_bankmachine7_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine7_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine7_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine7_cmd_buffer_lookahead_wrport_we; wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine7_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr; wire [23:0] sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; wire [20:0] sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; wire [20:0] sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine7_cmd_buffer_sink_valid; wire sdram_bankmachine7_cmd_buffer_sink_ready; wire sdram_bankmachine7_cmd_buffer_sink_first; wire sdram_bankmachine7_cmd_buffer_sink_last; wire sdram_bankmachine7_cmd_buffer_sink_payload_we; wire [20:0] sdram_bankmachine7_cmd_buffer_sink_payload_addr; reg sdram_bankmachine7_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine7_cmd_buffer_source_ready; reg sdram_bankmachine7_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine7_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0; reg [20:0] sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; reg [13:0] sdram_bankmachine7_row = 14'd0; reg sdram_bankmachine7_row_opened = 1'd0; wire sdram_bankmachine7_row_hit; reg sdram_bankmachine7_row_open = 1'd0; reg sdram_bankmachine7_row_close = 1'd0; reg sdram_bankmachine7_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine7_twtpcon_valid; (* dont_touch = "true" *) reg sdram_bankmachine7_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine7_twtpcon_count = 3'd0; wire sdram_bankmachine7_trccon_valid; (* dont_touch = "true" *) reg sdram_bankmachine7_trccon_ready = 1'd0; reg [2:0] sdram_bankmachine7_trccon_count = 3'd0; wire sdram_bankmachine7_trascon_valid; (* dont_touch = "true" *) reg sdram_bankmachine7_trascon_ready = 1'd0; reg [1:0] sdram_bankmachine7_trascon_count = 2'd0; wire sdram_ras_allowed; wire sdram_cas_allowed; wire [1:0] sdram_rdcmdphase; wire [1:0] sdram_wrcmdphase; reg sdram_choose_cmd_want_reads = 1'd0; reg sdram_choose_cmd_want_writes = 1'd0; reg sdram_choose_cmd_want_cmds = 1'd0; reg sdram_choose_cmd_want_activates = 1'd0; wire sdram_choose_cmd_cmd_valid; reg sdram_choose_cmd_cmd_ready = 1'd0; wire [13:0] sdram_choose_cmd_cmd_payload_a; wire [2:0] sdram_choose_cmd_cmd_payload_ba; reg sdram_choose_cmd_cmd_payload_cas = 1'd0; reg sdram_choose_cmd_cmd_payload_ras = 1'd0; reg sdram_choose_cmd_cmd_payload_we = 1'd0; wire sdram_choose_cmd_cmd_payload_is_cmd; wire sdram_choose_cmd_cmd_payload_is_read; wire sdram_choose_cmd_cmd_payload_is_write; reg [7:0] sdram_choose_cmd_valids = 8'd0; wire [7:0] sdram_choose_cmd_request; reg [2:0] sdram_choose_cmd_grant = 3'd0; wire sdram_choose_cmd_ce; reg sdram_choose_req_want_reads = 1'd0; reg sdram_choose_req_want_writes = 1'd0; reg sdram_choose_req_want_cmds = 1'd0; reg sdram_choose_req_want_activates = 1'd0; wire sdram_choose_req_cmd_valid; reg sdram_choose_req_cmd_ready = 1'd0; wire [13:0] sdram_choose_req_cmd_payload_a; wire [2:0] sdram_choose_req_cmd_payload_ba; reg sdram_choose_req_cmd_payload_cas = 1'd0; reg sdram_choose_req_cmd_payload_ras = 1'd0; reg sdram_choose_req_cmd_payload_we = 1'd0; wire sdram_choose_req_cmd_payload_is_cmd; wire sdram_choose_req_cmd_payload_is_read; wire sdram_choose_req_cmd_payload_is_write; reg [7:0] sdram_choose_req_valids = 8'd0; wire [7:0] sdram_choose_req_request; reg [2:0] sdram_choose_req_grant = 3'd0; wire sdram_choose_req_ce; reg [13:0] sdram_nop_a = 14'd0; reg [2:0] sdram_nop_ba = 3'd0; reg [1:0] sdram_steerer_sel0 = 2'd0; reg [1:0] sdram_steerer_sel1 = 2'd0; reg [1:0] sdram_steerer_sel2 = 2'd0; reg [1:0] sdram_steerer_sel3 = 2'd0; reg sdram_steerer0 = 1'd1; reg sdram_steerer1 = 1'd1; reg sdram_steerer2 = 1'd1; reg sdram_steerer3 = 1'd1; reg sdram_steerer4 = 1'd1; reg sdram_steerer5 = 1'd1; reg sdram_steerer6 = 1'd1; reg sdram_steerer7 = 1'd1; wire sdram_trrdcon_valid; (* dont_touch = "true" *) reg sdram_trrdcon_ready = 1'd0; reg sdram_trrdcon_count = 1'd0; wire sdram_tfawcon_valid; (* dont_touch = "true" *) reg sdram_tfawcon_ready = 1'd1; wire [1:0] sdram_tfawcon_count; reg [3:0] sdram_tfawcon_window = 4'd0; wire sdram_tccdcon_valid; (* dont_touch = "true" *) reg sdram_tccdcon_ready = 1'd0; reg sdram_tccdcon_count = 1'd0; wire sdram_twtrcon_valid; (* dont_touch = "true" *) reg sdram_twtrcon_ready = 1'd0; reg [2:0] sdram_twtrcon_count = 3'd0; wire sdram_read_available; wire sdram_write_available; reg sdram_en0 = 1'd0; wire sdram_max_time0; reg [4:0] sdram_time0 = 5'd0; reg sdram_en1 = 1'd0; wire sdram_max_time1; reg [3:0] sdram_time1 = 4'd0; wire sdram_go_to_refresh; wire port_flush; wire port_cmd_valid; wire port_cmd_ready; wire port_cmd_last; wire port_cmd_payload_we; wire [23:0] port_cmd_payload_addr; wire port_wdata_valid; wire port_wdata_ready; wire [127:0] port_wdata_payload_data; wire [15:0] port_wdata_payload_we; wire port_rdata_valid; wire port_rdata_ready; wire [127:0] port_rdata_payload_data; wire [29:0] wb_sdram_adr; wire [31:0] wb_sdram_dat_w; reg [31:0] wb_sdram_dat_r = 32'd0; wire [3:0] wb_sdram_sel; wire wb_sdram_cyc; wire wb_sdram_stb; reg wb_sdram_ack = 1'd0; wire wb_sdram_we; wire [2:0] wb_sdram_cti; wire [1:0] wb_sdram_bte; reg wb_sdram_err = 1'd0; wire [29:0] interface_adr; wire [127:0] interface_dat_w; wire [127:0] interface_dat_r; wire [15:0] interface_sel; reg interface_cyc = 1'd0; reg interface_stb = 1'd0; wire interface_ack; reg interface_we = 1'd0; wire [8:0] data_port_adr; wire [127:0] data_port_dat_r; reg [15:0] data_port_we = 16'd0; reg [127:0] data_port_dat_w = 128'd0; reg write_from_slave = 1'd0; reg [1:0] adr_offset_r = 2'd0; wire [8:0] tag_port_adr; wire [23:0] tag_port_dat_r; reg tag_port_we = 1'd0; wire [23:0] tag_port_dat_w; wire [22:0] tag_do_tag; wire tag_do_dirty; wire [22:0] tag_di_tag; reg tag_di_dirty = 1'd0; reg word_clr = 1'd0; reg word_inc = 1'd0; reg cmd_consumed = 1'd0; reg wdata_consumed = 1'd0; wire ack_cmd; wire ack_wdata; wire ack_rdata; wire enable; wire ready; wire a7litesataphy_ready; reg a7litesataphy_tx_idle = 1'd0; reg a7litesataphy_tx_polarity = 1'd0; reg a7litesataphy_tx_cominit_stb = 1'd0; wire a7litesataphy_tx_cominit_ack; reg a7litesataphy_tx_comwake_stb = 1'd0; wire a7litesataphy_tx_comwake_ack; reg a7litesataphy_rx_idle = 1'd0; reg a7litesataphy_rx_cdrhold = 1'd0; reg a7litesataphy_rx_polarity = 1'd0; wire a7litesataphy_rx_cominit_stb; wire a7litesataphy_rx_comwake_stb; wire [1:0] a7litesataphy_rxdisperr0; wire [1:0] a7litesataphy_rxnotintable0; wire a7litesataphy_sink_valid; reg a7litesataphy_sink_ready = 1'd0; wire a7litesataphy_sink_first; wire a7litesataphy_sink_last; wire [15:0] a7litesataphy_sink_payload_data; wire [1:0] a7litesataphy_sink_payload_charisk; reg a7litesataphy_source_valid = 1'd0; wire a7litesataphy_source_ready; reg a7litesataphy_source_first = 1'd0; reg a7litesataphy_source_last = 1'd0; reg [15:0] a7litesataphy_source_payload_data = 16'd0; reg [1:0] a7litesataphy_source_payload_charisk = 2'd0; wire a7litesataphy_gtrefclk0; wire a7litesataphy_qplllock; wire [1:0] a7litesataphy_rxcharisk; wire [15:0] a7litesataphy_rxdata; wire a7litesataphy_rxoutclk; wire a7litesataphy_rxusrclk; wire a7litesataphy_rxusrclk2; wire a7litesataphy_rxcominitdet0; wire a7litesataphy_rxcomwakedet0; reg [1:0] a7litesataphy_txcharisk = 2'd0; reg [15:0] a7litesataphy_txdata = 16'd0; wire a7litesataphy_txoutclk; wire a7litesataphy_txusrclk; wire a7litesataphy_txusrclk2; wire a7litesataphy_txelecidle0; wire a7litesataphy_txcomfinish0; wire a7litesataphy_txcominit0; wire a7litesataphy_txcomwake0; reg a7litesataphy_rxpd = 1'd0; reg a7litesataphy_txpd0 = 1'd0; reg a7litesataphy_tx_init_done = 1'd0; wire a7litesataphy_tx_init_restart; wire a7litesataphy_tx_init_plllock0; reg a7litesataphy_tx_init_pllreset = 1'd0; reg a7litesataphy_tx_init_gttxreset0 = 1'd0; reg a7litesataphy_tx_init_gttxpd0 = 1'd0; wire a7litesataphy_tx_init_txresetdone0; reg a7litesataphy_tx_init_txdlysreset0 = 1'd0; wire a7litesataphy_tx_init_txdlysresetdone0; reg a7litesataphy_tx_init_txphinit0 = 1'd0; wire a7litesataphy_tx_init_txphinitdone0; reg a7litesataphy_tx_init_txphalign0 = 1'd0; wire a7litesataphy_tx_init_txphaligndone0; reg a7litesataphy_tx_init_txdlyen0 = 1'd0; reg a7litesataphy_tx_init_txuserrdy0 = 1'd0; reg a7litesataphy_tx_init_drp_start = 1'd0; reg a7litesataphy_tx_init_drp_done = 1'd1; wire a7litesataphy_tx_init_plllock1; wire a7litesataphy_tx_init_txresetdone1; wire a7litesataphy_tx_init_txdlysresetdone1; wire a7litesataphy_tx_init_txphinitdone1; wire a7litesataphy_tx_init_txphaligndone1; reg a7litesataphy_tx_init_gttxreset1 = 1'd0; reg a7litesataphy_tx_init_gttxpd1 = 1'd0; reg a7litesataphy_tx_init_txdlysreset1 = 1'd0; reg a7litesataphy_tx_init_txphinit1 = 1'd0; reg a7litesataphy_tx_init_txphalign1 = 1'd0; reg a7litesataphy_tx_init_txdlyen1 = 1'd0; reg a7litesataphy_tx_init_txuserrdy1 = 1'd0; reg a7litesataphy_tx_init_txphaligndone_r = 1'd1; wire a7litesataphy_tx_init_txphaligndone_rising; wire a7litesataphy_tx_init_reset; wire a7litesataphy_tx_init_init_delay_wait; wire a7litesataphy_tx_init_init_delay_done; reg [5:0] a7litesataphy_tx_init_init_delay_count = 6'd40; wire a7litesataphy_tx_init_watchdog_wait; wire a7litesataphy_tx_init_watchdog_done; reg [16:0] a7litesataphy_tx_init_watchdog_count = 17'd80000; reg a7litesataphy_rx_init_done = 1'd0; wire a7litesataphy_rx_init_restart; wire a7litesataphy_rx_init_plllock0; reg a7litesataphy_rx_init_gtrxreset0 = 1'd0; reg a7litesataphy_rx_init_gtrxpd0 = 1'd0; wire a7litesataphy_rx_init_rxresetdone0; reg a7litesataphy_rx_init_rxdlysreset0 = 1'd0; wire a7litesataphy_rx_init_rxdlysresetdone0; reg a7litesataphy_rx_init_rxphalign0 = 1'd0; reg a7litesataphy_rx_init_rxuserrdy0 = 1'd0; wire a7litesataphy_rx_init_rxsyncdone0; wire a7litesataphy_rx_init_rxpmaresetdone0; wire a7litesataphy_rx_init_drp_clk; reg a7litesataphy_rx_init_drp_en = 1'd0; reg a7litesataphy_rx_init_drp_we = 1'd0; wire a7litesataphy_rx_init_drp_rdy; wire [8:0] a7litesataphy_rx_init_drp_addr; reg [15:0] a7litesataphy_rx_init_drp_di = 16'd0; wire [15:0] a7litesataphy_rx_init_drp_do; reg [15:0] a7litesataphy_rx_init_drpvalue = 16'd0; reg a7litesataphy_rx_init_drpmask = 1'd0; wire a7litesataphy_rx_init_rxpmaresetdone1; reg a7litesataphy_rx_init_rxpmaresetdone_r = 1'd0; wire a7litesataphy_rx_init_plllock1; wire a7litesataphy_rx_init_rxresetdone1; wire a7litesataphy_rx_init_rxdlysresetdone1; wire a7litesataphy_rx_init_rxsyncdone1; reg a7litesataphy_rx_init_gtrxreset1 = 1'd0; reg a7litesataphy_rx_init_gtrxpd1 = 1'd0; reg a7litesataphy_rx_init_rxdlysreset1 = 1'd0; reg a7litesataphy_rx_init_rxphalign1 = 1'd0; reg a7litesataphy_rx_init_rxuserrdy1 = 1'd0; wire a7litesataphy_rx_init_reset; wire a7litesataphy_rx_init_init_delay_wait; wire a7litesataphy_rx_init_init_delay_done; reg [5:0] a7litesataphy_rx_init_init_delay_count = 6'd40; wire a7litesataphy_rx_init_watchdog_wait; wire a7litesataphy_rx_init_watchdog_done; reg [18:0] a7litesataphy_rx_init_watchdog_count = 19'd320000; reg a7litesataphy_i_d0 = 1'd0; reg a7litesataphy_i_d1 = 1'd0; wire a7litesataphy_txpd1; wire a7litesataphy_txelecidle1; wire a7litesataphy_txcominit1; wire a7litesataphy_txcomwake1; wire a7litesataphy_pulsesynchronizer0_i; wire a7litesataphy_pulsesynchronizer0_o; reg a7litesataphy_pulsesynchronizer0_toggle_i = 1'd0; wire a7litesataphy_pulsesynchronizer0_toggle_o; reg a7litesataphy_pulsesynchronizer0_toggle_o_r = 1'd0; wire a7litesataphy_pulsesynchronizer1_i; wire a7litesataphy_pulsesynchronizer1_o; reg a7litesataphy_pulsesynchronizer1_toggle_i = 1'd0; wire a7litesataphy_pulsesynchronizer1_toggle_o; reg a7litesataphy_pulsesynchronizer1_toggle_o_r = 1'd0; wire a7litesataphy_txcomfinish1; wire a7litesataphy_pulsesynchronizer2_i; wire a7litesataphy_pulsesynchronizer2_o; reg a7litesataphy_pulsesynchronizer2_toggle_i = 1'd0; wire a7litesataphy_pulsesynchronizer2_toggle_o; reg a7litesataphy_pulsesynchronizer2_toggle_o_r = 1'd0; wire a7litesataphy_rxcominitdet1; wire a7litesataphy_rxcomwakedet1; wire [1:0] a7litesataphy_rxdisperr1; wire [1:0] a7litesataphy_rxnotintable1; wire a7litesataphy_qpll_clk; wire a7litesataphy_qpll_refclk; wire a7litesataphy_qpll_reset; wire a7litesataphy_qpll_lock; reg a7litesataphy_qpll_drp_clk = 1'd0; reg a7litesataphy_qpll_drp_en = 1'd0; reg a7litesataphy_qpll_drp_we = 1'd0; wire a7litesataphy_qpll_drp_rdy; reg [8:0] a7litesataphy_qpll_drp_addr = 9'd0; reg [15:0] a7litesataphy_qpll_drp_di = 16'd0; wire [15:0] a7litesataphy_qpll_drp_do; wire a7litesataphy_oobclk; wire a7litesataphy_rxphaligndone; wire a7litesataphy0; wire a7litesataphy1; wire a7litesataphy2; wire a7litesataphy3; wire a7litesataphy4; wire a7litesataphy5; wire a7litesataphy6; wire a7litesataphy7; wire a7litesataphy8; wire a7litesataphy9; wire a7litesataphy10; wire a7litesataphy11; wire a7litesataphy12; wire a7litesataphy13; wire a7litesataphy14; wire a7litesataphy15; wire a7litesataphy16; wire a7litesataphy17; wire a7litesataphy18; wire a7litesataphy19; wire a7litesataphy20; wire a7litesataphy21; wire a7litesataphy22; wire a7litesataphy23; wire a7litesataphy24; wire a7litesataphy25; wire a7litesataphy26; wire a7litesataphy27; wire a7litesataphy28; wire a7litesataphy29; wire a7litesataphy30; wire a7litesataphy31; wire a7litesataphy32; wire a7litesataphy33; wire a7litesataphy34; wire a7litesataphy35; wire a7litesataphy36; wire a7litesataphy37; wire a7litesataphy38; wire a7litesataphy39; wire a7litesataphy40; wire a7litesataphy41; wire a7litesataphy42; reg crg_tx_reset = 1'd0; reg crg_rx_reset = 1'd0; (* dont_touch = "true" *) wire sata_tx_clk; wire sata_tx_rst; (* dont_touch = "true" *) wire sata_rx_clk; wire sata_rx_rst; wire crg_refclk; reg ctrl_ready = 1'd0; wire ctrl_sink_valid; wire ctrl_sink_ready; wire ctrl_sink_first; wire ctrl_sink_last; wire [31:0] ctrl_sink_payload_data; wire [3:0] ctrl_sink_payload_charisk; wire ctrl_source_valid; wire ctrl_source_ready; reg ctrl_source_first = 1'd0; reg ctrl_source_last = 1'd0; reg [31:0] ctrl_source_payload_data = 32'd0; reg [3:0] ctrl_source_payload_charisk = 4'd0; wire ctrl_misalign; reg ctrl_tx_idle = 1'd0; reg ctrl_rx_reset = 1'd0; reg ctrl_tx_reset = 1'd0; wire ctrl_rx_idle; reg ctrl_retry_timer_wait = 1'd0; wire ctrl_retry_timer_done; reg [19:0] ctrl_retry_timer_count = 20'd800000; reg ctrl_align_timer_wait = 1'd0; wire ctrl_align_timer_done; reg [16:0] ctrl_align_timer_count = 17'd69840; reg [3:0] ctrl_align_count = 4'd0; wire ctrl_reset; reg ctrl_stability_timer_wait = 1'd0; wire ctrl_stability_timer_done; reg [18:0] ctrl_stability_timer_count = 19'd400000; wire datapath_sink_sink_valid; wire datapath_sink_sink_ready; wire datapath_sink_sink_first; wire datapath_sink_sink_last; wire [31:0] datapath_sink_sink_payload_data; wire [3:0] datapath_sink_sink_payload_charisk; wire datapath_source_source_valid; wire datapath_source_source_ready; wire datapath_source_source_first; wire datapath_source_source_last; wire [31:0] datapath_source_source_payload_data; wire [3:0] datapath_source_source_payload_charisk; wire datapath_misalign; wire datapath_rx_idle; reg datapath_mux_source_valid = 1'd0; wire datapath_mux_source_ready; reg datapath_mux_source_first = 1'd0; reg datapath_mux_source_last = 1'd0; reg [31:0] datapath_mux_source_payload_data = 32'd0; reg [3:0] datapath_mux_source_payload_charisk = 4'd0; wire datapath_mux_endpoint0_sink_valid; reg datapath_mux_endpoint0_sink_ready = 1'd0; wire datapath_mux_endpoint0_sink_first; wire datapath_mux_endpoint0_sink_last; wire [31:0] datapath_mux_endpoint0_sink_payload_data; wire [3:0] datapath_mux_endpoint0_sink_payload_charisk; wire datapath_mux_endpoint1_sink_valid; reg datapath_mux_endpoint1_sink_ready = 1'd0; wire datapath_mux_endpoint1_sink_first; wire datapath_mux_endpoint1_sink_last; wire [31:0] datapath_mux_endpoint1_sink_payload_data; wire [3:0] datapath_mux_endpoint1_sink_payload_charisk; wire datapath_mux_sel; wire datapath_tx_sink_sink_valid; wire datapath_tx_sink_sink_ready; wire datapath_tx_sink_sink_first; wire datapath_tx_sink_sink_last; wire [31:0] datapath_tx_sink_sink_payload_data; wire [3:0] datapath_tx_sink_sink_payload_charisk; wire datapath_tx_source_source_valid; wire datapath_tx_source_source_ready; wire datapath_tx_source_source_first; wire datapath_tx_source_source_last; wire [15:0] datapath_tx_source_source_payload_data; wire [1:0] datapath_tx_source_source_payload_charisk; wire datapath_tx_fifo_sink_valid; wire datapath_tx_fifo_sink_ready; wire datapath_tx_fifo_sink_first; wire datapath_tx_fifo_sink_last; wire [31:0] datapath_tx_fifo_sink_payload_data; wire [3:0] datapath_tx_fifo_sink_payload_charisk; wire datapath_tx_fifo_source_valid; wire datapath_tx_fifo_source_ready; wire datapath_tx_fifo_source_first; wire datapath_tx_fifo_source_last; wire [31:0] datapath_tx_fifo_source_payload_data; wire [3:0] datapath_tx_fifo_source_payload_charisk; wire datapath_tx_fifo_asyncfifo_we; wire datapath_tx_fifo_asyncfifo_writable; wire datapath_tx_fifo_asyncfifo_re; wire datapath_tx_fifo_asyncfifo_readable; wire [37:0] datapath_tx_fifo_asyncfifo_din; wire [37:0] datapath_tx_fifo_asyncfifo_dout; wire datapath_tx_fifo_graycounter0_ce; (* dont_touch = "true" *) reg [3:0] datapath_tx_fifo_graycounter0_q = 4'd0; wire [3:0] datapath_tx_fifo_graycounter0_q_next; reg [3:0] datapath_tx_fifo_graycounter0_q_binary = 4'd0; reg [3:0] datapath_tx_fifo_graycounter0_q_next_binary = 4'd0; wire datapath_tx_fifo_graycounter1_ce; (* dont_touch = "true" *) reg [3:0] datapath_tx_fifo_graycounter1_q = 4'd0; wire [3:0] datapath_tx_fifo_graycounter1_q_next; reg [3:0] datapath_tx_fifo_graycounter1_q_binary = 4'd0; reg [3:0] datapath_tx_fifo_graycounter1_q_next_binary = 4'd0; wire [3:0] datapath_tx_fifo_produce_rdomain; wire [3:0] datapath_tx_fifo_consume_wdomain; wire [2:0] datapath_tx_fifo_wrport_adr; wire [37:0] datapath_tx_fifo_wrport_dat_r; wire datapath_tx_fifo_wrport_we; wire [37:0] datapath_tx_fifo_wrport_dat_w; wire [2:0] datapath_tx_fifo_rdport_adr; wire [37:0] datapath_tx_fifo_rdport_dat_r; wire [31:0] datapath_tx_fifo_fifo_in_payload_data; wire [3:0] datapath_tx_fifo_fifo_in_payload_charisk; wire datapath_tx_fifo_fifo_in_first; wire datapath_tx_fifo_fifo_in_last; wire [31:0] datapath_tx_fifo_fifo_out_payload_data; wire [3:0] datapath_tx_fifo_fifo_out_payload_charisk; wire datapath_tx_fifo_fifo_out_first; wire datapath_tx_fifo_fifo_out_last; wire datapath_tx_converter_sink_valid; wire datapath_tx_converter_sink_ready; wire datapath_tx_converter_sink_first; wire datapath_tx_converter_sink_last; wire [31:0] datapath_tx_converter_sink_payload_data; wire [3:0] datapath_tx_converter_sink_payload_charisk; wire datapath_tx_converter_source_valid; wire datapath_tx_converter_source_ready; wire datapath_tx_converter_source_first; wire datapath_tx_converter_source_last; wire [15:0] datapath_tx_converter_source_payload_data; wire [1:0] datapath_tx_converter_source_payload_charisk; wire datapath_tx_converter_converter_sink_valid; wire datapath_tx_converter_converter_sink_ready; wire datapath_tx_converter_converter_sink_first; wire datapath_tx_converter_converter_sink_last; reg [35:0] datapath_tx_converter_converter_sink_payload_data = 36'd0; wire datapath_tx_converter_converter_source_valid; wire datapath_tx_converter_converter_source_ready; wire datapath_tx_converter_converter_source_first; wire datapath_tx_converter_converter_source_last; reg [17:0] datapath_tx_converter_converter_source_payload_data = 18'd0; wire datapath_tx_converter_converter_source_payload_valid_token_count; reg datapath_tx_converter_converter_mux = 1'd0; wire datapath_tx_converter_converter_first; wire datapath_tx_converter_converter_last; wire datapath_tx_converter_source_source_valid; wire datapath_tx_converter_source_source_ready; wire datapath_tx_converter_source_source_first; wire datapath_tx_converter_source_source_last; wire [17:0] datapath_tx_converter_source_source_payload_data; wire datapath_rx_sink_sink_valid; wire datapath_rx_sink_sink_ready; wire datapath_rx_sink_sink_first; wire datapath_rx_sink_sink_last; wire [15:0] datapath_rx_sink_sink_payload_data; wire [1:0] datapath_rx_sink_sink_payload_charisk; wire datapath_rx_source_source_valid; wire datapath_rx_source_source_ready; wire datapath_rx_source_source_first; wire datapath_rx_source_source_last; wire [31:0] datapath_rx_source_source_payload_data; wire [3:0] datapath_rx_source_source_payload_charisk; reg [1:0] datapath_rx_byte_alignment = 2'd0; reg [1:0] datapath_rx_last_charisk = 2'd0; reg [15:0] datapath_rx_last_data = 16'd0; wire [3:0] datapath_rx_sr_charisk; wire [31:0] datapath_rx_sr_data; wire datapath_rx_converter_sink_valid; wire datapath_rx_converter_sink_ready; reg datapath_rx_converter_sink_first = 1'd0; reg datapath_rx_converter_sink_last = 1'd0; reg [15:0] datapath_rx_converter_sink_payload_data = 16'd0; reg [1:0] datapath_rx_converter_sink_payload_charisk = 2'd0; wire datapath_rx_converter_source_valid; wire datapath_rx_converter_source_ready; wire datapath_rx_converter_source_first; wire datapath_rx_converter_source_last; reg [31:0] datapath_rx_converter_source_payload_data = 32'd0; reg [3:0] datapath_rx_converter_source_payload_charisk = 4'd0; wire datapath_rx_converter_converter_sink_valid; wire datapath_rx_converter_converter_sink_ready; wire datapath_rx_converter_converter_sink_first; wire datapath_rx_converter_converter_sink_last; wire [17:0] datapath_rx_converter_converter_sink_payload_data; wire datapath_rx_converter_converter_source_valid; wire datapath_rx_converter_converter_source_ready; reg datapath_rx_converter_converter_source_first = 1'd0; reg datapath_rx_converter_converter_source_last = 1'd0; reg [35:0] datapath_rx_converter_converter_source_payload_data = 36'd0; reg [1:0] datapath_rx_converter_converter_source_payload_valid_token_count = 2'd0; reg datapath_rx_converter_converter_demux = 1'd0; wire datapath_rx_converter_converter_load_part; reg datapath_rx_converter_converter_strobe_all = 1'd0; wire datapath_rx_converter_source_source_valid; wire datapath_rx_converter_source_source_ready; wire datapath_rx_converter_source_source_first; wire datapath_rx_converter_source_source_last; wire [35:0] datapath_rx_converter_source_source_payload_data; wire datapath_rx_converter_reset; wire datapath_rx_fifo_sink_valid; wire datapath_rx_fifo_sink_ready; wire datapath_rx_fifo_sink_first; wire datapath_rx_fifo_sink_last; wire [31:0] datapath_rx_fifo_sink_payload_data; wire [3:0] datapath_rx_fifo_sink_payload_charisk; wire datapath_rx_fifo_source_valid; wire datapath_rx_fifo_source_ready; wire datapath_rx_fifo_source_first; wire datapath_rx_fifo_source_last; wire [31:0] datapath_rx_fifo_source_payload_data; wire [3:0] datapath_rx_fifo_source_payload_charisk; wire datapath_rx_fifo_asyncfifo_we; wire datapath_rx_fifo_asyncfifo_writable; wire datapath_rx_fifo_asyncfifo_re; wire datapath_rx_fifo_asyncfifo_readable; wire [37:0] datapath_rx_fifo_asyncfifo_din; wire [37:0] datapath_rx_fifo_asyncfifo_dout; wire datapath_rx_fifo_graycounter0_ce; (* dont_touch = "true" *) reg [3:0] datapath_rx_fifo_graycounter0_q = 4'd0; wire [3:0] datapath_rx_fifo_graycounter0_q_next; reg [3:0] datapath_rx_fifo_graycounter0_q_binary = 4'd0; reg [3:0] datapath_rx_fifo_graycounter0_q_next_binary = 4'd0; wire datapath_rx_fifo_graycounter1_ce; (* dont_touch = "true" *) reg [3:0] datapath_rx_fifo_graycounter1_q = 4'd0; wire [3:0] datapath_rx_fifo_graycounter1_q_next; reg [3:0] datapath_rx_fifo_graycounter1_q_binary = 4'd0; reg [3:0] datapath_rx_fifo_graycounter1_q_next_binary = 4'd0; wire [3:0] datapath_rx_fifo_produce_rdomain; wire [3:0] datapath_rx_fifo_consume_wdomain; wire [2:0] datapath_rx_fifo_wrport_adr; wire [37:0] datapath_rx_fifo_wrport_dat_r; wire datapath_rx_fifo_wrport_we; wire [37:0] datapath_rx_fifo_wrport_dat_w; wire [2:0] datapath_rx_fifo_rdport_adr; wire [37:0] datapath_rx_fifo_rdport_dat_r; wire [31:0] datapath_rx_fifo_fifo_in_payload_data; wire [3:0] datapath_rx_fifo_fifo_in_payload_charisk; wire datapath_rx_fifo_fifo_in_first; wire datapath_rx_fifo_fifo_in_last; wire [31:0] datapath_rx_fifo_fifo_out_payload_data; wire [3:0] datapath_rx_fifo_fifo_out_payload_charisk; wire datapath_rx_fifo_fifo_out_first; wire datapath_rx_fifo_fifo_out_last; wire datapath_demux_sink_valid; reg datapath_demux_sink_ready = 1'd0; wire datapath_demux_sink_first; wire datapath_demux_sink_last; wire [31:0] datapath_demux_sink_payload_data; wire [3:0] datapath_demux_sink_payload_charisk; reg datapath_demux_endpoint0_source_valid = 1'd0; wire datapath_demux_endpoint0_source_ready; reg datapath_demux_endpoint0_source_first = 1'd0; reg datapath_demux_endpoint0_source_last = 1'd0; reg [31:0] datapath_demux_endpoint0_source_payload_data = 32'd0; reg [3:0] datapath_demux_endpoint0_source_payload_charisk = 4'd0; reg datapath_demux_endpoint1_source_valid = 1'd0; wire datapath_demux_endpoint1_source_ready; reg datapath_demux_endpoint1_source_first = 1'd0; reg datapath_demux_endpoint1_source_last = 1'd0; reg [31:0] datapath_demux_endpoint1_source_payload_data = 32'd0; reg [3:0] datapath_demux_endpoint1_source_payload_charisk = 4'd0; wire datapath_demux_sel; wire datapath_align_timer_sink_valid; wire datapath_align_timer_sink_first; wire datapath_align_timer_sink_last; wire [31:0] datapath_align_timer_sink_payload_data; wire [3:0] datapath_align_timer_sink_payload_charisk; reg datapath_align_timer_wait = 1'd0; wire datapath_align_timer_done; reg [12:0] datapath_align_timer_count = 13'd4096; reg litesataphy_enable_storage = 1'd1; reg litesataphy_enable_re = 1'd0; wire litesataphy_ready; wire litesataphy_tx_ready; wire litesataphy_rx_ready; wire litesataphy_ctrl_ready; reg [3:0] litesataphy_status_status = 4'd0; wire litesataphy_status_we; reg litesataphy_status_re = 1'd0; reg link_litesatalinktx_sink_sink_valid = 1'd0; wire link_litesatalinktx_sink_sink_ready; reg link_litesatalinktx_sink_sink_first = 1'd0; reg link_litesatalinktx_sink_sink_last = 1'd0; reg [31:0] link_litesatalinktx_sink_sink_payload_data = 32'd0; reg link_litesatalinktx_sink_sink_payload_error = 1'd0; reg link_litesatalinktx_source_source_valid = 1'd0; wire link_litesatalinktx_source_source_ready; reg link_litesatalinktx_source_source_first = 1'd0; reg link_litesatalinktx_source_source_last = 1'd0; reg [31:0] link_litesatalinktx_source_source_payload_data = 32'd0; reg [3:0] link_litesatalinktx_source_source_payload_charisk = 4'd0; wire link_litesatalinktx_from_rx_valid; reg link_litesatalinktx_from_rx_ready = 1'd0; wire link_litesatalinktx_from_rx_first; wire link_litesatalinktx_from_rx_last; wire link_litesatalinktx_from_rx_payload_idle; wire [31:0] link_litesatalinktx_from_rx_payload_insert; wire link_litesatalinktx_from_rx_payload_primitive_valid; wire [31:0] link_litesatalinktx_from_rx_payload_primitive; reg link_litesatalinktx_error = 1'd0; wire link_litesatalinktx_crc_sink_valid; reg link_litesatalinktx_crc_sink_ready = 1'd0; wire link_litesatalinktx_crc_sink_first; wire link_litesatalinktx_crc_sink_last; wire [31:0] link_litesatalinktx_crc_sink_payload_data; wire link_litesatalinktx_crc_sink_payload_error; reg link_litesatalinktx_crc_source_valid = 1'd0; wire link_litesatalinktx_crc_source_ready; reg link_litesatalinktx_crc_source_first = 1'd0; reg link_litesatalinktx_crc_source_last = 1'd0; reg [31:0] link_litesatalinktx_crc_source_payload_data = 32'd0; reg link_litesatalinktx_crc_source_payload_error = 1'd0; wire link_litesatalinktx_crc_busy; reg [31:0] link_litesatalinktx_crc_data0 = 32'd0; wire [31:0] link_litesatalinktx_crc_value; wire link_litesatalinktx_crc_error; wire [31:0] link_litesatalinktx_crc_data1; wire [31:0] link_litesatalinktx_crc_last; reg [31:0] link_litesatalinktx_crc_next = 32'd0; wire [31:0] link_litesatalinktx_crc_new; reg [31:0] link_litesatalinktx_crc_reg_i = 32'd1379029042; reg link_litesatalinktx_crc_ce = 1'd0; reg link_litesatalinktx_crc_reset = 1'd0; reg link_litesatalinktx_crc_is_ongoing = 1'd0; wire link_litesatalinktx_scrambler_sink_valid; wire link_litesatalinktx_scrambler_sink_ready; wire link_litesatalinktx_scrambler_sink_first; wire link_litesatalinktx_scrambler_sink_last; wire [31:0] link_litesatalinktx_scrambler_sink_payload_data; wire link_litesatalinktx_scrambler_sink_payload_error; wire link_litesatalinktx_scrambler_source_valid; reg link_litesatalinktx_scrambler_source_ready = 1'd0; wire link_litesatalinktx_scrambler_source_first; wire link_litesatalinktx_scrambler_source_last; reg [31:0] link_litesatalinktx_scrambler_source_payload_data = 32'd0; wire link_litesatalinktx_scrambler_source_payload_error; wire [31:0] link_litesatalinktx_scrambler_value; reg [15:0] link_litesatalinktx_scrambler_context = 16'd61686; reg [31:0] link_litesatalinktx_scrambler_next_value = 32'd0; wire link_litesatalinktx_scrambler_ce; reg link_litesatalinktx_scrambler_reset = 1'd0; reg [31:0] link_litesatalinktx_insert = 32'd0; reg link_litesatalinktx_copy = 1'd0; reg link_litesatalinktx_fsm_is_ongoing0 = 1'd0; reg link_litesatalinktx_fsm_is_ongoing1 = 1'd0; wire link_tx_sink_valid; wire link_tx_sink_ready; wire link_tx_sink_first; wire link_tx_sink_last; wire [31:0] link_tx_sink_payload_data; wire [3:0] link_tx_sink_payload_charisk; reg link_tx_source_valid = 1'd0; wire link_tx_source_ready; reg link_tx_source_first = 1'd0; reg link_tx_source_last = 1'd0; reg [31:0] link_tx_source_payload_data = 32'd0; reg [3:0] link_tx_source_payload_charisk = 4'd0; wire link_tx_align_sink_valid; reg link_tx_align_sink_ready = 1'd0; wire link_tx_align_sink_first; wire link_tx_align_sink_last; wire [31:0] link_tx_align_sink_payload_data; wire [3:0] link_tx_align_sink_payload_charisk; reg link_tx_align_source_valid = 1'd0; wire link_tx_align_source_ready; reg link_tx_align_source_first = 1'd0; reg link_tx_align_source_last = 1'd0; reg [31:0] link_tx_align_source_payload_data = 32'd0; reg [3:0] link_tx_align_source_payload_charisk = 4'd0; reg [7:0] link_tx_align_cnt = 8'd0; wire link_tx_align_send; wire link_rx_align_sink_valid; reg link_rx_align_sink_ready = 1'd0; wire link_rx_align_sink_first; wire link_rx_align_sink_last; wire [31:0] link_rx_align_sink_payload_data; wire [3:0] link_rx_align_sink_payload_charisk; reg link_rx_align_source_valid = 1'd0; wire link_rx_align_source_ready; reg link_rx_align_source_first = 1'd0; reg link_rx_align_source_last = 1'd0; reg [31:0] link_rx_align_source_payload_data = 32'd0; reg [3:0] link_rx_align_source_payload_charisk = 4'd0; wire link_rx_cont_sink_valid; wire link_rx_cont_sink_ready; wire link_rx_cont_sink_first; wire link_rx_cont_sink_last; wire [31:0] link_rx_cont_sink_payload_data; wire [3:0] link_rx_cont_sink_payload_charisk; wire link_rx_cont_source_valid; wire link_rx_cont_source_ready; wire link_rx_cont_source_first; wire link_rx_cont_source_last; reg [31:0] link_rx_cont_source_payload_data = 32'd0; reg [3:0] link_rx_cont_source_payload_charisk = 4'd0; wire link_rx_cont_is_data; wire link_rx_cont_is_cont; reg link_rx_cont_in_cont = 1'd0; wire link_rx_cont_cont_ongoing; reg [31:0] link_rx_cont_last_primitive = 32'd0; wire link_litesatalinkrx_sink_sink_valid; wire link_litesatalinkrx_sink_sink_ready; wire link_litesatalinkrx_sink_sink_first; wire link_litesatalinkrx_sink_sink_last; wire [31:0] link_litesatalinkrx_sink_sink_payload_data; wire [3:0] link_litesatalinkrx_sink_sink_payload_charisk; wire link_litesatalinkrx_source_source_valid; wire link_litesatalinkrx_source_source_ready; wire link_litesatalinkrx_source_source_first; wire link_litesatalinkrx_source_source_last; wire [31:0] link_litesatalinkrx_source_source_payload_data; wire link_litesatalinkrx_source_source_payload_error; wire link_litesatalinkrx_hold; reg link_litesatalinkrx_to_tx_valid = 1'd0; wire link_litesatalinkrx_to_tx_ready; reg link_litesatalinkrx_to_tx_first = 1'd0; reg link_litesatalinkrx_to_tx_last = 1'd0; wire link_litesatalinkrx_to_tx_payload_idle; wire [31:0] link_litesatalinkrx_to_tx_payload_insert; wire link_litesatalinkrx_to_tx_payload_primitive_valid; wire [31:0] link_litesatalinkrx_to_tx_payload_primitive; reg [31:0] link_litesatalinkrx_insert = 32'd0; reg link_litesatalinkrx_data_valid = 1'd0; reg link_litesatalinkrx_primitive_valid = 1'd0; wire [31:0] link_litesatalinkrx_primitive; reg link_litesatalinkrx_descrambler_sink_valid = 1'd0; wire link_litesatalinkrx_descrambler_sink_ready; reg link_litesatalinkrx_descrambler_sink_first = 1'd0; reg link_litesatalinkrx_descrambler_sink_last = 1'd0; reg [31:0] link_litesatalinkrx_descrambler_sink_payload_data = 32'd0; reg link_litesatalinkrx_descrambler_sink_payload_error = 1'd0; wire link_litesatalinkrx_descrambler_source_valid; wire link_litesatalinkrx_descrambler_source_ready; wire link_litesatalinkrx_descrambler_source_first; wire link_litesatalinkrx_descrambler_source_last; reg [31:0] link_litesatalinkrx_descrambler_source_payload_data = 32'd0; wire link_litesatalinkrx_descrambler_source_payload_error; wire [31:0] link_litesatalinkrx_descrambler_value; reg [15:0] link_litesatalinkrx_descrambler_context = 16'd61686; reg [31:0] link_litesatalinkrx_descrambler_next_value = 32'd0; wire link_litesatalinkrx_descrambler_ce; reg link_litesatalinkrx_descrambler_reset = 1'd0; wire link_litesatalinkrx_crc_sink_sink_valid; reg link_litesatalinkrx_crc_sink_sink_ready = 1'd0; wire link_litesatalinkrx_crc_sink_sink_first; wire link_litesatalinkrx_crc_sink_sink_last; wire [31:0] link_litesatalinkrx_crc_sink_sink_payload_data; wire link_litesatalinkrx_crc_sink_sink_payload_error; wire link_litesatalinkrx_crc_source_source_valid; wire link_litesatalinkrx_crc_source_source_ready; reg link_litesatalinkrx_crc_source_source_first = 1'd0; wire link_litesatalinkrx_crc_source_source_last; wire [31:0] link_litesatalinkrx_crc_source_source_payload_data; reg link_litesatalinkrx_crc_source_source_payload_error = 1'd0; wire link_litesatalinkrx_crc_busy; reg [31:0] link_litesatalinkrx_crc_crc_data0 = 32'd0; wire [31:0] link_litesatalinkrx_crc_crc_value; wire link_litesatalinkrx_crc_crc_error; wire [31:0] link_litesatalinkrx_crc_crc_data1; wire [31:0] link_litesatalinkrx_crc_crc_last; reg [31:0] link_litesatalinkrx_crc_crc_next = 32'd0; wire [31:0] link_litesatalinkrx_crc_crc_new; reg [31:0] link_litesatalinkrx_crc_crc_reg_i = 32'd1379029042; reg link_litesatalinkrx_crc_crc_ce = 1'd0; reg link_litesatalinkrx_crc_crc_reset = 1'd0; reg link_litesatalinkrx_crc_syncfifo_sink_valid = 1'd0; wire link_litesatalinkrx_crc_syncfifo_sink_ready; wire link_litesatalinkrx_crc_syncfifo_sink_first; wire link_litesatalinkrx_crc_syncfifo_sink_last; wire [31:0] link_litesatalinkrx_crc_syncfifo_sink_payload_data; wire link_litesatalinkrx_crc_syncfifo_sink_payload_error; wire link_litesatalinkrx_crc_syncfifo_source_valid; wire link_litesatalinkrx_crc_syncfifo_source_ready; wire link_litesatalinkrx_crc_syncfifo_source_first; wire link_litesatalinkrx_crc_syncfifo_source_last; wire [31:0] link_litesatalinkrx_crc_syncfifo_source_payload_data; wire link_litesatalinkrx_crc_syncfifo_source_payload_error; wire link_litesatalinkrx_crc_syncfifo_syncfifo_we; wire link_litesatalinkrx_crc_syncfifo_syncfifo_writable; wire link_litesatalinkrx_crc_syncfifo_syncfifo_re; wire link_litesatalinkrx_crc_syncfifo_syncfifo_readable; wire [34:0] link_litesatalinkrx_crc_syncfifo_syncfifo_din; wire [34:0] link_litesatalinkrx_crc_syncfifo_syncfifo_dout; reg [1:0] link_litesatalinkrx_crc_syncfifo_level = 2'd0; reg link_litesatalinkrx_crc_syncfifo_replace = 1'd0; reg link_litesatalinkrx_crc_syncfifo_produce = 1'd0; reg link_litesatalinkrx_crc_syncfifo_consume = 1'd0; reg link_litesatalinkrx_crc_syncfifo_wrport_adr = 1'd0; wire [34:0] link_litesatalinkrx_crc_syncfifo_wrport_dat_r; wire link_litesatalinkrx_crc_syncfifo_wrport_we; wire [34:0] link_litesatalinkrx_crc_syncfifo_wrport_dat_w; wire link_litesatalinkrx_crc_syncfifo_do_read; wire link_litesatalinkrx_crc_syncfifo_rdport_adr; wire [34:0] link_litesatalinkrx_crc_syncfifo_rdport_dat_r; wire [31:0] link_litesatalinkrx_crc_syncfifo_fifo_in_payload_data; wire link_litesatalinkrx_crc_syncfifo_fifo_in_payload_error; wire link_litesatalinkrx_crc_syncfifo_fifo_in_first; wire link_litesatalinkrx_crc_syncfifo_fifo_in_last; wire [31:0] link_litesatalinkrx_crc_syncfifo_fifo_out_payload_data; wire link_litesatalinkrx_crc_syncfifo_fifo_out_payload_error; wire link_litesatalinkrx_crc_syncfifo_fifo_out_first; wire link_litesatalinkrx_crc_syncfifo_fifo_out_last; reg link_litesatalinkrx_crc_fifo_reset = 1'd0; wire link_litesatalinkrx_crc_fifo_in; wire link_litesatalinkrx_crc_fifo_out; wire link_litesatalinkrx_crc_fifo_full; reg link_litesatalinkrx_crc_is_ongoing = 1'd0; reg link_litesatalinkrx_crc_error = 1'd0; reg link_litesatalinkrx_fsm_is_ongoing = 1'd0; wire link_rx_sink_valid; wire link_rx_sink_ready; wire link_rx_sink_first; wire link_rx_sink_last; wire [31:0] link_rx_sink_payload_data; wire [3:0] link_rx_sink_payload_charisk; reg link_rx_source_valid = 1'd0; wire link_rx_source_ready; reg link_rx_source_first = 1'd0; reg link_rx_source_last = 1'd0; reg [31:0] link_rx_source_payload_data = 32'd0; reg [3:0] link_rx_source_payload_charisk = 4'd0; wire link_rx_buffer_sink_valid; wire link_rx_buffer_sink_ready; wire link_rx_buffer_sink_first; wire link_rx_buffer_sink_last; wire [31:0] link_rx_buffer_sink_payload_data; wire link_rx_buffer_sink_payload_error; wire link_rx_buffer_source_valid; reg link_rx_buffer_source_ready = 1'd0; wire link_rx_buffer_source_first; wire link_rx_buffer_source_last; wire [31:0] link_rx_buffer_source_payload_data; wire link_rx_buffer_source_payload_error; wire link_rx_buffer_syncfifo_we; wire link_rx_buffer_syncfifo_writable; wire link_rx_buffer_syncfifo_re; wire link_rx_buffer_syncfifo_readable; wire [34:0] link_rx_buffer_syncfifo_din; wire [34:0] link_rx_buffer_syncfifo_dout; reg [7:0] link_rx_buffer_level = 8'd0; reg link_rx_buffer_replace = 1'd0; reg [6:0] link_rx_buffer_produce = 7'd0; reg [6:0] link_rx_buffer_consume = 7'd0; reg [6:0] link_rx_buffer_wrport_adr = 7'd0; wire [34:0] link_rx_buffer_wrport_dat_r; wire link_rx_buffer_wrport_we; wire [34:0] link_rx_buffer_wrport_dat_w; wire link_rx_buffer_do_read; wire [6:0] link_rx_buffer_rdport_adr; wire [34:0] link_rx_buffer_rdport_dat_r; wire [31:0] link_rx_buffer_fifo_in_payload_data; wire link_rx_buffer_fifo_in_payload_error; wire link_rx_buffer_fifo_in_first; wire link_rx_buffer_fifo_in_last; wire [31:0] link_rx_buffer_fifo_out_payload_data; wire link_rx_buffer_fifo_out_payload_error; wire link_rx_buffer_fifo_out_first; wire link_rx_buffer_fifo_out_last; reg transport_tx_sink_valid = 1'd0; reg transport_tx_sink_ready = 1'd0; reg transport_tx_sink_last = 1'd0; wire [31:0] transport_tx_sink_payload_data; reg [7:0] transport_tx_sink_param_type = 8'd0; wire [3:0] transport_tx_sink_param_pm_port; reg transport_tx_sink_param_c = 1'd0; reg [7:0] transport_tx_sink_param_command = 8'd0; wire [15:0] transport_tx_sink_param_features; wire [47:0] transport_tx_sink_param_lba; wire [7:0] transport_tx_sink_param_device; wire [15:0] transport_tx_sink_param_count; wire [7:0] transport_tx_sink_param_icc; wire [7:0] transport_tx_sink_param_control; reg [159:0] transport_tx_encoded_cmd = 160'd0; reg [2:0] transport_tx_counter = 3'd0; wire transport_tx_counter_ce; reg transport_tx_counter_reset = 1'd0; reg [2:0] transport_tx_cmd_len = 3'd0; reg transport_tx_cmd_with_data = 1'd0; reg transport_tx_cmd_send = 1'd0; reg transport_tx_data_send = 1'd0; wire transport_tx_cmd_done; reg [7:0] transport_tx_fis_type = 8'd0; reg transport_tx_update_fis_type = 1'd0; reg transport_rx_source_valid = 1'd0; reg transport_rx_source_ready = 1'd0; reg transport_rx_source_last = 1'd0; reg [31:0] transport_rx_source_payload_data = 32'd0; reg [7:0] transport_rx_source_param_type = 8'd0; reg [3:0] transport_rx_source_param_pm_port = 4'd0; reg transport_rx_source_param_d = 1'd0; reg transport_rx_source_param_i = 1'd0; reg [7:0] transport_rx_source_param_status = 8'd0; reg [7:0] transport_rx_source_param_errors = 8'd0; reg [47:0] transport_rx_source_param_lba = 48'd0; reg [7:0] transport_rx_source_param_device = 8'd0; reg [15:0] transport_rx_source_param_count = 16'd0; reg [15:0] transport_rx_source_param_transfer_count = 16'd0; reg transport_rx_source_param_error = 1'd0; reg [159:0] transport_rx_encoded_cmd = 160'd0; reg [2:0] transport_rx_counter = 3'd0; reg transport_rx_counter_ce = 1'd0; reg transport_rx_counter_reset = 1'd0; reg [2:0] transport_rx_cmd_len = 3'd0; reg transport_rx_cmd_receive = 1'd0; reg transport_rx_data_receive = 1'd0; wire transport_rx_cmd_done; reg [7:0] transport_rx_fis_type = 8'd0; reg transport_rx_update_fis_type = 1'd0; wire command_tx_sink_valid; reg command_tx_sink_ready = 1'd0; wire command_tx_sink_first; wire command_tx_sink_last; wire [31:0] command_tx_sink_payload_data; wire command_tx_sink_param_write; wire command_tx_sink_param_read; wire command_tx_sink_param_identify; wire [47:0] command_tx_sink_param_sector; wire [15:0] command_tx_sink_param_count; reg command_tx_to_rx_valid = 1'd0; wire command_tx_to_rx_ready; reg command_tx_to_rx_first = 1'd0; reg command_tx_to_rx_last = 1'd0; reg command_tx_to_rx_payload_write = 1'd0; reg command_tx_to_rx_payload_read = 1'd0; reg command_tx_to_rx_payload_identify = 1'd0; reg [15:0] command_tx_to_rx_payload_count = 16'd0; wire command_tx_from_rx_valid; reg command_tx_from_rx_ready = 1'd0; wire command_tx_from_rx_first; wire command_tx_from_rx_last; wire command_tx_from_rx_payload_dma_activate; wire command_tx_from_rx_payload_d2h_error; reg command_tx_is_write = 1'd0; reg command_tx_is_read = 1'd0; reg command_tx_is_identify = 1'd0; reg [10:0] command_tx_dwords_counter = 11'd0; reg command_tx_is_ongoing0 = 1'd0; reg command_tx_is_ongoing1 = 1'd0; reg command_rx_source_valid = 1'd0; wire command_rx_source_ready; reg command_rx_source_first = 1'd0; reg command_rx_source_last = 1'd0; reg [31:0] command_rx_source_payload_data = 32'd0; reg command_rx_source_param_write = 1'd0; reg command_rx_source_param_read = 1'd0; reg command_rx_source_param_identify = 1'd0; reg command_rx_source_param_end = 1'd0; reg command_rx_source_param_failed = 1'd0; reg command_rx_to_tx_valid = 1'd0; wire command_rx_to_tx_ready; reg command_rx_to_tx_first = 1'd0; reg command_rx_to_tx_last = 1'd0; wire command_rx_to_tx_payload_dma_activate; wire command_rx_to_tx_payload_d2h_error; wire command_rx_from_tx_valid; reg command_rx_from_tx_ready = 1'd0; wire command_rx_from_tx_first; wire command_rx_from_tx_last; wire command_rx_from_tx_payload_write; wire command_rx_from_tx_payload_read; wire command_rx_from_tx_payload_identify; wire [15:0] command_rx_from_tx_payload_count; reg [7:0] command_rx_d2h_status = 8'd0; reg [7:0] command_rx_d2h_errors = 8'd0; reg command_rx_is_identify = 1'd0; reg command_rx_is_dma_activate = 1'd0; reg [22:0] command_rx_read_ndwords = 23'd0; reg [22:0] command_rx_dwords_counter = 23'd0; wire command_rx_read_done; reg command_rx_d2h_error = 1'd0; reg command_rx_clr_d2h_error = 1'd0; reg command_rx_set_d2h_error = 1'd0; reg command_rx_read_error = 1'd0; reg command_rx_clr_read_error = 1'd0; reg command_rx_set_read_error = 1'd0; reg command_rx_update_d2h = 1'd0; reg command_rx_is_ongoing = 1'd0; reg source_valid = 1'd0; wire source_ready; reg source_first = 1'd0; reg source_last = 1'd0; reg [31:0] source_payload_data = 32'd0; reg source_param_write = 1'd0; reg source_param_read = 1'd0; reg source_param_identify = 1'd0; reg [47:0] source_param_sector = 48'd0; reg [15:0] source_param_count = 16'd0; wire sink_valid; reg sink_ready = 1'd0; wire sink_first; wire sink_last; wire [31:0] sink_payload_data; wire sink_param_write; wire sink_param_read; wire sink_param_identify; wire sink_param_end; wire sink_param_failed; wire [31:0] interface0_bus_adr; wire [31:0] interface0_bus_dat_w; wire [31:0] interface0_bus_dat_r; wire [3:0] interface0_bus_sel; wire interface0_bus_cyc; wire interface0_bus_stb; wire interface0_bus_ack; wire interface0_bus_we; reg [2:0] interface0_bus_cti = 3'd0; reg [1:0] interface0_bus_bte = 2'd0; wire interface0_bus_err; reg litesatauserport0_sink_valid = 1'd0; reg litesatauserport0_sink_ready = 1'd0; reg litesatauserport0_sink_first = 1'd0; reg litesatauserport0_sink_last = 1'd0; reg [31:0] litesatauserport0_sink_payload_data = 32'd0; reg litesatauserport0_sink_param_write = 1'd0; reg litesatauserport0_sink_param_read = 1'd0; reg litesatauserport0_sink_param_identify = 1'd0; reg [47:0] litesatauserport0_sink_param_sector = 48'd0; reg [15:0] litesatauserport0_sink_param_count = 16'd0; reg litesatauserport0_source_valid = 1'd0; wire litesatauserport0_source_ready; reg litesatauserport0_source_first = 1'd0; reg litesatauserport0_source_last = 1'd0; reg [31:0] litesatauserport0_source_payload_data = 32'd0; reg litesatauserport0_source_param_write = 1'd0; reg litesatauserport0_source_param_read = 1'd0; reg litesatauserport0_source_param_identify = 1'd0; reg litesatauserport0_source_param_end = 1'd0; reg litesatauserport0_source_param_failed = 1'd0; reg [47:0] sata_sector2mem_sector_storage = 48'd0; reg sata_sector2mem_sector_re = 1'd0; reg [63:0] sata_sector2mem_base_storage = 64'd0; reg sata_sector2mem_base_re = 1'd0; wire sata_sector2mem_start_re; wire sata_sector2mem_start_r; wire sata_sector2mem_start_we; reg sata_sector2mem_start_w = 1'd0; reg sata_sector2mem_done_status = 1'd0; wire sata_sector2mem_done_we; reg sata_sector2mem_done_re = 1'd0; reg sata_sector2mem_error_status = 1'd0; wire sata_sector2mem_error_we; reg sata_sector2mem_error_re = 1'd0; reg [6:0] sata_sector2mem_count = 7'd0; wire sata_sector2mem_buf_sink_valid; wire sata_sector2mem_buf_sink_ready; reg sata_sector2mem_buf_sink_first = 1'd0; wire sata_sector2mem_buf_sink_last; wire [31:0] sata_sector2mem_buf_sink_payload_data; wire sata_sector2mem_buf_source_valid; wire sata_sector2mem_buf_source_ready; wire sata_sector2mem_buf_source_first; wire sata_sector2mem_buf_source_last; wire [31:0] sata_sector2mem_buf_source_payload_data; wire sata_sector2mem_buf_syncfifo_we; wire sata_sector2mem_buf_syncfifo_writable; wire sata_sector2mem_buf_syncfifo_re; wire sata_sector2mem_buf_syncfifo_readable; wire [33:0] sata_sector2mem_buf_syncfifo_din; wire [33:0] sata_sector2mem_buf_syncfifo_dout; reg [7:0] sata_sector2mem_buf_level = 8'd0; reg sata_sector2mem_buf_replace = 1'd0; reg [6:0] sata_sector2mem_buf_produce = 7'd0; reg [6:0] sata_sector2mem_buf_consume = 7'd0; reg [6:0] sata_sector2mem_buf_wrport_adr = 7'd0; wire [33:0] sata_sector2mem_buf_wrport_dat_r; wire sata_sector2mem_buf_wrport_we; wire [33:0] sata_sector2mem_buf_wrport_dat_w; wire sata_sector2mem_buf_do_read; wire [6:0] sata_sector2mem_buf_rdport_adr; wire [33:0] sata_sector2mem_buf_rdport_dat_r; wire [31:0] sata_sector2mem_buf_fifo_in_payload_data; wire sata_sector2mem_buf_fifo_in_first; wire sata_sector2mem_buf_fifo_in_last; wire [31:0] sata_sector2mem_buf_fifo_out_payload_data; wire sata_sector2mem_buf_fifo_out_first; wire sata_sector2mem_buf_fifo_out_last; wire sata_sector2mem_converter_sink_valid; wire sata_sector2mem_converter_sink_ready; wire sata_sector2mem_converter_sink_first; wire sata_sector2mem_converter_sink_last; wire [31:0] sata_sector2mem_converter_sink_payload_data; wire sata_sector2mem_converter_source_valid; wire sata_sector2mem_converter_source_ready; wire sata_sector2mem_converter_source_first; wire sata_sector2mem_converter_source_last; wire [31:0] sata_sector2mem_converter_source_payload_data; wire sata_sector2mem_converter_source_payload_valid_token_count; wire sata_sector2mem_source_source_valid; reg sata_sector2mem_source_source_ready = 1'd0; wire sata_sector2mem_source_source_first; wire sata_sector2mem_source_source_last; wire [31:0] sata_sector2mem_source_source_payload_data; reg sata_sector2mem_dma_sink_valid = 1'd0; wire sata_sector2mem_dma_sink_ready; reg sata_sector2mem_dma_sink_last = 1'd0; reg [31:0] sata_sector2mem_dma_sink_payload_address = 32'd0; reg [31:0] sata_sector2mem_dma_sink_payload_data = 32'd0; reg [31:0] interface1_bus_adr = 32'd0; reg [31:0] interface1_bus_dat_w = 32'd0; wire [31:0] interface1_bus_dat_r; reg [3:0] interface1_bus_sel = 4'd0; reg interface1_bus_cyc = 1'd0; reg interface1_bus_stb = 1'd0; wire interface1_bus_ack; reg interface1_bus_we = 1'd0; reg [2:0] interface1_bus_cti = 3'd0; reg [1:0] interface1_bus_bte = 2'd0; wire interface1_bus_err; reg litesatauserport1_sink_valid = 1'd0; reg litesatauserport1_sink_ready = 1'd0; reg litesatauserport1_sink_first = 1'd0; reg litesatauserport1_sink_last = 1'd0; reg [31:0] litesatauserport1_sink_payload_data = 32'd0; reg litesatauserport1_sink_param_write = 1'd0; reg litesatauserport1_sink_param_read = 1'd0; reg litesatauserport1_sink_param_identify = 1'd0; reg [47:0] litesatauserport1_sink_param_sector = 48'd0; reg [15:0] litesatauserport1_sink_param_count = 16'd0; reg litesatauserport1_source_valid = 1'd0; reg litesatauserport1_source_ready = 1'd0; reg litesatauserport1_source_first = 1'd0; reg litesatauserport1_source_last = 1'd0; reg [31:0] litesatauserport1_source_payload_data = 32'd0; reg litesatauserport1_source_param_write = 1'd0; reg litesatauserport1_source_param_read = 1'd0; reg litesatauserport1_source_param_identify = 1'd0; reg litesatauserport1_source_param_end = 1'd0; reg litesatauserport1_source_param_failed = 1'd0; reg [47:0] sata_mem2sector_sector_storage = 48'd0; reg sata_mem2sector_sector_re = 1'd0; reg [63:0] sata_mem2sector_base_storage = 64'd0; reg sata_mem2sector_base_re = 1'd0; wire sata_mem2sector_start_re; wire sata_mem2sector_start_r; wire sata_mem2sector_start_we; reg sata_mem2sector_start_w = 1'd0; reg sata_mem2sector_done_status = 1'd0; wire sata_mem2sector_done_we; reg sata_mem2sector_done_re = 1'd0; reg sata_mem2sector_error_status = 1'd0; wire sata_mem2sector_error_we; reg sata_mem2sector_error_re = 1'd0; reg [6:0] sata_mem2sector_count = 7'd0; reg sata_mem2sector_dma_sink_valid = 1'd0; reg sata_mem2sector_dma_sink_ready = 1'd0; reg sata_mem2sector_dma_sink_last = 1'd0; reg [31:0] sata_mem2sector_dma_sink_payload_address = 32'd0; reg sata_mem2sector_dma_source_valid = 1'd0; wire sata_mem2sector_dma_source_ready; reg sata_mem2sector_dma_source_first = 1'd0; reg sata_mem2sector_dma_source_last = 1'd0; reg [31:0] sata_mem2sector_dma_source_payload_data = 32'd0; reg [31:0] sata_mem2sector_dma_data = 32'd0; wire sata_mem2sector_buf_sink_valid; wire sata_mem2sector_buf_sink_ready; wire sata_mem2sector_buf_sink_first; wire sata_mem2sector_buf_sink_last; wire [31:0] sata_mem2sector_buf_sink_payload_data; wire sata_mem2sector_buf_source_valid; wire sata_mem2sector_buf_source_ready; wire sata_mem2sector_buf_source_first; wire sata_mem2sector_buf_source_last; wire [31:0] sata_mem2sector_buf_source_payload_data; wire sata_mem2sector_buf_syncfifo_we; wire sata_mem2sector_buf_syncfifo_writable; wire sata_mem2sector_buf_syncfifo_re; wire sata_mem2sector_buf_syncfifo_readable; wire [33:0] sata_mem2sector_buf_syncfifo_din; wire [33:0] sata_mem2sector_buf_syncfifo_dout; reg [7:0] sata_mem2sector_buf_level = 8'd0; reg sata_mem2sector_buf_replace = 1'd0; reg [6:0] sata_mem2sector_buf_produce = 7'd0; reg [6:0] sata_mem2sector_buf_consume = 7'd0; reg [6:0] sata_mem2sector_buf_wrport_adr = 7'd0; wire [33:0] sata_mem2sector_buf_wrport_dat_r; wire sata_mem2sector_buf_wrport_we; wire [33:0] sata_mem2sector_buf_wrport_dat_w; wire sata_mem2sector_buf_do_read; wire [6:0] sata_mem2sector_buf_rdport_adr; wire [33:0] sata_mem2sector_buf_rdport_dat_r; wire [31:0] sata_mem2sector_buf_fifo_in_payload_data; wire sata_mem2sector_buf_fifo_in_first; wire sata_mem2sector_buf_fifo_in_last; wire [31:0] sata_mem2sector_buf_fifo_out_payload_data; wire sata_mem2sector_buf_fifo_out_first; wire sata_mem2sector_buf_fifo_out_last; wire sata_mem2sector_converter_sink_valid; wire sata_mem2sector_converter_sink_ready; wire sata_mem2sector_converter_sink_first; wire sata_mem2sector_converter_sink_last; wire [31:0] sata_mem2sector_converter_sink_payload_data; wire sata_mem2sector_converter_source_valid; wire sata_mem2sector_converter_source_ready; wire sata_mem2sector_converter_source_first; wire sata_mem2sector_converter_source_last; wire [31:0] sata_mem2sector_converter_source_payload_data; wire sata_mem2sector_converter_source_payload_valid_token_count; wire sata_mem2sector_source_source_valid; reg sata_mem2sector_source_source_ready = 1'd0; wire sata_mem2sector_source_source_first; wire sata_mem2sector_source_source_last; wire [31:0] sata_mem2sector_source_source_payload_data; reg [7:0] storage = 8'd0; reg re = 1'd0; reg [7:0] chaser = 8'd0; reg mode = 1'd0; wire wait_1; wire done; reg [22:0] count = 23'd5000000; wire subfragments_reset0; wire subfragments_reset1; wire subfragments_reset2; wire subfragments_reset3; wire subfragments_reset4; wire subfragments_reset5; wire subfragments_reset6; wire subfragments_reset7; wire subfragments_pll_fb; reg [1:0] subfragments_refresher_state = 2'd0; reg [1:0] subfragments_refresher_next_state = 2'd0; reg [2:0] subfragments_bankmachine0_state = 3'd0; reg [2:0] subfragments_bankmachine0_next_state = 3'd0; reg [2:0] subfragments_bankmachine1_state = 3'd0; reg [2:0] subfragments_bankmachine1_next_state = 3'd0; reg [2:0] subfragments_bankmachine2_state = 3'd0; reg [2:0] subfragments_bankmachine2_next_state = 3'd0; reg [2:0] subfragments_bankmachine3_state = 3'd0; reg [2:0] subfragments_bankmachine3_next_state = 3'd0; reg [2:0] subfragments_bankmachine4_state = 3'd0; reg [2:0] subfragments_bankmachine4_next_state = 3'd0; reg [2:0] subfragments_bankmachine5_state = 3'd0; reg [2:0] subfragments_bankmachine5_next_state = 3'd0; reg [2:0] subfragments_bankmachine6_state = 3'd0; reg [2:0] subfragments_bankmachine6_next_state = 3'd0; reg [2:0] subfragments_bankmachine7_state = 3'd0; reg [2:0] subfragments_bankmachine7_next_state = 3'd0; reg [3:0] subfragments_multiplexer_state = 4'd0; reg [3:0] subfragments_multiplexer_next_state = 4'd0; wire subfragments_roundrobin0_request; wire subfragments_roundrobin0_grant; wire subfragments_roundrobin0_ce; wire subfragments_roundrobin1_request; wire subfragments_roundrobin1_grant; wire subfragments_roundrobin1_ce; wire subfragments_roundrobin2_request; wire subfragments_roundrobin2_grant; wire subfragments_roundrobin2_ce; wire subfragments_roundrobin3_request; wire subfragments_roundrobin3_grant; wire subfragments_roundrobin3_ce; wire subfragments_roundrobin4_request; wire subfragments_roundrobin4_grant; wire subfragments_roundrobin4_ce; wire subfragments_roundrobin5_request; wire subfragments_roundrobin5_grant; wire subfragments_roundrobin5_ce; wire subfragments_roundrobin6_request; wire subfragments_roundrobin6_grant; wire subfragments_roundrobin6_ce; wire subfragments_roundrobin7_request; wire subfragments_roundrobin7_grant; wire subfragments_roundrobin7_ce; reg subfragments_locked0 = 1'd0; reg subfragments_locked1 = 1'd0; reg subfragments_locked2 = 1'd0; reg subfragments_locked3 = 1'd0; reg subfragments_locked4 = 1'd0; reg subfragments_locked5 = 1'd0; reg subfragments_locked6 = 1'd0; reg subfragments_locked7 = 1'd0; reg subfragments_new_master_wdata_ready0 = 1'd0; reg subfragments_new_master_wdata_ready1 = 1'd0; reg subfragments_new_master_rdata_valid0 = 1'd0; reg subfragments_new_master_rdata_valid1 = 1'd0; reg subfragments_new_master_rdata_valid2 = 1'd0; reg subfragments_new_master_rdata_valid3 = 1'd0; reg subfragments_new_master_rdata_valid4 = 1'd0; reg subfragments_new_master_rdata_valid5 = 1'd0; reg subfragments_new_master_rdata_valid6 = 1'd0; reg subfragments_new_master_rdata_valid7 = 1'd0; reg subfragments_new_master_rdata_valid8 = 1'd0; reg [1:0] subfragments_fullmemorywe_state = 2'd0; reg [1:0] subfragments_fullmemorywe_next_state = 2'd0; reg [3:0] subfragments_litesataphy_gtptxinit_state = 4'd0; reg [3:0] subfragments_litesataphy_gtptxinit_next_state = 4'd0; reg [3:0] subfragments_litesataphy_gtprxinit_state = 4'd0; reg [3:0] subfragments_litesataphy_gtprxinit_next_state = 4'd0; reg [15:0] a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value = 16'd0; reg a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value_ce = 1'd0; reg [3:0] subfragments_litesataphy_state = 4'd0; reg [3:0] subfragments_litesataphy_next_state = 4'd0; reg [3:0] ctrl_align_count_subfragments_litesataphyctrl_next_value0 = 4'd0; reg ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 = 1'd0; reg a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 = 1'd0; reg a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 = 1'd0; reg a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value2 = 1'd0; reg a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value_ce2 = 1'd0; reg [1:0] subfragments_litesatalinktx_litesatacrcinserter_state = 2'd0; reg [1:0] subfragments_litesatalinktx_litesatacrcinserter_next_state = 2'd0; reg [2:0] subfragments_litesatalinktx_fsm_state = 3'd0; reg [2:0] subfragments_litesatalinktx_fsm_next_state = 3'd0; reg [1:0] subfragments_litesatalinkrx_litesatacrcchecker_state = 2'd0; reg [1:0] subfragments_litesatalinkrx_litesatacrcchecker_next_state = 2'd0; reg [2:0] subfragments_litesatalinkrx_fsm_state = 3'd0; reg [2:0] subfragments_litesatalinkrx_fsm_next_state = 3'd0; reg [1:0] subfragments_litesatatransporttx_state = 2'd0; reg [1:0] subfragments_litesatatransporttx_next_state = 2'd0; reg [2:0] subfragments_litesatatransportrx_state = 3'd0; reg [2:0] subfragments_litesatatransportrx_next_state = 3'd0; reg [1:0] subfragments_litesatacommandtx_state = 2'd0; reg [1:0] subfragments_litesatacommandtx_next_state = 2'd0; reg [10:0] command_tx_dwords_counter_subfragments_litesatacommandtx_next_value = 11'd0; reg command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce = 1'd0; reg [3:0] subfragments_litesatacommandrx_state = 4'd0; reg [3:0] subfragments_litesatacommandrx_next_state = 4'd0; reg [22:0] command_rx_dwords_counter_subfragments_litesatacommandrx_next_value = 23'd0; reg command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce = 1'd0; reg [1:0] subfragments_request = 2'd0; reg subfragments_grant = 1'd0; wire subfragments_done0; reg subfragments_ongoing0 = 1'd0; wire subfragments_done1; reg subfragments_ongoing1 = 1'd0; reg [1:0] subfragments_litesatasector2memdma_state = 2'd0; reg [1:0] subfragments_litesatasector2memdma_next_state = 2'd0; reg [6:0] sata_sector2mem_count_subfragments_next_value0 = 7'd0; reg sata_sector2mem_count_subfragments_next_value_ce0 = 1'd0; reg sata_sector2mem_error_status_subfragments_next_value1 = 1'd0; reg sata_sector2mem_error_status_subfragments_next_value_ce1 = 1'd0; reg subfragments_wishbonedmareader_state = 1'd0; reg subfragments_wishbonedmareader_next_state = 1'd0; reg [31:0] sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value = 32'd0; reg sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value_ce = 1'd0; reg [1:0] subfragments_fsm_state = 2'd0; reg [1:0] subfragments_fsm_next_state = 2'd0; reg [6:0] sata_mem2sector_count_subfragments_fsm_next_value0 = 7'd0; reg sata_mem2sector_count_subfragments_fsm_next_value_ce0 = 1'd0; reg sata_mem2sector_error_status_subfragments_fsm_next_value1 = 1'd0; reg sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 = 1'd0; reg [13:0] basesoc_basesoc_adr = 14'd0; reg basesoc_basesoc_we = 1'd0; reg [31:0] basesoc_basesoc_dat_w = 32'd0; wire [31:0] basesoc_basesoc_dat_r; wire [29:0] basesoc_basesoc_wishbone_adr; wire [31:0] basesoc_basesoc_wishbone_dat_w; reg [31:0] basesoc_basesoc_wishbone_dat_r = 32'd0; wire [3:0] basesoc_basesoc_wishbone_sel; wire basesoc_basesoc_wishbone_cyc; wire basesoc_basesoc_wishbone_stb; reg basesoc_basesoc_wishbone_ack = 1'd0; wire basesoc_basesoc_wishbone_we; wire [2:0] basesoc_basesoc_wishbone_cti; wire [1:0] basesoc_basesoc_wishbone_bte; reg basesoc_basesoc_wishbone_err = 1'd0; wire [29:0] basesoc_shared_adr; wire [31:0] basesoc_shared_dat_w; reg [31:0] basesoc_shared_dat_r = 32'd0; wire [3:0] basesoc_shared_sel; wire basesoc_shared_cyc; wire basesoc_shared_stb; reg basesoc_shared_ack = 1'd0; wire basesoc_shared_we; wire [2:0] basesoc_shared_cti; wire [1:0] basesoc_shared_bte; wire basesoc_shared_err; wire [3:0] basesoc_request; reg [1:0] basesoc_grant = 2'd0; reg [3:0] basesoc_slave_sel = 4'd0; reg [3:0] basesoc_slave_sel_r = 4'd0; reg basesoc_error = 1'd0; wire basesoc_wait; wire basesoc_done; reg [19:0] basesoc_count = 20'd1000000; wire [13:0] basesoc_csr_bankarray_interface0_bank_bus_adr; wire basesoc_csr_bankarray_interface0_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank0_reset0_re; wire basesoc_csr_bankarray_csrbank0_reset0_r; wire basesoc_csr_bankarray_csrbank0_reset0_we; wire basesoc_csr_bankarray_csrbank0_reset0_w; wire basesoc_csr_bankarray_csrbank0_scratch0_re; wire [31:0] basesoc_csr_bankarray_csrbank0_scratch0_r; wire basesoc_csr_bankarray_csrbank0_scratch0_we; wire [31:0] basesoc_csr_bankarray_csrbank0_scratch0_w; wire basesoc_csr_bankarray_csrbank0_bus_errors_re; wire [31:0] basesoc_csr_bankarray_csrbank0_bus_errors_r; wire basesoc_csr_bankarray_csrbank0_bus_errors_we; wire [31:0] basesoc_csr_bankarray_csrbank0_bus_errors_w; wire basesoc_csr_bankarray_csrbank0_sel; wire [13:0] basesoc_csr_bankarray_interface1_bank_bus_adr; wire basesoc_csr_bankarray_interface1_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank1_rst0_re; wire basesoc_csr_bankarray_csrbank1_rst0_r; wire basesoc_csr_bankarray_csrbank1_rst0_we; wire basesoc_csr_bankarray_csrbank1_rst0_w; wire basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_re; wire [4:0] basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_r; wire basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_we; wire [4:0] basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_w; wire basesoc_csr_bankarray_csrbank1_wlevel_en0_re; wire basesoc_csr_bankarray_csrbank1_wlevel_en0_r; wire basesoc_csr_bankarray_csrbank1_wlevel_en0_we; wire basesoc_csr_bankarray_csrbank1_wlevel_en0_w; wire basesoc_csr_bankarray_csrbank1_dly_sel0_re; wire [1:0] basesoc_csr_bankarray_csrbank1_dly_sel0_r; wire basesoc_csr_bankarray_csrbank1_dly_sel0_we; wire [1:0] basesoc_csr_bankarray_csrbank1_dly_sel0_w; wire basesoc_csr_bankarray_csrbank1_rdphase0_re; wire [1:0] basesoc_csr_bankarray_csrbank1_rdphase0_r; wire basesoc_csr_bankarray_csrbank1_rdphase0_we; wire [1:0] basesoc_csr_bankarray_csrbank1_rdphase0_w; wire basesoc_csr_bankarray_csrbank1_wrphase0_re; wire [1:0] basesoc_csr_bankarray_csrbank1_wrphase0_r; wire basesoc_csr_bankarray_csrbank1_wrphase0_we; wire [1:0] basesoc_csr_bankarray_csrbank1_wrphase0_w; wire basesoc_csr_bankarray_csrbank1_sel; wire [13:0] basesoc_csr_bankarray_sram_bus_adr; wire basesoc_csr_bankarray_sram_bus_we; wire [31:0] basesoc_csr_bankarray_sram_bus_dat_w; reg [31:0] basesoc_csr_bankarray_sram_bus_dat_r = 32'd0; wire [5:0] basesoc_csr_bankarray_adr; wire [7:0] basesoc_csr_bankarray_dat_r; wire basesoc_csr_bankarray_sel; reg basesoc_csr_bankarray_sel_r = 1'd0; wire [13:0] basesoc_csr_bankarray_interface2_bank_bus_adr; wire basesoc_csr_bankarray_interface2_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank2_out0_re; wire [7:0] basesoc_csr_bankarray_csrbank2_out0_r; wire basesoc_csr_bankarray_csrbank2_out0_we; wire [7:0] basesoc_csr_bankarray_csrbank2_out0_w; wire basesoc_csr_bankarray_csrbank2_sel; wire [13:0] basesoc_csr_bankarray_interface3_bank_bus_adr; wire basesoc_csr_bankarray_interface3_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank3_sector1_re; wire [15:0] basesoc_csr_bankarray_csrbank3_sector1_r; wire basesoc_csr_bankarray_csrbank3_sector1_we; wire [15:0] basesoc_csr_bankarray_csrbank3_sector1_w; wire basesoc_csr_bankarray_csrbank3_sector0_re; wire [31:0] basesoc_csr_bankarray_csrbank3_sector0_r; wire basesoc_csr_bankarray_csrbank3_sector0_we; wire [31:0] basesoc_csr_bankarray_csrbank3_sector0_w; wire basesoc_csr_bankarray_csrbank3_base1_re; wire [31:0] basesoc_csr_bankarray_csrbank3_base1_r; wire basesoc_csr_bankarray_csrbank3_base1_we; wire [31:0] basesoc_csr_bankarray_csrbank3_base1_w; wire basesoc_csr_bankarray_csrbank3_base0_re; wire [31:0] basesoc_csr_bankarray_csrbank3_base0_r; wire basesoc_csr_bankarray_csrbank3_base0_we; wire [31:0] basesoc_csr_bankarray_csrbank3_base0_w; wire basesoc_csr_bankarray_csrbank3_done_re; wire basesoc_csr_bankarray_csrbank3_done_r; wire basesoc_csr_bankarray_csrbank3_done_we; wire basesoc_csr_bankarray_csrbank3_done_w; wire basesoc_csr_bankarray_csrbank3_error_re; wire basesoc_csr_bankarray_csrbank3_error_r; wire basesoc_csr_bankarray_csrbank3_error_we; wire basesoc_csr_bankarray_csrbank3_error_w; wire basesoc_csr_bankarray_csrbank3_sel; wire [13:0] basesoc_csr_bankarray_interface4_bank_bus_adr; wire basesoc_csr_bankarray_interface4_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank4_enable0_re; wire basesoc_csr_bankarray_csrbank4_enable0_r; wire basesoc_csr_bankarray_csrbank4_enable0_we; wire basesoc_csr_bankarray_csrbank4_enable0_w; wire basesoc_csr_bankarray_csrbank4_status_re; wire [3:0] basesoc_csr_bankarray_csrbank4_status_r; wire basesoc_csr_bankarray_csrbank4_status_we; wire [3:0] basesoc_csr_bankarray_csrbank4_status_w; wire basesoc_csr_bankarray_csrbank4_sel; wire [13:0] basesoc_csr_bankarray_interface5_bank_bus_adr; wire basesoc_csr_bankarray_interface5_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank5_sector1_re; wire [15:0] basesoc_csr_bankarray_csrbank5_sector1_r; wire basesoc_csr_bankarray_csrbank5_sector1_we; wire [15:0] basesoc_csr_bankarray_csrbank5_sector1_w; wire basesoc_csr_bankarray_csrbank5_sector0_re; wire [31:0] basesoc_csr_bankarray_csrbank5_sector0_r; wire basesoc_csr_bankarray_csrbank5_sector0_we; wire [31:0] basesoc_csr_bankarray_csrbank5_sector0_w; wire basesoc_csr_bankarray_csrbank5_base1_re; wire [31:0] basesoc_csr_bankarray_csrbank5_base1_r; wire basesoc_csr_bankarray_csrbank5_base1_we; wire [31:0] basesoc_csr_bankarray_csrbank5_base1_w; wire basesoc_csr_bankarray_csrbank5_base0_re; wire [31:0] basesoc_csr_bankarray_csrbank5_base0_r; wire basesoc_csr_bankarray_csrbank5_base0_we; wire [31:0] basesoc_csr_bankarray_csrbank5_base0_w; wire basesoc_csr_bankarray_csrbank5_done_re; wire basesoc_csr_bankarray_csrbank5_done_r; wire basesoc_csr_bankarray_csrbank5_done_we; wire basesoc_csr_bankarray_csrbank5_done_w; wire basesoc_csr_bankarray_csrbank5_error_re; wire basesoc_csr_bankarray_csrbank5_error_r; wire basesoc_csr_bankarray_csrbank5_error_we; wire basesoc_csr_bankarray_csrbank5_error_w; wire basesoc_csr_bankarray_csrbank5_sel; wire [13:0] basesoc_csr_bankarray_interface6_bank_bus_adr; wire basesoc_csr_bankarray_interface6_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank6_dfii_control0_re; wire [3:0] basesoc_csr_bankarray_csrbank6_dfii_control0_r; wire basesoc_csr_bankarray_csrbank6_dfii_control0_we; wire [3:0] basesoc_csr_bankarray_csrbank6_dfii_control0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_re; wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_we; wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_re; wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_we; wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_re; wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_we; wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_re; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_we; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_re; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_we; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_re; wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_we; wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_re; wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_we; wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_re; wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_we; wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_re; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_we; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_re; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_we; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_re; wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_we; wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_re; wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_we; wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_re; wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_we; wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_re; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_we; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_re; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_we; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_re; wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_we; wire [5:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_re; wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_we; wire [13:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_re; wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_we; wire [2:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_re; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_we; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_w; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_re; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_r; wire basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_we; wire [31:0] basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_w; wire basesoc_csr_bankarray_csrbank6_sel; wire [13:0] basesoc_csr_bankarray_interface7_bank_bus_adr; wire basesoc_csr_bankarray_interface7_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank7_load0_re; wire [31:0] basesoc_csr_bankarray_csrbank7_load0_r; wire basesoc_csr_bankarray_csrbank7_load0_we; wire [31:0] basesoc_csr_bankarray_csrbank7_load0_w; wire basesoc_csr_bankarray_csrbank7_reload0_re; wire [31:0] basesoc_csr_bankarray_csrbank7_reload0_r; wire basesoc_csr_bankarray_csrbank7_reload0_we; wire [31:0] basesoc_csr_bankarray_csrbank7_reload0_w; wire basesoc_csr_bankarray_csrbank7_en0_re; wire basesoc_csr_bankarray_csrbank7_en0_r; wire basesoc_csr_bankarray_csrbank7_en0_we; wire basesoc_csr_bankarray_csrbank7_en0_w; wire basesoc_csr_bankarray_csrbank7_update_value0_re; wire basesoc_csr_bankarray_csrbank7_update_value0_r; wire basesoc_csr_bankarray_csrbank7_update_value0_we; wire basesoc_csr_bankarray_csrbank7_update_value0_w; wire basesoc_csr_bankarray_csrbank7_value_re; wire [31:0] basesoc_csr_bankarray_csrbank7_value_r; wire basesoc_csr_bankarray_csrbank7_value_we; wire [31:0] basesoc_csr_bankarray_csrbank7_value_w; wire basesoc_csr_bankarray_csrbank7_ev_status_re; wire basesoc_csr_bankarray_csrbank7_ev_status_r; wire basesoc_csr_bankarray_csrbank7_ev_status_we; wire basesoc_csr_bankarray_csrbank7_ev_status_w; wire basesoc_csr_bankarray_csrbank7_ev_pending_re; wire basesoc_csr_bankarray_csrbank7_ev_pending_r; wire basesoc_csr_bankarray_csrbank7_ev_pending_we; wire basesoc_csr_bankarray_csrbank7_ev_pending_w; wire basesoc_csr_bankarray_csrbank7_ev_enable0_re; wire basesoc_csr_bankarray_csrbank7_ev_enable0_r; wire basesoc_csr_bankarray_csrbank7_ev_enable0_we; wire basesoc_csr_bankarray_csrbank7_ev_enable0_w; wire basesoc_csr_bankarray_csrbank7_sel; wire [13:0] basesoc_csr_bankarray_interface8_bank_bus_adr; wire basesoc_csr_bankarray_interface8_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank8_txfull_re; wire basesoc_csr_bankarray_csrbank8_txfull_r; wire basesoc_csr_bankarray_csrbank8_txfull_we; wire basesoc_csr_bankarray_csrbank8_txfull_w; wire basesoc_csr_bankarray_csrbank8_rxempty_re; wire basesoc_csr_bankarray_csrbank8_rxempty_r; wire basesoc_csr_bankarray_csrbank8_rxempty_we; wire basesoc_csr_bankarray_csrbank8_rxempty_w; wire basesoc_csr_bankarray_csrbank8_ev_status_re; wire [1:0] basesoc_csr_bankarray_csrbank8_ev_status_r; wire basesoc_csr_bankarray_csrbank8_ev_status_we; wire [1:0] basesoc_csr_bankarray_csrbank8_ev_status_w; wire basesoc_csr_bankarray_csrbank8_ev_pending_re; wire [1:0] basesoc_csr_bankarray_csrbank8_ev_pending_r; wire basesoc_csr_bankarray_csrbank8_ev_pending_we; wire [1:0] basesoc_csr_bankarray_csrbank8_ev_pending_w; wire basesoc_csr_bankarray_csrbank8_ev_enable0_re; wire [1:0] basesoc_csr_bankarray_csrbank8_ev_enable0_r; wire basesoc_csr_bankarray_csrbank8_ev_enable0_we; wire [1:0] basesoc_csr_bankarray_csrbank8_ev_enable0_w; wire basesoc_csr_bankarray_csrbank8_txempty_re; wire basesoc_csr_bankarray_csrbank8_txempty_r; wire basesoc_csr_bankarray_csrbank8_txempty_we; wire basesoc_csr_bankarray_csrbank8_txempty_w; wire basesoc_csr_bankarray_csrbank8_rxfull_re; wire basesoc_csr_bankarray_csrbank8_rxfull_r; wire basesoc_csr_bankarray_csrbank8_rxfull_we; wire basesoc_csr_bankarray_csrbank8_rxfull_w; wire basesoc_csr_bankarray_csrbank8_sel; wire [13:0] basesoc_csr_bankarray_interface9_bank_bus_adr; wire basesoc_csr_bankarray_interface9_bank_bus_we; wire [31:0] basesoc_csr_bankarray_interface9_bank_bus_dat_w; reg [31:0] basesoc_csr_bankarray_interface9_bank_bus_dat_r = 32'd0; wire basesoc_csr_bankarray_csrbank9_tuning_word0_re; wire [31:0] basesoc_csr_bankarray_csrbank9_tuning_word0_r; wire basesoc_csr_bankarray_csrbank9_tuning_word0_we; wire [31:0] basesoc_csr_bankarray_csrbank9_tuning_word0_w; wire basesoc_csr_bankarray_csrbank9_sel; wire [13:0] basesoc_csr_interconnect_adr; wire basesoc_csr_interconnect_we; wire [31:0] basesoc_csr_interconnect_dat_w; wire [31:0] basesoc_csr_interconnect_dat_r; reg [1:0] basesoc_state = 2'd0; reg [1:0] basesoc_next_state = 2'd0; reg [31:0] basesoc_basesoc_dat_w_basesoc_next_value0 = 32'd0; reg basesoc_basesoc_dat_w_basesoc_next_value_ce0 = 1'd0; reg [13:0] basesoc_basesoc_adr_basesoc_next_value1 = 14'd0; reg basesoc_basesoc_adr_basesoc_next_value_ce1 = 1'd0; reg basesoc_basesoc_we_basesoc_next_value2 = 1'd0; reg basesoc_basesoc_we_basesoc_next_value_ce2 = 1'd0; reg rhs_array_muxed0 = 1'd0; reg [13:0] rhs_array_muxed1 = 14'd0; reg [2:0] rhs_array_muxed2 = 3'd0; reg rhs_array_muxed3 = 1'd0; reg rhs_array_muxed4 = 1'd0; reg rhs_array_muxed5 = 1'd0; reg t_array_muxed0 = 1'd0; reg t_array_muxed1 = 1'd0; reg t_array_muxed2 = 1'd0; reg rhs_array_muxed6 = 1'd0; reg [13:0] rhs_array_muxed7 = 14'd0; reg [2:0] rhs_array_muxed8 = 3'd0; reg rhs_array_muxed9 = 1'd0; reg rhs_array_muxed10 = 1'd0; reg rhs_array_muxed11 = 1'd0; reg t_array_muxed3 = 1'd0; reg t_array_muxed4 = 1'd0; reg t_array_muxed5 = 1'd0; reg [20:0] rhs_array_muxed12 = 21'd0; reg rhs_array_muxed13 = 1'd0; reg rhs_array_muxed14 = 1'd0; reg [20:0] rhs_array_muxed15 = 21'd0; reg rhs_array_muxed16 = 1'd0; reg rhs_array_muxed17 = 1'd0; reg [20:0] rhs_array_muxed18 = 21'd0; reg rhs_array_muxed19 = 1'd0; reg rhs_array_muxed20 = 1'd0; reg [20:0] rhs_array_muxed21 = 21'd0; reg rhs_array_muxed22 = 1'd0; reg rhs_array_muxed23 = 1'd0; reg [20:0] rhs_array_muxed24 = 21'd0; reg rhs_array_muxed25 = 1'd0; reg rhs_array_muxed26 = 1'd0; reg [20:0] rhs_array_muxed27 = 21'd0; reg rhs_array_muxed28 = 1'd0; reg rhs_array_muxed29 = 1'd0; reg [20:0] rhs_array_muxed30 = 21'd0; reg rhs_array_muxed31 = 1'd0; reg rhs_array_muxed32 = 1'd0; reg [20:0] rhs_array_muxed33 = 21'd0; reg rhs_array_muxed34 = 1'd0; reg rhs_array_muxed35 = 1'd0; reg [31:0] rhs_array_muxed36 = 32'd0; reg [31:0] rhs_array_muxed37 = 32'd0; reg [3:0] rhs_array_muxed38 = 4'd0; reg rhs_array_muxed39 = 1'd0; reg rhs_array_muxed40 = 1'd0; reg rhs_array_muxed41 = 1'd0; reg [2:0] rhs_array_muxed42 = 3'd0; reg [1:0] rhs_array_muxed43 = 2'd0; reg [2:0] array_muxed0 = 3'd0; reg [13:0] array_muxed1 = 14'd0; reg array_muxed2 = 1'd0; reg array_muxed3 = 1'd0; reg array_muxed4 = 1'd0; reg array_muxed5 = 1'd0; reg array_muxed6 = 1'd0; reg [2:0] array_muxed7 = 3'd0; reg [13:0] array_muxed8 = 14'd0; reg array_muxed9 = 1'd0; reg array_muxed10 = 1'd0; reg array_muxed11 = 1'd0; reg array_muxed12 = 1'd0; reg array_muxed13 = 1'd0; reg [2:0] array_muxed14 = 3'd0; reg [13:0] array_muxed15 = 14'd0; reg array_muxed16 = 1'd0; reg array_muxed17 = 1'd0; reg array_muxed18 = 1'd0; reg array_muxed19 = 1'd0; reg array_muxed20 = 1'd0; reg [2:0] array_muxed21 = 3'd0; reg [13:0] array_muxed22 = 14'd0; reg array_muxed23 = 1'd0; reg array_muxed24 = 1'd0; reg array_muxed25 = 1'd0; reg array_muxed26 = 1'd0; reg array_muxed27 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0; wire xilinxasyncresetsynchronizerimpl0; wire xilinxasyncresetsynchronizerimpl0_rst_meta; wire xilinxasyncresetsynchronizerimpl1; wire xilinxasyncresetsynchronizerimpl1_rst_meta; wire xilinxasyncresetsynchronizerimpl1_expr; wire xilinxasyncresetsynchronizerimpl2; wire xilinxasyncresetsynchronizerimpl2_rst_meta; wire xilinxasyncresetsynchronizerimpl2_expr; wire xilinxasyncresetsynchronizerimpl3; wire xilinxasyncresetsynchronizerimpl3_rst_meta; wire xilinxasyncresetsynchronizerimpl4; wire xilinxasyncresetsynchronizerimpl4_rst_meta; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl4_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl4_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl5_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl5_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl6_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl6_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl7_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl7_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl8_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl8_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl9_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl9_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl10_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl10_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl11_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl11_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl12_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl12_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl13_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl13_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl14_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl14_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl15_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl15_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl16_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl16_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl17_regs0 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl17_regs1 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl18_regs0 = 2'd0; (* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl18_regs1 = 2'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl19_regs0 = 2'd0; (* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl19_regs1 = 2'd0; wire xilinxasyncresetsynchronizerimpl5; wire xilinxasyncresetsynchronizerimpl5_rst_meta; wire xilinxasyncresetsynchronizerimpl6; wire xilinxasyncresetsynchronizerimpl6_rst_meta; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl20_regs0 = 4'd0; (* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl20_regs1 = 4'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl21_regs0 = 4'd0; (* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl21_regs1 = 4'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl22_regs0 = 4'd0; (* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl22_regs1 = 4'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl23_regs0 = 4'd0; (* async_reg = "true", dont_touch = "true" *) reg [3:0] xilinxmultiregimpl23_regs1 = 4'd0; assign cpu_reset_1 = soccontroller_reset; assign crg_rst = soccontroller_reset_re; assign soccontroller_bus_error = basesoc_error; always @(*) begin cpu_interrupt <= 32'd0; cpu_interrupt[1] <= timer_irq; cpu_interrupt[0] <= uart_irq; end assign soccontroller_reset = soccontroller_reset_re; assign soccontroller_bus_errors_status = soccontroller_bus_errors; assign basesoc_adr = basesoc_ram_bus_adr[13:0]; assign basesoc_ram_bus_dat_r = basesoc_dat_r; always @(*) begin ram_we <= 4'd0; ram_we[0] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[0]); ram_we[1] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[1]); ram_we[2] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[2]); ram_we[3] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[3]); end assign ram_adr = ram_bus_ram_bus_adr[10:0]; assign ram_bus_ram_bus_dat_r = ram_dat_r; assign ram_dat_w = ram_bus_ram_bus_dat_w; assign uart_uart_sink_valid = uart_phy_source_valid; assign uart_phy_source_ready = uart_uart_sink_ready; assign uart_uart_sink_first = uart_phy_source_first; assign uart_uart_sink_last = uart_phy_source_last; assign uart_uart_sink_payload_data = uart_phy_source_payload_data; assign uart_phy_sink_valid = uart_uart_source_valid; assign uart_uart_source_ready = uart_phy_sink_ready; assign uart_phy_sink_first = uart_uart_source_first; assign uart_phy_sink_last = uart_uart_source_last; assign uart_phy_sink_payload_data = uart_uart_source_payload_data; assign uart_tx_fifo_sink_valid = uart_rxtx_re; assign uart_tx_fifo_sink_payload_data = uart_rxtx_r; assign uart_txfull_status = (~uart_tx_fifo_sink_ready); assign uart_txempty_status = (~uart_tx_fifo_source_valid); assign uart_uart_source_valid = uart_tx_fifo_source_valid; assign uart_tx_fifo_source_ready = uart_uart_source_ready; assign uart_uart_source_first = uart_tx_fifo_source_first; assign uart_uart_source_last = uart_tx_fifo_source_last; assign uart_uart_source_payload_data = uart_tx_fifo_source_payload_data; assign uart_tx_trigger = (~uart_tx_fifo_sink_ready); assign uart_rx_fifo_sink_valid = uart_uart_sink_valid; assign uart_uart_sink_ready = uart_rx_fifo_sink_ready; assign uart_rx_fifo_sink_first = uart_uart_sink_first; assign uart_rx_fifo_sink_last = uart_uart_sink_last; assign uart_rx_fifo_sink_payload_data = uart_uart_sink_payload_data; assign uart_rxempty_status = (~uart_rx_fifo_source_valid); assign uart_rxfull_status = (~uart_rx_fifo_sink_ready); assign uart_rxtx_w = uart_rx_fifo_source_payload_data; assign uart_rx_fifo_source_ready = (uart_rx_clear | (1'd0 & uart_rxtx_we)); assign uart_rx_trigger = (~uart_rx_fifo_source_valid); assign uart_tx0 = uart_tx_status; assign uart_tx1 = uart_tx_pending; always @(*) begin uart_tx_clear <= 1'd0; if ((uart_pending_re & uart_pending_r[0])) begin uart_tx_clear <= 1'd1; end end assign uart_rx0 = uart_rx_status; assign uart_rx1 = uart_rx_pending; always @(*) begin uart_rx_clear <= 1'd0; if ((uart_pending_re & uart_pending_r[1])) begin uart_rx_clear <= 1'd1; end end assign uart_irq = ((uart_pending_status[0] & uart_enable_storage[0]) | (uart_pending_status[1] & uart_enable_storage[1])); assign uart_tx_status = uart_tx_trigger; assign uart_rx_status = uart_rx_trigger; assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_last, uart_tx_fifo_fifo_in_first, uart_tx_fifo_fifo_in_payload_data}; assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout; assign uart_tx_fifo_sink_ready = uart_tx_fifo_syncfifo_writable; assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_valid; assign uart_tx_fifo_fifo_in_first = uart_tx_fifo_sink_first; assign uart_tx_fifo_fifo_in_last = uart_tx_fifo_sink_last; assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data; assign uart_tx_fifo_source_valid = uart_tx_fifo_readable; assign uart_tx_fifo_source_first = uart_tx_fifo_fifo_out_first; assign uart_tx_fifo_source_last = uart_tx_fifo_fifo_out_last; assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data; assign uart_tx_fifo_re = uart_tx_fifo_source_ready; assign uart_tx_fifo_syncfifo_re = (uart_tx_fifo_syncfifo_readable & ((~uart_tx_fifo_readable) | uart_tx_fifo_re)); assign uart_tx_fifo_level1 = (uart_tx_fifo_level0 + uart_tx_fifo_readable); always @(*) begin uart_tx_fifo_wrport_adr <= 4'd0; if (uart_tx_fifo_replace) begin uart_tx_fifo_wrport_adr <= (uart_tx_fifo_produce - 1'd1); end else begin uart_tx_fifo_wrport_adr <= uart_tx_fifo_produce; end end assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din; assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace)); assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re); assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume; assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r; assign uart_tx_fifo_rdport_re = uart_tx_fifo_do_read; assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level0 != 5'd16); assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level0 != 1'd0); assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_last, uart_rx_fifo_fifo_in_first, uart_rx_fifo_fifo_in_payload_data}; assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout; assign uart_rx_fifo_sink_ready = uart_rx_fifo_syncfifo_writable; assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_valid; assign uart_rx_fifo_fifo_in_first = uart_rx_fifo_sink_first; assign uart_rx_fifo_fifo_in_last = uart_rx_fifo_sink_last; assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data; assign uart_rx_fifo_source_valid = uart_rx_fifo_readable; assign uart_rx_fifo_source_first = uart_rx_fifo_fifo_out_first; assign uart_rx_fifo_source_last = uart_rx_fifo_fifo_out_last; assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data; assign uart_rx_fifo_re = uart_rx_fifo_source_ready; assign uart_rx_fifo_syncfifo_re = (uart_rx_fifo_syncfifo_readable & ((~uart_rx_fifo_readable) | uart_rx_fifo_re)); assign uart_rx_fifo_level1 = (uart_rx_fifo_level0 + uart_rx_fifo_readable); always @(*) begin uart_rx_fifo_wrport_adr <= 4'd0; if (uart_rx_fifo_replace) begin uart_rx_fifo_wrport_adr <= (uart_rx_fifo_produce - 1'd1); end else begin uart_rx_fifo_wrport_adr <= uart_rx_fifo_produce; end end assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din; assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace)); assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re); assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume; assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r; assign uart_rx_fifo_rdport_re = uart_rx_fifo_do_read; assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level0 != 5'd16); assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level0 != 1'd0); assign timer_zero_trigger = (timer_value != 1'd0); assign timer_zero0 = timer_zero_status; assign timer_zero1 = timer_zero_pending; always @(*) begin timer_zero_clear <= 1'd0; if ((timer_pending_re & timer_pending_r)) begin timer_zero_clear <= 1'd1; end end assign timer_irq = (timer_pending_status & timer_enable_storage); assign timer_zero_status = timer_zero_trigger; assign crg_reset = ((~cpu_reset) | crg_rst); assign crg_clkin = clk100; assign sys_clk = crg_clkout_buf0; assign sys4x_clk = crg_clkout_buf1; assign sys4x_dqs_clk = crg_clkout_buf2; assign idelay_clk = crg_clkout_buf3; assign clk100_clk = crg_clkout_buf4; assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); always @(*) begin a7ddrphy_dfi_p0_rddata <= 32'd0; a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; end always @(*) begin a7ddrphy_dfi_p1_rddata <= 32'd0; a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; end always @(*) begin a7ddrphy_dfi_p2_rddata <= 32'd0; a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; end always @(*) begin a7ddrphy_dfi_p3_rddata <= 32'd0; a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; end assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; always @(*) begin a7ddrphy_dqs_oe <= 1'd0; if (a7ddrphy_wlevel_en_storage) begin a7ddrphy_dqs_oe <= 1'd1; end else begin a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; end end assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); always @(*) begin a7ddrphy_dqspattern_o0 <= 8'd0; a7ddrphy_dqspattern_o0 <= 7'd85; if (a7ddrphy_dqspattern0) begin a7ddrphy_dqspattern_o0 <= 5'd21; end if (a7ddrphy_dqspattern1) begin a7ddrphy_dqspattern_o0 <= 7'd84; end if (a7ddrphy_wlevel_en_storage) begin a7ddrphy_dqspattern_o0 <= 1'd0; if (a7ddrphy_wlevel_strobe_re) begin a7ddrphy_dqspattern_o0 <= 1'd1; end end end always @(*) begin a7ddrphy_bitslip00 <= 8'd0; case (a7ddrphy_bitslip0_value0) 1'd0: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip10 <= 8'd0; case (a7ddrphy_bitslip1_value0) 1'd0: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip01 <= 8'd0; case (a7ddrphy_bitslip0_value1) 1'd0: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip11 <= 8'd0; case (a7ddrphy_bitslip1_value1) 1'd0: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip02 <= 8'd0; case (a7ddrphy_bitslip0_value2) 1'd0: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip04 <= 8'd0; case (a7ddrphy_bitslip0_value3) 1'd0: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip12 <= 8'd0; case (a7ddrphy_bitslip1_value2) 1'd0: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip14 <= 8'd0; case (a7ddrphy_bitslip1_value3) 1'd0: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip20 <= 8'd0; case (a7ddrphy_bitslip2_value0) 1'd0: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip22 <= 8'd0; case (a7ddrphy_bitslip2_value1) 1'd0: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip30 <= 8'd0; case (a7ddrphy_bitslip3_value0) 1'd0: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip32 <= 8'd0; case (a7ddrphy_bitslip3_value1) 1'd0: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip40 <= 8'd0; case (a7ddrphy_bitslip4_value0) 1'd0: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip42 <= 8'd0; case (a7ddrphy_bitslip4_value1) 1'd0: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip50 <= 8'd0; case (a7ddrphy_bitslip5_value0) 1'd0: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip52 <= 8'd0; case (a7ddrphy_bitslip5_value1) 1'd0: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip60 <= 8'd0; case (a7ddrphy_bitslip6_value0) 1'd0: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip62 <= 8'd0; case (a7ddrphy_bitslip6_value1) 1'd0: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip70 <= 8'd0; case (a7ddrphy_bitslip7_value0) 1'd0: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip72 <= 8'd0; case (a7ddrphy_bitslip7_value1) 1'd0: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip80 <= 8'd0; case (a7ddrphy_bitslip8_value0) 1'd0: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip82 <= 8'd0; case (a7ddrphy_bitslip8_value1) 1'd0: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip90 <= 8'd0; case (a7ddrphy_bitslip9_value0) 1'd0: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip92 <= 8'd0; case (a7ddrphy_bitslip9_value1) 1'd0: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip100 <= 8'd0; case (a7ddrphy_bitslip10_value0) 1'd0: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip102 <= 8'd0; case (a7ddrphy_bitslip10_value1) 1'd0: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip110 <= 8'd0; case (a7ddrphy_bitslip11_value0) 1'd0: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip112 <= 8'd0; case (a7ddrphy_bitslip11_value1) 1'd0: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip120 <= 8'd0; case (a7ddrphy_bitslip12_value0) 1'd0: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip122 <= 8'd0; case (a7ddrphy_bitslip12_value1) 1'd0: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip130 <= 8'd0; case (a7ddrphy_bitslip13_value0) 1'd0: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip132 <= 8'd0; case (a7ddrphy_bitslip13_value1) 1'd0: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip140 <= 8'd0; case (a7ddrphy_bitslip14_value0) 1'd0: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip142 <= 8'd0; case (a7ddrphy_bitslip14_value1) 1'd0: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip150 <= 8'd0; case (a7ddrphy_bitslip15_value0) 1'd0: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip152 <= 8'd0; case (a7ddrphy_bitslip15_value1) 1'd0: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; end endcase end assign a7ddrphy_dfi_p0_address = sdram_master_p0_address; assign a7ddrphy_dfi_p0_bank = sdram_master_p0_bank; assign a7ddrphy_dfi_p0_cas_n = sdram_master_p0_cas_n; assign a7ddrphy_dfi_p0_cs_n = sdram_master_p0_cs_n; assign a7ddrphy_dfi_p0_ras_n = sdram_master_p0_ras_n; assign a7ddrphy_dfi_p0_we_n = sdram_master_p0_we_n; assign a7ddrphy_dfi_p0_cke = sdram_master_p0_cke; assign a7ddrphy_dfi_p0_odt = sdram_master_p0_odt; assign a7ddrphy_dfi_p0_reset_n = sdram_master_p0_reset_n; assign a7ddrphy_dfi_p0_act_n = sdram_master_p0_act_n; assign a7ddrphy_dfi_p0_wrdata = sdram_master_p0_wrdata; assign a7ddrphy_dfi_p0_wrdata_en = sdram_master_p0_wrdata_en; assign a7ddrphy_dfi_p0_wrdata_mask = sdram_master_p0_wrdata_mask; assign a7ddrphy_dfi_p0_rddata_en = sdram_master_p0_rddata_en; assign sdram_master_p0_rddata = a7ddrphy_dfi_p0_rddata; assign sdram_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; assign a7ddrphy_dfi_p1_address = sdram_master_p1_address; assign a7ddrphy_dfi_p1_bank = sdram_master_p1_bank; assign a7ddrphy_dfi_p1_cas_n = sdram_master_p1_cas_n; assign a7ddrphy_dfi_p1_cs_n = sdram_master_p1_cs_n; assign a7ddrphy_dfi_p1_ras_n = sdram_master_p1_ras_n; assign a7ddrphy_dfi_p1_we_n = sdram_master_p1_we_n; assign a7ddrphy_dfi_p1_cke = sdram_master_p1_cke; assign a7ddrphy_dfi_p1_odt = sdram_master_p1_odt; assign a7ddrphy_dfi_p1_reset_n = sdram_master_p1_reset_n; assign a7ddrphy_dfi_p1_act_n = sdram_master_p1_act_n; assign a7ddrphy_dfi_p1_wrdata = sdram_master_p1_wrdata; assign a7ddrphy_dfi_p1_wrdata_en = sdram_master_p1_wrdata_en; assign a7ddrphy_dfi_p1_wrdata_mask = sdram_master_p1_wrdata_mask; assign a7ddrphy_dfi_p1_rddata_en = sdram_master_p1_rddata_en; assign sdram_master_p1_rddata = a7ddrphy_dfi_p1_rddata; assign sdram_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; assign a7ddrphy_dfi_p2_address = sdram_master_p2_address; assign a7ddrphy_dfi_p2_bank = sdram_master_p2_bank; assign a7ddrphy_dfi_p2_cas_n = sdram_master_p2_cas_n; assign a7ddrphy_dfi_p2_cs_n = sdram_master_p2_cs_n; assign a7ddrphy_dfi_p2_ras_n = sdram_master_p2_ras_n; assign a7ddrphy_dfi_p2_we_n = sdram_master_p2_we_n; assign a7ddrphy_dfi_p2_cke = sdram_master_p2_cke; assign a7ddrphy_dfi_p2_odt = sdram_master_p2_odt; assign a7ddrphy_dfi_p2_reset_n = sdram_master_p2_reset_n; assign a7ddrphy_dfi_p2_act_n = sdram_master_p2_act_n; assign a7ddrphy_dfi_p2_wrdata = sdram_master_p2_wrdata; assign a7ddrphy_dfi_p2_wrdata_en = sdram_master_p2_wrdata_en; assign a7ddrphy_dfi_p2_wrdata_mask = sdram_master_p2_wrdata_mask; assign a7ddrphy_dfi_p2_rddata_en = sdram_master_p2_rddata_en; assign sdram_master_p2_rddata = a7ddrphy_dfi_p2_rddata; assign sdram_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; assign a7ddrphy_dfi_p3_address = sdram_master_p3_address; assign a7ddrphy_dfi_p3_bank = sdram_master_p3_bank; assign a7ddrphy_dfi_p3_cas_n = sdram_master_p3_cas_n; assign a7ddrphy_dfi_p3_cs_n = sdram_master_p3_cs_n; assign a7ddrphy_dfi_p3_ras_n = sdram_master_p3_ras_n; assign a7ddrphy_dfi_p3_we_n = sdram_master_p3_we_n; assign a7ddrphy_dfi_p3_cke = sdram_master_p3_cke; assign a7ddrphy_dfi_p3_odt = sdram_master_p3_odt; assign a7ddrphy_dfi_p3_reset_n = sdram_master_p3_reset_n; assign a7ddrphy_dfi_p3_act_n = sdram_master_p3_act_n; assign a7ddrphy_dfi_p3_wrdata = sdram_master_p3_wrdata; assign a7ddrphy_dfi_p3_wrdata_en = sdram_master_p3_wrdata_en; assign a7ddrphy_dfi_p3_wrdata_mask = sdram_master_p3_wrdata_mask; assign a7ddrphy_dfi_p3_rddata_en = sdram_master_p3_rddata_en; assign sdram_master_p3_rddata = a7ddrphy_dfi_p3_rddata; assign sdram_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; assign sdram_slave_p0_address = sdram_dfi_p0_address; assign sdram_slave_p0_bank = sdram_dfi_p0_bank; assign sdram_slave_p0_cas_n = sdram_dfi_p0_cas_n; assign sdram_slave_p0_cs_n = sdram_dfi_p0_cs_n; assign sdram_slave_p0_ras_n = sdram_dfi_p0_ras_n; assign sdram_slave_p0_we_n = sdram_dfi_p0_we_n; assign sdram_slave_p0_cke = sdram_dfi_p0_cke; assign sdram_slave_p0_odt = sdram_dfi_p0_odt; assign sdram_slave_p0_reset_n = sdram_dfi_p0_reset_n; assign sdram_slave_p0_act_n = sdram_dfi_p0_act_n; assign sdram_slave_p0_wrdata = sdram_dfi_p0_wrdata; assign sdram_slave_p0_wrdata_en = sdram_dfi_p0_wrdata_en; assign sdram_slave_p0_wrdata_mask = sdram_dfi_p0_wrdata_mask; assign sdram_slave_p0_rddata_en = sdram_dfi_p0_rddata_en; assign sdram_dfi_p0_rddata = sdram_slave_p0_rddata; assign sdram_dfi_p0_rddata_valid = sdram_slave_p0_rddata_valid; assign sdram_slave_p1_address = sdram_dfi_p1_address; assign sdram_slave_p1_bank = sdram_dfi_p1_bank; assign sdram_slave_p1_cas_n = sdram_dfi_p1_cas_n; assign sdram_slave_p1_cs_n = sdram_dfi_p1_cs_n; assign sdram_slave_p1_ras_n = sdram_dfi_p1_ras_n; assign sdram_slave_p1_we_n = sdram_dfi_p1_we_n; assign sdram_slave_p1_cke = sdram_dfi_p1_cke; assign sdram_slave_p1_odt = sdram_dfi_p1_odt; assign sdram_slave_p1_reset_n = sdram_dfi_p1_reset_n; assign sdram_slave_p1_act_n = sdram_dfi_p1_act_n; assign sdram_slave_p1_wrdata = sdram_dfi_p1_wrdata; assign sdram_slave_p1_wrdata_en = sdram_dfi_p1_wrdata_en; assign sdram_slave_p1_wrdata_mask = sdram_dfi_p1_wrdata_mask; assign sdram_slave_p1_rddata_en = sdram_dfi_p1_rddata_en; assign sdram_dfi_p1_rddata = sdram_slave_p1_rddata; assign sdram_dfi_p1_rddata_valid = sdram_slave_p1_rddata_valid; assign sdram_slave_p2_address = sdram_dfi_p2_address; assign sdram_slave_p2_bank = sdram_dfi_p2_bank; assign sdram_slave_p2_cas_n = sdram_dfi_p2_cas_n; assign sdram_slave_p2_cs_n = sdram_dfi_p2_cs_n; assign sdram_slave_p2_ras_n = sdram_dfi_p2_ras_n; assign sdram_slave_p2_we_n = sdram_dfi_p2_we_n; assign sdram_slave_p2_cke = sdram_dfi_p2_cke; assign sdram_slave_p2_odt = sdram_dfi_p2_odt; assign sdram_slave_p2_reset_n = sdram_dfi_p2_reset_n; assign sdram_slave_p2_act_n = sdram_dfi_p2_act_n; assign sdram_slave_p2_wrdata = sdram_dfi_p2_wrdata; assign sdram_slave_p2_wrdata_en = sdram_dfi_p2_wrdata_en; assign sdram_slave_p2_wrdata_mask = sdram_dfi_p2_wrdata_mask; assign sdram_slave_p2_rddata_en = sdram_dfi_p2_rddata_en; assign sdram_dfi_p2_rddata = sdram_slave_p2_rddata; assign sdram_dfi_p2_rddata_valid = sdram_slave_p2_rddata_valid; assign sdram_slave_p3_address = sdram_dfi_p3_address; assign sdram_slave_p3_bank = sdram_dfi_p3_bank; assign sdram_slave_p3_cas_n = sdram_dfi_p3_cas_n; assign sdram_slave_p3_cs_n = sdram_dfi_p3_cs_n; assign sdram_slave_p3_ras_n = sdram_dfi_p3_ras_n; assign sdram_slave_p3_we_n = sdram_dfi_p3_we_n; assign sdram_slave_p3_cke = sdram_dfi_p3_cke; assign sdram_slave_p3_odt = sdram_dfi_p3_odt; assign sdram_slave_p3_reset_n = sdram_dfi_p3_reset_n; assign sdram_slave_p3_act_n = sdram_dfi_p3_act_n; assign sdram_slave_p3_wrdata = sdram_dfi_p3_wrdata; assign sdram_slave_p3_wrdata_en = sdram_dfi_p3_wrdata_en; assign sdram_slave_p3_wrdata_mask = sdram_dfi_p3_wrdata_mask; assign sdram_slave_p3_rddata_en = sdram_dfi_p3_rddata_en; assign sdram_dfi_p3_rddata = sdram_slave_p3_rddata; assign sdram_dfi_p3_rddata_valid = sdram_slave_p3_rddata_valid; always @(*) begin sdram_master_p0_address <= 14'd0; sdram_master_p0_bank <= 3'd0; sdram_master_p0_cas_n <= 1'd1; sdram_master_p0_cs_n <= 1'd1; sdram_master_p0_ras_n <= 1'd1; sdram_master_p0_we_n <= 1'd1; sdram_master_p0_cke <= 1'd0; sdram_master_p0_odt <= 1'd0; sdram_master_p0_reset_n <= 1'd0; sdram_master_p0_act_n <= 1'd1; sdram_master_p0_wrdata <= 32'd0; sdram_inti_p1_rddata <= 32'd0; sdram_master_p0_wrdata_en <= 1'd0; sdram_inti_p1_rddata_valid <= 1'd0; sdram_master_p0_wrdata_mask <= 4'd0; sdram_master_p0_rddata_en <= 1'd0; sdram_master_p1_address <= 14'd0; sdram_master_p1_bank <= 3'd0; sdram_master_p1_cas_n <= 1'd1; sdram_master_p1_cs_n <= 1'd1; sdram_master_p1_ras_n <= 1'd1; sdram_master_p1_we_n <= 1'd1; sdram_master_p1_cke <= 1'd0; sdram_master_p1_odt <= 1'd0; sdram_master_p1_reset_n <= 1'd0; sdram_master_p1_act_n <= 1'd1; sdram_master_p1_wrdata <= 32'd0; sdram_inti_p2_rddata <= 32'd0; sdram_master_p1_wrdata_en <= 1'd0; sdram_inti_p2_rddata_valid <= 1'd0; sdram_master_p1_wrdata_mask <= 4'd0; sdram_master_p1_rddata_en <= 1'd0; sdram_master_p2_address <= 14'd0; sdram_master_p2_bank <= 3'd0; sdram_master_p2_cas_n <= 1'd1; sdram_master_p2_cs_n <= 1'd1; sdram_master_p2_ras_n <= 1'd1; sdram_master_p2_we_n <= 1'd1; sdram_master_p2_cke <= 1'd0; sdram_master_p2_odt <= 1'd0; sdram_master_p2_reset_n <= 1'd0; sdram_master_p2_act_n <= 1'd1; sdram_master_p2_wrdata <= 32'd0; sdram_inti_p3_rddata <= 32'd0; sdram_master_p2_wrdata_en <= 1'd0; sdram_inti_p3_rddata_valid <= 1'd0; sdram_master_p2_wrdata_mask <= 4'd0; sdram_master_p2_rddata_en <= 1'd0; sdram_master_p3_address <= 14'd0; sdram_master_p3_bank <= 3'd0; sdram_master_p3_cas_n <= 1'd1; sdram_master_p3_cs_n <= 1'd1; sdram_master_p3_ras_n <= 1'd1; sdram_master_p3_we_n <= 1'd1; sdram_master_p3_cke <= 1'd0; sdram_master_p3_odt <= 1'd0; sdram_master_p3_reset_n <= 1'd0; sdram_master_p3_act_n <= 1'd1; sdram_master_p3_wrdata <= 32'd0; sdram_master_p3_wrdata_en <= 1'd0; sdram_master_p3_wrdata_mask <= 4'd0; sdram_master_p3_rddata_en <= 1'd0; sdram_slave_p0_rddata <= 32'd0; sdram_slave_p0_rddata_valid <= 1'd0; sdram_slave_p1_rddata <= 32'd0; sdram_slave_p1_rddata_valid <= 1'd0; sdram_slave_p2_rddata <= 32'd0; sdram_slave_p2_rddata_valid <= 1'd0; sdram_slave_p3_rddata <= 32'd0; sdram_slave_p3_rddata_valid <= 1'd0; sdram_inti_p0_rddata <= 32'd0; sdram_inti_p0_rddata_valid <= 1'd0; if (sdram_sel) begin sdram_master_p0_address <= sdram_slave_p0_address; sdram_master_p0_bank <= sdram_slave_p0_bank; sdram_master_p0_cas_n <= sdram_slave_p0_cas_n; sdram_master_p0_cs_n <= sdram_slave_p0_cs_n; sdram_master_p0_ras_n <= sdram_slave_p0_ras_n; sdram_master_p0_we_n <= sdram_slave_p0_we_n; sdram_master_p0_cke <= sdram_slave_p0_cke; sdram_master_p0_odt <= sdram_slave_p0_odt; sdram_master_p0_reset_n <= sdram_slave_p0_reset_n; sdram_master_p0_act_n <= sdram_slave_p0_act_n; sdram_master_p0_wrdata <= sdram_slave_p0_wrdata; sdram_master_p0_wrdata_en <= sdram_slave_p0_wrdata_en; sdram_master_p0_wrdata_mask <= sdram_slave_p0_wrdata_mask; sdram_master_p0_rddata_en <= sdram_slave_p0_rddata_en; sdram_slave_p0_rddata <= sdram_master_p0_rddata; sdram_slave_p0_rddata_valid <= sdram_master_p0_rddata_valid; sdram_master_p1_address <= sdram_slave_p1_address; sdram_master_p1_bank <= sdram_slave_p1_bank; sdram_master_p1_cas_n <= sdram_slave_p1_cas_n; sdram_master_p1_cs_n <= sdram_slave_p1_cs_n; sdram_master_p1_ras_n <= sdram_slave_p1_ras_n; sdram_master_p1_we_n <= sdram_slave_p1_we_n; sdram_master_p1_cke <= sdram_slave_p1_cke; sdram_master_p1_odt <= sdram_slave_p1_odt; sdram_master_p1_reset_n <= sdram_slave_p1_reset_n; sdram_master_p1_act_n <= sdram_slave_p1_act_n; sdram_master_p1_wrdata <= sdram_slave_p1_wrdata; sdram_master_p1_wrdata_en <= sdram_slave_p1_wrdata_en; sdram_master_p1_wrdata_mask <= sdram_slave_p1_wrdata_mask; sdram_master_p1_rddata_en <= sdram_slave_p1_rddata_en; sdram_slave_p1_rddata <= sdram_master_p1_rddata; sdram_slave_p1_rddata_valid <= sdram_master_p1_rddata_valid; sdram_master_p2_address <= sdram_slave_p2_address; sdram_master_p2_bank <= sdram_slave_p2_bank; sdram_master_p2_cas_n <= sdram_slave_p2_cas_n; sdram_master_p2_cs_n <= sdram_slave_p2_cs_n; sdram_master_p2_ras_n <= sdram_slave_p2_ras_n; sdram_master_p2_we_n <= sdram_slave_p2_we_n; sdram_master_p2_cke <= sdram_slave_p2_cke; sdram_master_p2_odt <= sdram_slave_p2_odt; sdram_master_p2_reset_n <= sdram_slave_p2_reset_n; sdram_master_p2_act_n <= sdram_slave_p2_act_n; sdram_master_p2_wrdata <= sdram_slave_p2_wrdata; sdram_master_p2_wrdata_en <= sdram_slave_p2_wrdata_en; sdram_master_p2_wrdata_mask <= sdram_slave_p2_wrdata_mask; sdram_master_p2_rddata_en <= sdram_slave_p2_rddata_en; sdram_slave_p2_rddata <= sdram_master_p2_rddata; sdram_slave_p2_rddata_valid <= sdram_master_p2_rddata_valid; sdram_master_p3_address <= sdram_slave_p3_address; sdram_master_p3_bank <= sdram_slave_p3_bank; sdram_master_p3_cas_n <= sdram_slave_p3_cas_n; sdram_master_p3_cs_n <= sdram_slave_p3_cs_n; sdram_master_p3_ras_n <= sdram_slave_p3_ras_n; sdram_master_p3_we_n <= sdram_slave_p3_we_n; sdram_master_p3_cke <= sdram_slave_p3_cke; sdram_master_p3_odt <= sdram_slave_p3_odt; sdram_master_p3_reset_n <= sdram_slave_p3_reset_n; sdram_master_p3_act_n <= sdram_slave_p3_act_n; sdram_master_p3_wrdata <= sdram_slave_p3_wrdata; sdram_master_p3_wrdata_en <= sdram_slave_p3_wrdata_en; sdram_master_p3_wrdata_mask <= sdram_slave_p3_wrdata_mask; sdram_master_p3_rddata_en <= sdram_slave_p3_rddata_en; sdram_slave_p3_rddata <= sdram_master_p3_rddata; sdram_slave_p3_rddata_valid <= sdram_master_p3_rddata_valid; end else begin sdram_master_p0_address <= sdram_inti_p0_address; sdram_master_p0_bank <= sdram_inti_p0_bank; sdram_master_p0_cas_n <= sdram_inti_p0_cas_n; sdram_master_p0_cs_n <= sdram_inti_p0_cs_n; sdram_master_p0_ras_n <= sdram_inti_p0_ras_n; sdram_master_p0_we_n <= sdram_inti_p0_we_n; sdram_master_p0_cke <= sdram_inti_p0_cke; sdram_master_p0_odt <= sdram_inti_p0_odt; sdram_master_p0_reset_n <= sdram_inti_p0_reset_n; sdram_master_p0_act_n <= sdram_inti_p0_act_n; sdram_master_p0_wrdata <= sdram_inti_p0_wrdata; sdram_master_p0_wrdata_en <= sdram_inti_p0_wrdata_en; sdram_master_p0_wrdata_mask <= sdram_inti_p0_wrdata_mask; sdram_master_p0_rddata_en <= sdram_inti_p0_rddata_en; sdram_inti_p0_rddata <= sdram_master_p0_rddata; sdram_inti_p0_rddata_valid <= sdram_master_p0_rddata_valid; sdram_master_p1_address <= sdram_inti_p1_address; sdram_master_p1_bank <= sdram_inti_p1_bank; sdram_master_p1_cas_n <= sdram_inti_p1_cas_n; sdram_master_p1_cs_n <= sdram_inti_p1_cs_n; sdram_master_p1_ras_n <= sdram_inti_p1_ras_n; sdram_master_p1_we_n <= sdram_inti_p1_we_n; sdram_master_p1_cke <= sdram_inti_p1_cke; sdram_master_p1_odt <= sdram_inti_p1_odt; sdram_master_p1_reset_n <= sdram_inti_p1_reset_n; sdram_master_p1_act_n <= sdram_inti_p1_act_n; sdram_master_p1_wrdata <= sdram_inti_p1_wrdata; sdram_master_p1_wrdata_en <= sdram_inti_p1_wrdata_en; sdram_master_p1_wrdata_mask <= sdram_inti_p1_wrdata_mask; sdram_master_p1_rddata_en <= sdram_inti_p1_rddata_en; sdram_inti_p1_rddata <= sdram_master_p1_rddata; sdram_inti_p1_rddata_valid <= sdram_master_p1_rddata_valid; sdram_master_p2_address <= sdram_inti_p2_address; sdram_master_p2_bank <= sdram_inti_p2_bank; sdram_master_p2_cas_n <= sdram_inti_p2_cas_n; sdram_master_p2_cs_n <= sdram_inti_p2_cs_n; sdram_master_p2_ras_n <= sdram_inti_p2_ras_n; sdram_master_p2_we_n <= sdram_inti_p2_we_n; sdram_master_p2_cke <= sdram_inti_p2_cke; sdram_master_p2_odt <= sdram_inti_p2_odt; sdram_master_p2_reset_n <= sdram_inti_p2_reset_n; sdram_master_p2_act_n <= sdram_inti_p2_act_n; sdram_master_p2_wrdata <= sdram_inti_p2_wrdata; sdram_master_p2_wrdata_en <= sdram_inti_p2_wrdata_en; sdram_master_p2_wrdata_mask <= sdram_inti_p2_wrdata_mask; sdram_master_p2_rddata_en <= sdram_inti_p2_rddata_en; sdram_inti_p2_rddata <= sdram_master_p2_rddata; sdram_inti_p2_rddata_valid <= sdram_master_p2_rddata_valid; sdram_master_p3_address <= sdram_inti_p3_address; sdram_master_p3_bank <= sdram_inti_p3_bank; sdram_master_p3_cas_n <= sdram_inti_p3_cas_n; sdram_master_p3_cs_n <= sdram_inti_p3_cs_n; sdram_master_p3_ras_n <= sdram_inti_p3_ras_n; sdram_master_p3_we_n <= sdram_inti_p3_we_n; sdram_master_p3_cke <= sdram_inti_p3_cke; sdram_master_p3_odt <= sdram_inti_p3_odt; sdram_master_p3_reset_n <= sdram_inti_p3_reset_n; sdram_master_p3_act_n <= sdram_inti_p3_act_n; sdram_master_p3_wrdata <= sdram_inti_p3_wrdata; sdram_master_p3_wrdata_en <= sdram_inti_p3_wrdata_en; sdram_master_p3_wrdata_mask <= sdram_inti_p3_wrdata_mask; sdram_master_p3_rddata_en <= sdram_inti_p3_rddata_en; sdram_inti_p3_rddata <= sdram_master_p3_rddata; sdram_inti_p3_rddata_valid <= sdram_master_p3_rddata_valid; end end assign sdram_inti_p0_cke = sdram_cke; assign sdram_inti_p1_cke = sdram_cke; assign sdram_inti_p2_cke = sdram_cke; assign sdram_inti_p3_cke = sdram_cke; assign sdram_inti_p0_odt = sdram_odt; assign sdram_inti_p1_odt = sdram_odt; assign sdram_inti_p2_odt = sdram_odt; assign sdram_inti_p3_odt = sdram_odt; assign sdram_inti_p0_reset_n = sdram_reset_n; assign sdram_inti_p1_reset_n = sdram_reset_n; assign sdram_inti_p2_reset_n = sdram_reset_n; assign sdram_inti_p3_reset_n = sdram_reset_n; always @(*) begin sdram_inti_p0_cas_n <= 1'd1; sdram_inti_p0_cs_n <= 1'd1; sdram_inti_p0_ras_n <= 1'd1; sdram_inti_p0_we_n <= 1'd1; if (sdram_phaseinjector0_command_issue_re) begin sdram_inti_p0_cs_n <= {1{(~sdram_phaseinjector0_command_storage[0])}}; sdram_inti_p0_we_n <= (~sdram_phaseinjector0_command_storage[1]); sdram_inti_p0_cas_n <= (~sdram_phaseinjector0_command_storage[2]); sdram_inti_p0_ras_n <= (~sdram_phaseinjector0_command_storage[3]); end else begin sdram_inti_p0_cs_n <= {1{1'd1}}; sdram_inti_p0_we_n <= 1'd1; sdram_inti_p0_cas_n <= 1'd1; sdram_inti_p0_ras_n <= 1'd1; end end assign sdram_inti_p0_address = sdram_phaseinjector0_address_storage; assign sdram_inti_p0_bank = sdram_phaseinjector0_baddress_storage; assign sdram_inti_p0_wrdata_en = (sdram_phaseinjector0_command_issue_re & sdram_phaseinjector0_command_storage[4]); assign sdram_inti_p0_rddata_en = (sdram_phaseinjector0_command_issue_re & sdram_phaseinjector0_command_storage[5]); assign sdram_inti_p0_wrdata = sdram_phaseinjector0_wrdata_storage; assign sdram_inti_p0_wrdata_mask = 1'd0; always @(*) begin sdram_inti_p1_cas_n <= 1'd1; sdram_inti_p1_cs_n <= 1'd1; sdram_inti_p1_ras_n <= 1'd1; sdram_inti_p1_we_n <= 1'd1; if (sdram_phaseinjector1_command_issue_re) begin sdram_inti_p1_cs_n <= {1{(~sdram_phaseinjector1_command_storage[0])}}; sdram_inti_p1_we_n <= (~sdram_phaseinjector1_command_storage[1]); sdram_inti_p1_cas_n <= (~sdram_phaseinjector1_command_storage[2]); sdram_inti_p1_ras_n <= (~sdram_phaseinjector1_command_storage[3]); end else begin sdram_inti_p1_cs_n <= {1{1'd1}}; sdram_inti_p1_we_n <= 1'd1; sdram_inti_p1_cas_n <= 1'd1; sdram_inti_p1_ras_n <= 1'd1; end end assign sdram_inti_p1_address = sdram_phaseinjector1_address_storage; assign sdram_inti_p1_bank = sdram_phaseinjector1_baddress_storage; assign sdram_inti_p1_wrdata_en = (sdram_phaseinjector1_command_issue_re & sdram_phaseinjector1_command_storage[4]); assign sdram_inti_p1_rddata_en = (sdram_phaseinjector1_command_issue_re & sdram_phaseinjector1_command_storage[5]); assign sdram_inti_p1_wrdata = sdram_phaseinjector1_wrdata_storage; assign sdram_inti_p1_wrdata_mask = 1'd0; always @(*) begin sdram_inti_p2_cas_n <= 1'd1; sdram_inti_p2_cs_n <= 1'd1; sdram_inti_p2_ras_n <= 1'd1; sdram_inti_p2_we_n <= 1'd1; if (sdram_phaseinjector2_command_issue_re) begin sdram_inti_p2_cs_n <= {1{(~sdram_phaseinjector2_command_storage[0])}}; sdram_inti_p2_we_n <= (~sdram_phaseinjector2_command_storage[1]); sdram_inti_p2_cas_n <= (~sdram_phaseinjector2_command_storage[2]); sdram_inti_p2_ras_n <= (~sdram_phaseinjector2_command_storage[3]); end else begin sdram_inti_p2_cs_n <= {1{1'd1}}; sdram_inti_p2_we_n <= 1'd1; sdram_inti_p2_cas_n <= 1'd1; sdram_inti_p2_ras_n <= 1'd1; end end assign sdram_inti_p2_address = sdram_phaseinjector2_address_storage; assign sdram_inti_p2_bank = sdram_phaseinjector2_baddress_storage; assign sdram_inti_p2_wrdata_en = (sdram_phaseinjector2_command_issue_re & sdram_phaseinjector2_command_storage[4]); assign sdram_inti_p2_rddata_en = (sdram_phaseinjector2_command_issue_re & sdram_phaseinjector2_command_storage[5]); assign sdram_inti_p2_wrdata = sdram_phaseinjector2_wrdata_storage; assign sdram_inti_p2_wrdata_mask = 1'd0; always @(*) begin sdram_inti_p3_cas_n <= 1'd1; sdram_inti_p3_cs_n <= 1'd1; sdram_inti_p3_ras_n <= 1'd1; sdram_inti_p3_we_n <= 1'd1; if (sdram_phaseinjector3_command_issue_re) begin sdram_inti_p3_cs_n <= {1{(~sdram_phaseinjector3_command_storage[0])}}; sdram_inti_p3_we_n <= (~sdram_phaseinjector3_command_storage[1]); sdram_inti_p3_cas_n <= (~sdram_phaseinjector3_command_storage[2]); sdram_inti_p3_ras_n <= (~sdram_phaseinjector3_command_storage[3]); end else begin sdram_inti_p3_cs_n <= {1{1'd1}}; sdram_inti_p3_we_n <= 1'd1; sdram_inti_p3_cas_n <= 1'd1; sdram_inti_p3_ras_n <= 1'd1; end end assign sdram_inti_p3_address = sdram_phaseinjector3_address_storage; assign sdram_inti_p3_bank = sdram_phaseinjector3_baddress_storage; assign sdram_inti_p3_wrdata_en = (sdram_phaseinjector3_command_issue_re & sdram_phaseinjector3_command_storage[4]); assign sdram_inti_p3_rddata_en = (sdram_phaseinjector3_command_issue_re & sdram_phaseinjector3_command_storage[5]); assign sdram_inti_p3_wrdata = sdram_phaseinjector3_wrdata_storage; assign sdram_inti_p3_wrdata_mask = 1'd0; assign sdram_bankmachine0_req_valid = sdram_interface_bank0_valid; assign sdram_interface_bank0_ready = sdram_bankmachine0_req_ready; assign sdram_bankmachine0_req_we = sdram_interface_bank0_we; assign sdram_bankmachine0_req_addr = sdram_interface_bank0_addr; assign sdram_interface_bank0_lock = sdram_bankmachine0_req_lock; assign sdram_interface_bank0_wdata_ready = sdram_bankmachine0_req_wdata_ready; assign sdram_interface_bank0_rdata_valid = sdram_bankmachine0_req_rdata_valid; assign sdram_bankmachine1_req_valid = sdram_interface_bank1_valid; assign sdram_interface_bank1_ready = sdram_bankmachine1_req_ready; assign sdram_bankmachine1_req_we = sdram_interface_bank1_we; assign sdram_bankmachine1_req_addr = sdram_interface_bank1_addr; assign sdram_interface_bank1_lock = sdram_bankmachine1_req_lock; assign sdram_interface_bank1_wdata_ready = sdram_bankmachine1_req_wdata_ready; assign sdram_interface_bank1_rdata_valid = sdram_bankmachine1_req_rdata_valid; assign sdram_bankmachine2_req_valid = sdram_interface_bank2_valid; assign sdram_interface_bank2_ready = sdram_bankmachine2_req_ready; assign sdram_bankmachine2_req_we = sdram_interface_bank2_we; assign sdram_bankmachine2_req_addr = sdram_interface_bank2_addr; assign sdram_interface_bank2_lock = sdram_bankmachine2_req_lock; assign sdram_interface_bank2_wdata_ready = sdram_bankmachine2_req_wdata_ready; assign sdram_interface_bank2_rdata_valid = sdram_bankmachine2_req_rdata_valid; assign sdram_bankmachine3_req_valid = sdram_interface_bank3_valid; assign sdram_interface_bank3_ready = sdram_bankmachine3_req_ready; assign sdram_bankmachine3_req_we = sdram_interface_bank3_we; assign sdram_bankmachine3_req_addr = sdram_interface_bank3_addr; assign sdram_interface_bank3_lock = sdram_bankmachine3_req_lock; assign sdram_interface_bank3_wdata_ready = sdram_bankmachine3_req_wdata_ready; assign sdram_interface_bank3_rdata_valid = sdram_bankmachine3_req_rdata_valid; assign sdram_bankmachine4_req_valid = sdram_interface_bank4_valid; assign sdram_interface_bank4_ready = sdram_bankmachine4_req_ready; assign sdram_bankmachine4_req_we = sdram_interface_bank4_we; assign sdram_bankmachine4_req_addr = sdram_interface_bank4_addr; assign sdram_interface_bank4_lock = sdram_bankmachine4_req_lock; assign sdram_interface_bank4_wdata_ready = sdram_bankmachine4_req_wdata_ready; assign sdram_interface_bank4_rdata_valid = sdram_bankmachine4_req_rdata_valid; assign sdram_bankmachine5_req_valid = sdram_interface_bank5_valid; assign sdram_interface_bank5_ready = sdram_bankmachine5_req_ready; assign sdram_bankmachine5_req_we = sdram_interface_bank5_we; assign sdram_bankmachine5_req_addr = sdram_interface_bank5_addr; assign sdram_interface_bank5_lock = sdram_bankmachine5_req_lock; assign sdram_interface_bank5_wdata_ready = sdram_bankmachine5_req_wdata_ready; assign sdram_interface_bank5_rdata_valid = sdram_bankmachine5_req_rdata_valid; assign sdram_bankmachine6_req_valid = sdram_interface_bank6_valid; assign sdram_interface_bank6_ready = sdram_bankmachine6_req_ready; assign sdram_bankmachine6_req_we = sdram_interface_bank6_we; assign sdram_bankmachine6_req_addr = sdram_interface_bank6_addr; assign sdram_interface_bank6_lock = sdram_bankmachine6_req_lock; assign sdram_interface_bank6_wdata_ready = sdram_bankmachine6_req_wdata_ready; assign sdram_interface_bank6_rdata_valid = sdram_bankmachine6_req_rdata_valid; assign sdram_bankmachine7_req_valid = sdram_interface_bank7_valid; assign sdram_interface_bank7_ready = sdram_bankmachine7_req_ready; assign sdram_bankmachine7_req_we = sdram_interface_bank7_we; assign sdram_bankmachine7_req_addr = sdram_interface_bank7_addr; assign sdram_interface_bank7_lock = sdram_bankmachine7_req_lock; assign sdram_interface_bank7_wdata_ready = sdram_bankmachine7_req_wdata_ready; assign sdram_interface_bank7_rdata_valid = sdram_bankmachine7_req_rdata_valid; assign sdram_timer_wait = (~sdram_timer_done0); assign sdram_postponer_req_i = sdram_timer_done0; assign sdram_wants_refresh = sdram_postponer_req_o; assign sdram_wants_zqcs = sdram_zqcs_timer_done0; assign sdram_zqcs_timer_wait = (~sdram_zqcs_executer_done); assign sdram_timer_done1 = (sdram_timer_count1 == 1'd0); assign sdram_timer_done0 = sdram_timer_done1; assign sdram_timer_count0 = sdram_timer_count1; assign sdram_sequencer_start1 = (sdram_sequencer_start0 | (sdram_sequencer_count != 1'd0)); assign sdram_sequencer_done0 = (sdram_sequencer_done1 & (sdram_sequencer_count == 1'd0)); assign sdram_zqcs_timer_done1 = (sdram_zqcs_timer_count1 == 1'd0); assign sdram_zqcs_timer_done0 = sdram_zqcs_timer_done1; assign sdram_zqcs_timer_count0 = sdram_zqcs_timer_count1; always @(*) begin sdram_sequencer_start0 <= 1'd0; sdram_cmd_valid <= 1'd0; subfragments_refresher_next_state <= 2'd0; sdram_zqcs_executer_start <= 1'd0; sdram_cmd_last <= 1'd0; subfragments_refresher_next_state <= subfragments_refresher_state; case (subfragments_refresher_state) 1'd1: begin sdram_cmd_valid <= 1'd1; if (sdram_cmd_ready) begin sdram_sequencer_start0 <= 1'd1; subfragments_refresher_next_state <= 2'd2; end end 2'd2: begin sdram_cmd_valid <= 1'd1; if (sdram_sequencer_done0) begin if (sdram_wants_zqcs) begin sdram_zqcs_executer_start <= 1'd1; subfragments_refresher_next_state <= 2'd3; end else begin sdram_cmd_valid <= 1'd0; sdram_cmd_last <= 1'd1; subfragments_refresher_next_state <= 1'd0; end end end 2'd3: begin sdram_cmd_valid <= 1'd1; if (sdram_zqcs_executer_done) begin sdram_cmd_valid <= 1'd0; sdram_cmd_last <= 1'd1; subfragments_refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin if (sdram_wants_refresh) begin subfragments_refresher_next_state <= 1'd1; end end end endcase end assign sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = sdram_bankmachine0_req_valid; assign sdram_bankmachine0_req_ready = sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine0_req_we; assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine0_req_addr; assign sdram_bankmachine0_cmd_buffer_sink_valid = sdram_bankmachine0_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine0_cmd_buffer_lookahead_source_ready = sdram_bankmachine0_cmd_buffer_sink_ready; assign sdram_bankmachine0_cmd_buffer_sink_first = sdram_bankmachine0_cmd_buffer_lookahead_source_first; assign sdram_bankmachine0_cmd_buffer_sink_last = sdram_bankmachine0_cmd_buffer_lookahead_source_last; assign sdram_bankmachine0_cmd_buffer_sink_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine0_cmd_buffer_sink_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine0_cmd_buffer_source_ready = (sdram_bankmachine0_req_wdata_ready | sdram_bankmachine0_req_rdata_valid); assign sdram_bankmachine0_req_lock = (sdram_bankmachine0_cmd_buffer_lookahead_source_valid | sdram_bankmachine0_cmd_buffer_source_valid); assign sdram_bankmachine0_row_hit = (sdram_bankmachine0_row == sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]); assign sdram_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin sdram_bankmachine0_cmd_payload_a <= 14'd0; if (sdram_bankmachine0_row_col_n_addr_sel) begin sdram_bankmachine0_cmd_payload_a <= sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; end else begin sdram_bankmachine0_cmd_payload_a <= ((sdram_bankmachine0_auto_precharge <<< 4'd10) | {sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign sdram_bankmachine0_twtpcon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_cmd_payload_is_write); assign sdram_bankmachine0_trccon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open); assign sdram_bankmachine0_trascon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open); always @(*) begin sdram_bankmachine0_auto_precharge <= 1'd0; if ((sdram_bankmachine0_cmd_buffer_lookahead_source_valid & sdram_bankmachine0_cmd_buffer_source_valid)) begin if ((sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin sdram_bankmachine0_auto_precharge <= (sdram_bankmachine0_row_close == 1'd0); end end end assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; assign sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine0_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine0_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine0_cmd_buffer_lookahead_source_valid = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; assign sdram_bankmachine0_cmd_buffer_lookahead_source_first = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine0_cmd_buffer_lookahead_source_last = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = sdram_bankmachine0_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine0_cmd_buffer_lookahead_replace) begin sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine0_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | sdram_bankmachine0_cmd_buffer_lookahead_replace)); assign sdram_bankmachine0_cmd_buffer_lookahead_do_read = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine0_cmd_buffer_lookahead_consume; assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine0_cmd_buffer_sink_ready = ((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine0_row_open <= 1'd0; sdram_bankmachine0_row_close <= 1'd0; sdram_bankmachine0_cmd_payload_cas <= 1'd0; sdram_bankmachine0_req_rdata_valid <= 1'd0; sdram_bankmachine0_cmd_payload_ras <= 1'd0; sdram_bankmachine0_cmd_payload_we <= 1'd0; sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine0_cmd_payload_is_read <= 1'd0; sdram_bankmachine0_cmd_payload_is_write <= 1'd0; sdram_bankmachine0_req_wdata_ready <= 1'd0; subfragments_bankmachine0_next_state <= 3'd0; sdram_bankmachine0_refresh_gnt <= 1'd0; sdram_bankmachine0_cmd_valid <= 1'd0; subfragments_bankmachine0_next_state <= subfragments_bankmachine0_state; case (subfragments_bankmachine0_state) 1'd1: begin if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin sdram_bankmachine0_cmd_valid <= 1'd1; if (sdram_bankmachine0_cmd_ready) begin subfragments_bankmachine0_next_state <= 3'd5; end sdram_bankmachine0_cmd_payload_ras <= 1'd1; sdram_bankmachine0_cmd_payload_we <= 1'd1; sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine0_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin subfragments_bankmachine0_next_state <= 3'd5; end sdram_bankmachine0_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine0_trccon_ready) begin sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; sdram_bankmachine0_row_open <= 1'd1; sdram_bankmachine0_cmd_valid <= 1'd1; sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine0_cmd_ready) begin subfragments_bankmachine0_next_state <= 3'd6; end sdram_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine0_twtpcon_ready) begin sdram_bankmachine0_refresh_gnt <= 1'd1; end sdram_bankmachine0_row_close <= 1'd1; sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine0_refresh_req)) begin subfragments_bankmachine0_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine0_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine0_next_state <= 1'd0; end default: begin if (sdram_bankmachine0_refresh_req) begin subfragments_bankmachine0_next_state <= 3'd4; end else begin if (sdram_bankmachine0_cmd_buffer_source_valid) begin if (sdram_bankmachine0_row_opened) begin if (sdram_bankmachine0_row_hit) begin sdram_bankmachine0_cmd_valid <= 1'd1; if (sdram_bankmachine0_cmd_buffer_source_payload_we) begin sdram_bankmachine0_req_wdata_ready <= sdram_bankmachine0_cmd_ready; sdram_bankmachine0_cmd_payload_is_write <= 1'd1; sdram_bankmachine0_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine0_req_rdata_valid <= sdram_bankmachine0_cmd_ready; sdram_bankmachine0_cmd_payload_is_read <= 1'd1; end sdram_bankmachine0_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine0_cmd_ready & sdram_bankmachine0_auto_precharge)) begin subfragments_bankmachine0_next_state <= 2'd2; end end else begin subfragments_bankmachine0_next_state <= 1'd1; end end else begin subfragments_bankmachine0_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = sdram_bankmachine1_req_valid; assign sdram_bankmachine1_req_ready = sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine1_req_we; assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine1_req_addr; assign sdram_bankmachine1_cmd_buffer_sink_valid = sdram_bankmachine1_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine1_cmd_buffer_lookahead_source_ready = sdram_bankmachine1_cmd_buffer_sink_ready; assign sdram_bankmachine1_cmd_buffer_sink_first = sdram_bankmachine1_cmd_buffer_lookahead_source_first; assign sdram_bankmachine1_cmd_buffer_sink_last = sdram_bankmachine1_cmd_buffer_lookahead_source_last; assign sdram_bankmachine1_cmd_buffer_sink_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine1_cmd_buffer_sink_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine1_cmd_buffer_source_ready = (sdram_bankmachine1_req_wdata_ready | sdram_bankmachine1_req_rdata_valid); assign sdram_bankmachine1_req_lock = (sdram_bankmachine1_cmd_buffer_lookahead_source_valid | sdram_bankmachine1_cmd_buffer_source_valid); assign sdram_bankmachine1_row_hit = (sdram_bankmachine1_row == sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]); assign sdram_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin sdram_bankmachine1_cmd_payload_a <= 14'd0; if (sdram_bankmachine1_row_col_n_addr_sel) begin sdram_bankmachine1_cmd_payload_a <= sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; end else begin sdram_bankmachine1_cmd_payload_a <= ((sdram_bankmachine1_auto_precharge <<< 4'd10) | {sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign sdram_bankmachine1_twtpcon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_cmd_payload_is_write); assign sdram_bankmachine1_trccon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open); assign sdram_bankmachine1_trascon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open); always @(*) begin sdram_bankmachine1_auto_precharge <= 1'd0; if ((sdram_bankmachine1_cmd_buffer_lookahead_source_valid & sdram_bankmachine1_cmd_buffer_source_valid)) begin if ((sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin sdram_bankmachine1_auto_precharge <= (sdram_bankmachine1_row_close == 1'd0); end end end assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; assign sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine1_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine1_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine1_cmd_buffer_lookahead_source_valid = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; assign sdram_bankmachine1_cmd_buffer_lookahead_source_first = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine1_cmd_buffer_lookahead_source_last = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = sdram_bankmachine1_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine1_cmd_buffer_lookahead_replace) begin sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine1_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | sdram_bankmachine1_cmd_buffer_lookahead_replace)); assign sdram_bankmachine1_cmd_buffer_lookahead_do_read = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine1_cmd_buffer_lookahead_consume; assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine1_cmd_buffer_sink_ready = ((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine1_row_open <= 1'd0; sdram_bankmachine1_row_close <= 1'd0; sdram_bankmachine1_cmd_payload_cas <= 1'd0; sdram_bankmachine1_cmd_payload_ras <= 1'd0; sdram_bankmachine1_cmd_payload_we <= 1'd0; sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine1_cmd_payload_is_read <= 1'd0; sdram_bankmachine1_cmd_payload_is_write <= 1'd0; subfragments_bankmachine1_next_state <= 3'd0; sdram_bankmachine1_req_wdata_ready <= 1'd0; sdram_bankmachine1_req_rdata_valid <= 1'd0; sdram_bankmachine1_refresh_gnt <= 1'd0; sdram_bankmachine1_cmd_valid <= 1'd0; subfragments_bankmachine1_next_state <= subfragments_bankmachine1_state; case (subfragments_bankmachine1_state) 1'd1: begin if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin sdram_bankmachine1_cmd_valid <= 1'd1; if (sdram_bankmachine1_cmd_ready) begin subfragments_bankmachine1_next_state <= 3'd5; end sdram_bankmachine1_cmd_payload_ras <= 1'd1; sdram_bankmachine1_cmd_payload_we <= 1'd1; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine1_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin subfragments_bankmachine1_next_state <= 3'd5; end sdram_bankmachine1_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine1_trccon_ready) begin sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; sdram_bankmachine1_row_open <= 1'd1; sdram_bankmachine1_cmd_valid <= 1'd1; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine1_cmd_ready) begin subfragments_bankmachine1_next_state <= 3'd6; end sdram_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine1_twtpcon_ready) begin sdram_bankmachine1_refresh_gnt <= 1'd1; end sdram_bankmachine1_row_close <= 1'd1; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine1_refresh_req)) begin subfragments_bankmachine1_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine1_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine1_next_state <= 1'd0; end default: begin if (sdram_bankmachine1_refresh_req) begin subfragments_bankmachine1_next_state <= 3'd4; end else begin if (sdram_bankmachine1_cmd_buffer_source_valid) begin if (sdram_bankmachine1_row_opened) begin if (sdram_bankmachine1_row_hit) begin sdram_bankmachine1_cmd_valid <= 1'd1; if (sdram_bankmachine1_cmd_buffer_source_payload_we) begin sdram_bankmachine1_req_wdata_ready <= sdram_bankmachine1_cmd_ready; sdram_bankmachine1_cmd_payload_is_write <= 1'd1; sdram_bankmachine1_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine1_req_rdata_valid <= sdram_bankmachine1_cmd_ready; sdram_bankmachine1_cmd_payload_is_read <= 1'd1; end sdram_bankmachine1_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine1_cmd_ready & sdram_bankmachine1_auto_precharge)) begin subfragments_bankmachine1_next_state <= 2'd2; end end else begin subfragments_bankmachine1_next_state <= 1'd1; end end else begin subfragments_bankmachine1_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = sdram_bankmachine2_req_valid; assign sdram_bankmachine2_req_ready = sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine2_req_we; assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine2_req_addr; assign sdram_bankmachine2_cmd_buffer_sink_valid = sdram_bankmachine2_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine2_cmd_buffer_lookahead_source_ready = sdram_bankmachine2_cmd_buffer_sink_ready; assign sdram_bankmachine2_cmd_buffer_sink_first = sdram_bankmachine2_cmd_buffer_lookahead_source_first; assign sdram_bankmachine2_cmd_buffer_sink_last = sdram_bankmachine2_cmd_buffer_lookahead_source_last; assign sdram_bankmachine2_cmd_buffer_sink_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine2_cmd_buffer_sink_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine2_cmd_buffer_source_ready = (sdram_bankmachine2_req_wdata_ready | sdram_bankmachine2_req_rdata_valid); assign sdram_bankmachine2_req_lock = (sdram_bankmachine2_cmd_buffer_lookahead_source_valid | sdram_bankmachine2_cmd_buffer_source_valid); assign sdram_bankmachine2_row_hit = (sdram_bankmachine2_row == sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]); assign sdram_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin sdram_bankmachine2_cmd_payload_a <= 14'd0; if (sdram_bankmachine2_row_col_n_addr_sel) begin sdram_bankmachine2_cmd_payload_a <= sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; end else begin sdram_bankmachine2_cmd_payload_a <= ((sdram_bankmachine2_auto_precharge <<< 4'd10) | {sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign sdram_bankmachine2_twtpcon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_cmd_payload_is_write); assign sdram_bankmachine2_trccon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open); assign sdram_bankmachine2_trascon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open); always @(*) begin sdram_bankmachine2_auto_precharge <= 1'd0; if ((sdram_bankmachine2_cmd_buffer_lookahead_source_valid & sdram_bankmachine2_cmd_buffer_source_valid)) begin if ((sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin sdram_bankmachine2_auto_precharge <= (sdram_bankmachine2_row_close == 1'd0); end end end assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; assign sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine2_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine2_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine2_cmd_buffer_lookahead_source_valid = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; assign sdram_bankmachine2_cmd_buffer_lookahead_source_first = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine2_cmd_buffer_lookahead_source_last = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = sdram_bankmachine2_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine2_cmd_buffer_lookahead_replace) begin sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine2_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | sdram_bankmachine2_cmd_buffer_lookahead_replace)); assign sdram_bankmachine2_cmd_buffer_lookahead_do_read = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine2_cmd_buffer_lookahead_consume; assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine2_cmd_buffer_sink_ready = ((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine2_row_open <= 1'd0; sdram_bankmachine2_row_close <= 1'd0; sdram_bankmachine2_cmd_payload_cas <= 1'd0; sdram_bankmachine2_cmd_payload_ras <= 1'd0; sdram_bankmachine2_cmd_payload_we <= 1'd0; sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; subfragments_bankmachine2_next_state <= 3'd0; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine2_cmd_payload_is_read <= 1'd0; sdram_bankmachine2_cmd_payload_is_write <= 1'd0; sdram_bankmachine2_req_wdata_ready <= 1'd0; sdram_bankmachine2_req_rdata_valid <= 1'd0; sdram_bankmachine2_refresh_gnt <= 1'd0; sdram_bankmachine2_cmd_valid <= 1'd0; subfragments_bankmachine2_next_state <= subfragments_bankmachine2_state; case (subfragments_bankmachine2_state) 1'd1: begin if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin sdram_bankmachine2_cmd_valid <= 1'd1; if (sdram_bankmachine2_cmd_ready) begin subfragments_bankmachine2_next_state <= 3'd5; end sdram_bankmachine2_cmd_payload_ras <= 1'd1; sdram_bankmachine2_cmd_payload_we <= 1'd1; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine2_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin subfragments_bankmachine2_next_state <= 3'd5; end sdram_bankmachine2_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine2_trccon_ready) begin sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; sdram_bankmachine2_row_open <= 1'd1; sdram_bankmachine2_cmd_valid <= 1'd1; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine2_cmd_ready) begin subfragments_bankmachine2_next_state <= 3'd6; end sdram_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine2_twtpcon_ready) begin sdram_bankmachine2_refresh_gnt <= 1'd1; end sdram_bankmachine2_row_close <= 1'd1; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine2_refresh_req)) begin subfragments_bankmachine2_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine2_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine2_next_state <= 1'd0; end default: begin if (sdram_bankmachine2_refresh_req) begin subfragments_bankmachine2_next_state <= 3'd4; end else begin if (sdram_bankmachine2_cmd_buffer_source_valid) begin if (sdram_bankmachine2_row_opened) begin if (sdram_bankmachine2_row_hit) begin sdram_bankmachine2_cmd_valid <= 1'd1; if (sdram_bankmachine2_cmd_buffer_source_payload_we) begin sdram_bankmachine2_req_wdata_ready <= sdram_bankmachine2_cmd_ready; sdram_bankmachine2_cmd_payload_is_write <= 1'd1; sdram_bankmachine2_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine2_req_rdata_valid <= sdram_bankmachine2_cmd_ready; sdram_bankmachine2_cmd_payload_is_read <= 1'd1; end sdram_bankmachine2_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine2_cmd_ready & sdram_bankmachine2_auto_precharge)) begin subfragments_bankmachine2_next_state <= 2'd2; end end else begin subfragments_bankmachine2_next_state <= 1'd1; end end else begin subfragments_bankmachine2_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = sdram_bankmachine3_req_valid; assign sdram_bankmachine3_req_ready = sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine3_req_we; assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine3_req_addr; assign sdram_bankmachine3_cmd_buffer_sink_valid = sdram_bankmachine3_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine3_cmd_buffer_lookahead_source_ready = sdram_bankmachine3_cmd_buffer_sink_ready; assign sdram_bankmachine3_cmd_buffer_sink_first = sdram_bankmachine3_cmd_buffer_lookahead_source_first; assign sdram_bankmachine3_cmd_buffer_sink_last = sdram_bankmachine3_cmd_buffer_lookahead_source_last; assign sdram_bankmachine3_cmd_buffer_sink_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine3_cmd_buffer_sink_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine3_cmd_buffer_source_ready = (sdram_bankmachine3_req_wdata_ready | sdram_bankmachine3_req_rdata_valid); assign sdram_bankmachine3_req_lock = (sdram_bankmachine3_cmd_buffer_lookahead_source_valid | sdram_bankmachine3_cmd_buffer_source_valid); assign sdram_bankmachine3_row_hit = (sdram_bankmachine3_row == sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]); assign sdram_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin sdram_bankmachine3_cmd_payload_a <= 14'd0; if (sdram_bankmachine3_row_col_n_addr_sel) begin sdram_bankmachine3_cmd_payload_a <= sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; end else begin sdram_bankmachine3_cmd_payload_a <= ((sdram_bankmachine3_auto_precharge <<< 4'd10) | {sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign sdram_bankmachine3_twtpcon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_cmd_payload_is_write); assign sdram_bankmachine3_trccon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open); assign sdram_bankmachine3_trascon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open); always @(*) begin sdram_bankmachine3_auto_precharge <= 1'd0; if ((sdram_bankmachine3_cmd_buffer_lookahead_source_valid & sdram_bankmachine3_cmd_buffer_source_valid)) begin if ((sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin sdram_bankmachine3_auto_precharge <= (sdram_bankmachine3_row_close == 1'd0); end end end assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; assign sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine3_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine3_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine3_cmd_buffer_lookahead_source_valid = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; assign sdram_bankmachine3_cmd_buffer_lookahead_source_first = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine3_cmd_buffer_lookahead_source_last = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = sdram_bankmachine3_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine3_cmd_buffer_lookahead_replace) begin sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine3_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | sdram_bankmachine3_cmd_buffer_lookahead_replace)); assign sdram_bankmachine3_cmd_buffer_lookahead_do_read = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine3_cmd_buffer_lookahead_consume; assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine3_row_open <= 1'd0; sdram_bankmachine3_row_close <= 1'd0; sdram_bankmachine3_cmd_payload_cas <= 1'd0; subfragments_bankmachine3_next_state <= 3'd0; sdram_bankmachine3_cmd_payload_ras <= 1'd0; sdram_bankmachine3_cmd_payload_we <= 1'd0; sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine3_cmd_payload_is_read <= 1'd0; sdram_bankmachine3_cmd_payload_is_write <= 1'd0; sdram_bankmachine3_req_wdata_ready <= 1'd0; sdram_bankmachine3_req_rdata_valid <= 1'd0; sdram_bankmachine3_refresh_gnt <= 1'd0; sdram_bankmachine3_cmd_valid <= 1'd0; subfragments_bankmachine3_next_state <= subfragments_bankmachine3_state; case (subfragments_bankmachine3_state) 1'd1: begin if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin sdram_bankmachine3_cmd_valid <= 1'd1; if (sdram_bankmachine3_cmd_ready) begin subfragments_bankmachine3_next_state <= 3'd5; end sdram_bankmachine3_cmd_payload_ras <= 1'd1; sdram_bankmachine3_cmd_payload_we <= 1'd1; sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine3_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin subfragments_bankmachine3_next_state <= 3'd5; end sdram_bankmachine3_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine3_trccon_ready) begin sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; sdram_bankmachine3_row_open <= 1'd1; sdram_bankmachine3_cmd_valid <= 1'd1; sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine3_cmd_ready) begin subfragments_bankmachine3_next_state <= 3'd6; end sdram_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine3_twtpcon_ready) begin sdram_bankmachine3_refresh_gnt <= 1'd1; end sdram_bankmachine3_row_close <= 1'd1; sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine3_refresh_req)) begin subfragments_bankmachine3_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine3_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine3_next_state <= 1'd0; end default: begin if (sdram_bankmachine3_refresh_req) begin subfragments_bankmachine3_next_state <= 3'd4; end else begin if (sdram_bankmachine3_cmd_buffer_source_valid) begin if (sdram_bankmachine3_row_opened) begin if (sdram_bankmachine3_row_hit) begin sdram_bankmachine3_cmd_valid <= 1'd1; if (sdram_bankmachine3_cmd_buffer_source_payload_we) begin sdram_bankmachine3_req_wdata_ready <= sdram_bankmachine3_cmd_ready; sdram_bankmachine3_cmd_payload_is_write <= 1'd1; sdram_bankmachine3_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine3_req_rdata_valid <= sdram_bankmachine3_cmd_ready; sdram_bankmachine3_cmd_payload_is_read <= 1'd1; end sdram_bankmachine3_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine3_cmd_ready & sdram_bankmachine3_auto_precharge)) begin subfragments_bankmachine3_next_state <= 2'd2; end end else begin subfragments_bankmachine3_next_state <= 1'd1; end end else begin subfragments_bankmachine3_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = sdram_bankmachine4_req_valid; assign sdram_bankmachine4_req_ready = sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine4_req_we; assign sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine4_req_addr; assign sdram_bankmachine4_cmd_buffer_sink_valid = sdram_bankmachine4_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine4_cmd_buffer_lookahead_source_ready = sdram_bankmachine4_cmd_buffer_sink_ready; assign sdram_bankmachine4_cmd_buffer_sink_first = sdram_bankmachine4_cmd_buffer_lookahead_source_first; assign sdram_bankmachine4_cmd_buffer_sink_last = sdram_bankmachine4_cmd_buffer_lookahead_source_last; assign sdram_bankmachine4_cmd_buffer_sink_payload_we = sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine4_cmd_buffer_sink_payload_addr = sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine4_cmd_buffer_source_ready = (sdram_bankmachine4_req_wdata_ready | sdram_bankmachine4_req_rdata_valid); assign sdram_bankmachine4_req_lock = (sdram_bankmachine4_cmd_buffer_lookahead_source_valid | sdram_bankmachine4_cmd_buffer_source_valid); assign sdram_bankmachine4_row_hit = (sdram_bankmachine4_row == sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]); assign sdram_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin sdram_bankmachine4_cmd_payload_a <= 14'd0; if (sdram_bankmachine4_row_col_n_addr_sel) begin sdram_bankmachine4_cmd_payload_a <= sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; end else begin sdram_bankmachine4_cmd_payload_a <= ((sdram_bankmachine4_auto_precharge <<< 4'd10) | {sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign sdram_bankmachine4_twtpcon_valid = ((sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_ready) & sdram_bankmachine4_cmd_payload_is_write); assign sdram_bankmachine4_trccon_valid = ((sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_ready) & sdram_bankmachine4_row_open); assign sdram_bankmachine4_trascon_valid = ((sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_ready) & sdram_bankmachine4_row_open); always @(*) begin sdram_bankmachine4_auto_precharge <= 1'd0; if ((sdram_bankmachine4_cmd_buffer_lookahead_source_valid & sdram_bankmachine4_cmd_buffer_source_valid)) begin if ((sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin sdram_bankmachine4_auto_precharge <= (sdram_bankmachine4_row_close == 1'd0); end end end assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; assign sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine4_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine4_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine4_cmd_buffer_lookahead_source_valid = sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; assign sdram_bankmachine4_cmd_buffer_lookahead_source_first = sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine4_cmd_buffer_lookahead_source_last = sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = sdram_bankmachine4_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine4_cmd_buffer_lookahead_replace) begin sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine4_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; assign sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | sdram_bankmachine4_cmd_buffer_lookahead_replace)); assign sdram_bankmachine4_cmd_buffer_lookahead_do_read = (sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); assign sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine4_cmd_buffer_lookahead_consume; assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (sdram_bankmachine4_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine4_cmd_buffer_sink_ready = ((~sdram_bankmachine4_cmd_buffer_source_valid) | sdram_bankmachine4_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine4_row_open <= 1'd0; sdram_bankmachine4_row_close <= 1'd0; subfragments_bankmachine4_next_state <= 3'd0; sdram_bankmachine4_cmd_payload_cas <= 1'd0; sdram_bankmachine4_cmd_payload_ras <= 1'd0; sdram_bankmachine4_cmd_payload_we <= 1'd0; sdram_bankmachine4_row_col_n_addr_sel <= 1'd0; sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine4_cmd_payload_is_read <= 1'd0; sdram_bankmachine4_cmd_payload_is_write <= 1'd0; sdram_bankmachine4_req_wdata_ready <= 1'd0; sdram_bankmachine4_req_rdata_valid <= 1'd0; sdram_bankmachine4_refresh_gnt <= 1'd0; sdram_bankmachine4_cmd_valid <= 1'd0; subfragments_bankmachine4_next_state <= subfragments_bankmachine4_state; case (subfragments_bankmachine4_state) 1'd1: begin if ((sdram_bankmachine4_twtpcon_ready & sdram_bankmachine4_trascon_ready)) begin sdram_bankmachine4_cmd_valid <= 1'd1; if (sdram_bankmachine4_cmd_ready) begin subfragments_bankmachine4_next_state <= 3'd5; end sdram_bankmachine4_cmd_payload_ras <= 1'd1; sdram_bankmachine4_cmd_payload_we <= 1'd1; sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine4_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine4_twtpcon_ready & sdram_bankmachine4_trascon_ready)) begin subfragments_bankmachine4_next_state <= 3'd5; end sdram_bankmachine4_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine4_trccon_ready) begin sdram_bankmachine4_row_col_n_addr_sel <= 1'd1; sdram_bankmachine4_row_open <= 1'd1; sdram_bankmachine4_cmd_valid <= 1'd1; sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine4_cmd_ready) begin subfragments_bankmachine4_next_state <= 3'd6; end sdram_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine4_twtpcon_ready) begin sdram_bankmachine4_refresh_gnt <= 1'd1; end sdram_bankmachine4_row_close <= 1'd1; sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine4_refresh_req)) begin subfragments_bankmachine4_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine4_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine4_next_state <= 1'd0; end default: begin if (sdram_bankmachine4_refresh_req) begin subfragments_bankmachine4_next_state <= 3'd4; end else begin if (sdram_bankmachine4_cmd_buffer_source_valid) begin if (sdram_bankmachine4_row_opened) begin if (sdram_bankmachine4_row_hit) begin sdram_bankmachine4_cmd_valid <= 1'd1; if (sdram_bankmachine4_cmd_buffer_source_payload_we) begin sdram_bankmachine4_req_wdata_ready <= sdram_bankmachine4_cmd_ready; sdram_bankmachine4_cmd_payload_is_write <= 1'd1; sdram_bankmachine4_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine4_req_rdata_valid <= sdram_bankmachine4_cmd_ready; sdram_bankmachine4_cmd_payload_is_read <= 1'd1; end sdram_bankmachine4_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine4_cmd_ready & sdram_bankmachine4_auto_precharge)) begin subfragments_bankmachine4_next_state <= 2'd2; end end else begin subfragments_bankmachine4_next_state <= 1'd1; end end else begin subfragments_bankmachine4_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = sdram_bankmachine5_req_valid; assign sdram_bankmachine5_req_ready = sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine5_req_we; assign sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine5_req_addr; assign sdram_bankmachine5_cmd_buffer_sink_valid = sdram_bankmachine5_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine5_cmd_buffer_lookahead_source_ready = sdram_bankmachine5_cmd_buffer_sink_ready; assign sdram_bankmachine5_cmd_buffer_sink_first = sdram_bankmachine5_cmd_buffer_lookahead_source_first; assign sdram_bankmachine5_cmd_buffer_sink_last = sdram_bankmachine5_cmd_buffer_lookahead_source_last; assign sdram_bankmachine5_cmd_buffer_sink_payload_we = sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine5_cmd_buffer_sink_payload_addr = sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine5_cmd_buffer_source_ready = (sdram_bankmachine5_req_wdata_ready | sdram_bankmachine5_req_rdata_valid); assign sdram_bankmachine5_req_lock = (sdram_bankmachine5_cmd_buffer_lookahead_source_valid | sdram_bankmachine5_cmd_buffer_source_valid); assign sdram_bankmachine5_row_hit = (sdram_bankmachine5_row == sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]); assign sdram_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin sdram_bankmachine5_cmd_payload_a <= 14'd0; if (sdram_bankmachine5_row_col_n_addr_sel) begin sdram_bankmachine5_cmd_payload_a <= sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; end else begin sdram_bankmachine5_cmd_payload_a <= ((sdram_bankmachine5_auto_precharge <<< 4'd10) | {sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign sdram_bankmachine5_twtpcon_valid = ((sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_ready) & sdram_bankmachine5_cmd_payload_is_write); assign sdram_bankmachine5_trccon_valid = ((sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_ready) & sdram_bankmachine5_row_open); assign sdram_bankmachine5_trascon_valid = ((sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_ready) & sdram_bankmachine5_row_open); always @(*) begin sdram_bankmachine5_auto_precharge <= 1'd0; if ((sdram_bankmachine5_cmd_buffer_lookahead_source_valid & sdram_bankmachine5_cmd_buffer_source_valid)) begin if ((sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin sdram_bankmachine5_auto_precharge <= (sdram_bankmachine5_row_close == 1'd0); end end end assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; assign sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine5_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine5_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine5_cmd_buffer_lookahead_source_valid = sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; assign sdram_bankmachine5_cmd_buffer_lookahead_source_first = sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine5_cmd_buffer_lookahead_source_last = sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = sdram_bankmachine5_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine5_cmd_buffer_lookahead_replace) begin sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine5_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; assign sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | sdram_bankmachine5_cmd_buffer_lookahead_replace)); assign sdram_bankmachine5_cmd_buffer_lookahead_do_read = (sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); assign sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine5_cmd_buffer_lookahead_consume; assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (sdram_bankmachine5_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine5_cmd_buffer_sink_ready = ((~sdram_bankmachine5_cmd_buffer_source_valid) | sdram_bankmachine5_cmd_buffer_source_ready); always @(*) begin subfragments_bankmachine5_next_state <= 3'd0; sdram_bankmachine5_row_open <= 1'd0; sdram_bankmachine5_row_close <= 1'd0; sdram_bankmachine5_cmd_payload_cas <= 1'd0; sdram_bankmachine5_cmd_payload_ras <= 1'd0; sdram_bankmachine5_cmd_payload_we <= 1'd0; sdram_bankmachine5_row_col_n_addr_sel <= 1'd0; sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine5_cmd_payload_is_read <= 1'd0; sdram_bankmachine5_cmd_payload_is_write <= 1'd0; sdram_bankmachine5_req_wdata_ready <= 1'd0; sdram_bankmachine5_req_rdata_valid <= 1'd0; sdram_bankmachine5_refresh_gnt <= 1'd0; sdram_bankmachine5_cmd_valid <= 1'd0; subfragments_bankmachine5_next_state <= subfragments_bankmachine5_state; case (subfragments_bankmachine5_state) 1'd1: begin if ((sdram_bankmachine5_twtpcon_ready & sdram_bankmachine5_trascon_ready)) begin sdram_bankmachine5_cmd_valid <= 1'd1; if (sdram_bankmachine5_cmd_ready) begin subfragments_bankmachine5_next_state <= 3'd5; end sdram_bankmachine5_cmd_payload_ras <= 1'd1; sdram_bankmachine5_cmd_payload_we <= 1'd1; sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine5_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine5_twtpcon_ready & sdram_bankmachine5_trascon_ready)) begin subfragments_bankmachine5_next_state <= 3'd5; end sdram_bankmachine5_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine5_trccon_ready) begin sdram_bankmachine5_row_col_n_addr_sel <= 1'd1; sdram_bankmachine5_row_open <= 1'd1; sdram_bankmachine5_cmd_valid <= 1'd1; sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine5_cmd_ready) begin subfragments_bankmachine5_next_state <= 3'd6; end sdram_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine5_twtpcon_ready) begin sdram_bankmachine5_refresh_gnt <= 1'd1; end sdram_bankmachine5_row_close <= 1'd1; sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine5_refresh_req)) begin subfragments_bankmachine5_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine5_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine5_next_state <= 1'd0; end default: begin if (sdram_bankmachine5_refresh_req) begin subfragments_bankmachine5_next_state <= 3'd4; end else begin if (sdram_bankmachine5_cmd_buffer_source_valid) begin if (sdram_bankmachine5_row_opened) begin if (sdram_bankmachine5_row_hit) begin sdram_bankmachine5_cmd_valid <= 1'd1; if (sdram_bankmachine5_cmd_buffer_source_payload_we) begin sdram_bankmachine5_req_wdata_ready <= sdram_bankmachine5_cmd_ready; sdram_bankmachine5_cmd_payload_is_write <= 1'd1; sdram_bankmachine5_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine5_req_rdata_valid <= sdram_bankmachine5_cmd_ready; sdram_bankmachine5_cmd_payload_is_read <= 1'd1; end sdram_bankmachine5_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine5_cmd_ready & sdram_bankmachine5_auto_precharge)) begin subfragments_bankmachine5_next_state <= 2'd2; end end else begin subfragments_bankmachine5_next_state <= 1'd1; end end else begin subfragments_bankmachine5_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = sdram_bankmachine6_req_valid; assign sdram_bankmachine6_req_ready = sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine6_req_we; assign sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine6_req_addr; assign sdram_bankmachine6_cmd_buffer_sink_valid = sdram_bankmachine6_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine6_cmd_buffer_lookahead_source_ready = sdram_bankmachine6_cmd_buffer_sink_ready; assign sdram_bankmachine6_cmd_buffer_sink_first = sdram_bankmachine6_cmd_buffer_lookahead_source_first; assign sdram_bankmachine6_cmd_buffer_sink_last = sdram_bankmachine6_cmd_buffer_lookahead_source_last; assign sdram_bankmachine6_cmd_buffer_sink_payload_we = sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine6_cmd_buffer_sink_payload_addr = sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine6_cmd_buffer_source_ready = (sdram_bankmachine6_req_wdata_ready | sdram_bankmachine6_req_rdata_valid); assign sdram_bankmachine6_req_lock = (sdram_bankmachine6_cmd_buffer_lookahead_source_valid | sdram_bankmachine6_cmd_buffer_source_valid); assign sdram_bankmachine6_row_hit = (sdram_bankmachine6_row == sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]); assign sdram_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin sdram_bankmachine6_cmd_payload_a <= 14'd0; if (sdram_bankmachine6_row_col_n_addr_sel) begin sdram_bankmachine6_cmd_payload_a <= sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; end else begin sdram_bankmachine6_cmd_payload_a <= ((sdram_bankmachine6_auto_precharge <<< 4'd10) | {sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign sdram_bankmachine6_twtpcon_valid = ((sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_ready) & sdram_bankmachine6_cmd_payload_is_write); assign sdram_bankmachine6_trccon_valid = ((sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_ready) & sdram_bankmachine6_row_open); assign sdram_bankmachine6_trascon_valid = ((sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_ready) & sdram_bankmachine6_row_open); always @(*) begin sdram_bankmachine6_auto_precharge <= 1'd0; if ((sdram_bankmachine6_cmd_buffer_lookahead_source_valid & sdram_bankmachine6_cmd_buffer_source_valid)) begin if ((sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin sdram_bankmachine6_auto_precharge <= (sdram_bankmachine6_row_close == 1'd0); end end end assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; assign sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine6_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine6_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine6_cmd_buffer_lookahead_source_valid = sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; assign sdram_bankmachine6_cmd_buffer_lookahead_source_first = sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine6_cmd_buffer_lookahead_source_last = sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = sdram_bankmachine6_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine6_cmd_buffer_lookahead_replace) begin sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine6_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; assign sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | sdram_bankmachine6_cmd_buffer_lookahead_replace)); assign sdram_bankmachine6_cmd_buffer_lookahead_do_read = (sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); assign sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine6_cmd_buffer_lookahead_consume; assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (sdram_bankmachine6_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine6_cmd_buffer_sink_ready = ((~sdram_bankmachine6_cmd_buffer_source_valid) | sdram_bankmachine6_cmd_buffer_source_ready); always @(*) begin subfragments_bankmachine6_next_state <= 3'd0; sdram_bankmachine6_row_open <= 1'd0; sdram_bankmachine6_row_close <= 1'd0; sdram_bankmachine6_cmd_payload_cas <= 1'd0; sdram_bankmachine6_cmd_payload_ras <= 1'd0; sdram_bankmachine6_cmd_payload_we <= 1'd0; sdram_bankmachine6_row_col_n_addr_sel <= 1'd0; sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine6_cmd_payload_is_read <= 1'd0; sdram_bankmachine6_cmd_payload_is_write <= 1'd0; sdram_bankmachine6_req_wdata_ready <= 1'd0; sdram_bankmachine6_req_rdata_valid <= 1'd0; sdram_bankmachine6_refresh_gnt <= 1'd0; sdram_bankmachine6_cmd_valid <= 1'd0; subfragments_bankmachine6_next_state <= subfragments_bankmachine6_state; case (subfragments_bankmachine6_state) 1'd1: begin if ((sdram_bankmachine6_twtpcon_ready & sdram_bankmachine6_trascon_ready)) begin sdram_bankmachine6_cmd_valid <= 1'd1; if (sdram_bankmachine6_cmd_ready) begin subfragments_bankmachine6_next_state <= 3'd5; end sdram_bankmachine6_cmd_payload_ras <= 1'd1; sdram_bankmachine6_cmd_payload_we <= 1'd1; sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine6_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine6_twtpcon_ready & sdram_bankmachine6_trascon_ready)) begin subfragments_bankmachine6_next_state <= 3'd5; end sdram_bankmachine6_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine6_trccon_ready) begin sdram_bankmachine6_row_col_n_addr_sel <= 1'd1; sdram_bankmachine6_row_open <= 1'd1; sdram_bankmachine6_cmd_valid <= 1'd1; sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine6_cmd_ready) begin subfragments_bankmachine6_next_state <= 3'd6; end sdram_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine6_twtpcon_ready) begin sdram_bankmachine6_refresh_gnt <= 1'd1; end sdram_bankmachine6_row_close <= 1'd1; sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine6_refresh_req)) begin subfragments_bankmachine6_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine6_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine6_next_state <= 1'd0; end default: begin if (sdram_bankmachine6_refresh_req) begin subfragments_bankmachine6_next_state <= 3'd4; end else begin if (sdram_bankmachine6_cmd_buffer_source_valid) begin if (sdram_bankmachine6_row_opened) begin if (sdram_bankmachine6_row_hit) begin sdram_bankmachine6_cmd_valid <= 1'd1; if (sdram_bankmachine6_cmd_buffer_source_payload_we) begin sdram_bankmachine6_req_wdata_ready <= sdram_bankmachine6_cmd_ready; sdram_bankmachine6_cmd_payload_is_write <= 1'd1; sdram_bankmachine6_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine6_req_rdata_valid <= sdram_bankmachine6_cmd_ready; sdram_bankmachine6_cmd_payload_is_read <= 1'd1; end sdram_bankmachine6_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine6_cmd_ready & sdram_bankmachine6_auto_precharge)) begin subfragments_bankmachine6_next_state <= 2'd2; end end else begin subfragments_bankmachine6_next_state <= 1'd1; end end else begin subfragments_bankmachine6_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = sdram_bankmachine7_req_valid; assign sdram_bankmachine7_req_ready = sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine7_req_we; assign sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine7_req_addr; assign sdram_bankmachine7_cmd_buffer_sink_valid = sdram_bankmachine7_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine7_cmd_buffer_lookahead_source_ready = sdram_bankmachine7_cmd_buffer_sink_ready; assign sdram_bankmachine7_cmd_buffer_sink_first = sdram_bankmachine7_cmd_buffer_lookahead_source_first; assign sdram_bankmachine7_cmd_buffer_sink_last = sdram_bankmachine7_cmd_buffer_lookahead_source_last; assign sdram_bankmachine7_cmd_buffer_sink_payload_we = sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine7_cmd_buffer_sink_payload_addr = sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine7_cmd_buffer_source_ready = (sdram_bankmachine7_req_wdata_ready | sdram_bankmachine7_req_rdata_valid); assign sdram_bankmachine7_req_lock = (sdram_bankmachine7_cmd_buffer_lookahead_source_valid | sdram_bankmachine7_cmd_buffer_source_valid); assign sdram_bankmachine7_row_hit = (sdram_bankmachine7_row == sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]); assign sdram_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin sdram_bankmachine7_cmd_payload_a <= 14'd0; if (sdram_bankmachine7_row_col_n_addr_sel) begin sdram_bankmachine7_cmd_payload_a <= sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; end else begin sdram_bankmachine7_cmd_payload_a <= ((sdram_bankmachine7_auto_precharge <<< 4'd10) | {sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign sdram_bankmachine7_twtpcon_valid = ((sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_ready) & sdram_bankmachine7_cmd_payload_is_write); assign sdram_bankmachine7_trccon_valid = ((sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_ready) & sdram_bankmachine7_row_open); assign sdram_bankmachine7_trascon_valid = ((sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_ready) & sdram_bankmachine7_row_open); always @(*) begin sdram_bankmachine7_auto_precharge <= 1'd0; if ((sdram_bankmachine7_cmd_buffer_lookahead_source_valid & sdram_bankmachine7_cmd_buffer_source_valid)) begin if ((sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin sdram_bankmachine7_auto_precharge <= (sdram_bankmachine7_row_close == 1'd0); end end end assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; assign sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine7_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine7_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine7_cmd_buffer_lookahead_source_valid = sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; assign sdram_bankmachine7_cmd_buffer_lookahead_source_first = sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine7_cmd_buffer_lookahead_source_last = sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = sdram_bankmachine7_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine7_cmd_buffer_lookahead_replace) begin sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine7_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; assign sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | sdram_bankmachine7_cmd_buffer_lookahead_replace)); assign sdram_bankmachine7_cmd_buffer_lookahead_do_read = (sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); assign sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine7_cmd_buffer_lookahead_consume; assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (sdram_bankmachine7_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine7_cmd_buffer_sink_ready = ((~sdram_bankmachine7_cmd_buffer_source_valid) | sdram_bankmachine7_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine7_row_open <= 1'd0; sdram_bankmachine7_row_close <= 1'd0; sdram_bankmachine7_cmd_payload_cas <= 1'd0; sdram_bankmachine7_cmd_payload_ras <= 1'd0; sdram_bankmachine7_cmd_payload_we <= 1'd0; sdram_bankmachine7_row_col_n_addr_sel <= 1'd0; sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine7_cmd_payload_is_read <= 1'd0; sdram_bankmachine7_cmd_payload_is_write <= 1'd0; sdram_bankmachine7_req_wdata_ready <= 1'd0; sdram_bankmachine7_refresh_gnt <= 1'd0; sdram_bankmachine7_req_rdata_valid <= 1'd0; subfragments_bankmachine7_next_state <= 3'd0; sdram_bankmachine7_cmd_valid <= 1'd0; subfragments_bankmachine7_next_state <= subfragments_bankmachine7_state; case (subfragments_bankmachine7_state) 1'd1: begin if ((sdram_bankmachine7_twtpcon_ready & sdram_bankmachine7_trascon_ready)) begin sdram_bankmachine7_cmd_valid <= 1'd1; if (sdram_bankmachine7_cmd_ready) begin subfragments_bankmachine7_next_state <= 3'd5; end sdram_bankmachine7_cmd_payload_ras <= 1'd1; sdram_bankmachine7_cmd_payload_we <= 1'd1; sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine7_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine7_twtpcon_ready & sdram_bankmachine7_trascon_ready)) begin subfragments_bankmachine7_next_state <= 3'd5; end sdram_bankmachine7_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine7_trccon_ready) begin sdram_bankmachine7_row_col_n_addr_sel <= 1'd1; sdram_bankmachine7_row_open <= 1'd1; sdram_bankmachine7_cmd_valid <= 1'd1; sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine7_cmd_ready) begin subfragments_bankmachine7_next_state <= 3'd6; end sdram_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine7_twtpcon_ready) begin sdram_bankmachine7_refresh_gnt <= 1'd1; end sdram_bankmachine7_row_close <= 1'd1; sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine7_refresh_req)) begin subfragments_bankmachine7_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine7_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine7_next_state <= 1'd0; end default: begin if (sdram_bankmachine7_refresh_req) begin subfragments_bankmachine7_next_state <= 3'd4; end else begin if (sdram_bankmachine7_cmd_buffer_source_valid) begin if (sdram_bankmachine7_row_opened) begin if (sdram_bankmachine7_row_hit) begin sdram_bankmachine7_cmd_valid <= 1'd1; if (sdram_bankmachine7_cmd_buffer_source_payload_we) begin sdram_bankmachine7_req_wdata_ready <= sdram_bankmachine7_cmd_ready; sdram_bankmachine7_cmd_payload_is_write <= 1'd1; sdram_bankmachine7_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine7_req_rdata_valid <= sdram_bankmachine7_cmd_ready; sdram_bankmachine7_cmd_payload_is_read <= 1'd1; end sdram_bankmachine7_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine7_cmd_ready & sdram_bankmachine7_auto_precharge)) begin subfragments_bankmachine7_next_state <= 2'd2; end end else begin subfragments_bankmachine7_next_state <= 1'd1; end end else begin subfragments_bankmachine7_next_state <= 2'd3; end end end end endcase end assign sdram_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); assign sdram_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); assign sdram_trrdcon_valid = ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & ((sdram_choose_cmd_cmd_payload_ras & (~sdram_choose_cmd_cmd_payload_cas)) & (~sdram_choose_cmd_cmd_payload_we))); assign sdram_tfawcon_valid = ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & ((sdram_choose_cmd_cmd_payload_ras & (~sdram_choose_cmd_cmd_payload_cas)) & (~sdram_choose_cmd_cmd_payload_we))); assign sdram_ras_allowed = (sdram_trrdcon_ready & sdram_tfawcon_ready); assign sdram_tccdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_cmd_payload_is_write | sdram_choose_req_cmd_payload_is_read)); assign sdram_cas_allowed = sdram_tccdcon_ready; assign sdram_twtrcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); assign sdram_read_available = ((((((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_read) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_read)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_read)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_read)) | (sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_payload_is_read)) | (sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_payload_is_read)) | (sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_payload_is_read)) | (sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_payload_is_read)); assign sdram_write_available = ((((((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_write) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_write)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_write)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_write)) | (sdram_bankmachine4_cmd_valid & sdram_bankmachine4_cmd_payload_is_write)) | (sdram_bankmachine5_cmd_valid & sdram_bankmachine5_cmd_payload_is_write)) | (sdram_bankmachine6_cmd_valid & sdram_bankmachine6_cmd_payload_is_write)) | (sdram_bankmachine7_cmd_valid & sdram_bankmachine7_cmd_payload_is_write)); assign sdram_max_time0 = (sdram_time0 == 1'd0); assign sdram_max_time1 = (sdram_time1 == 1'd0); assign sdram_bankmachine0_refresh_req = sdram_cmd_valid; assign sdram_bankmachine1_refresh_req = sdram_cmd_valid; assign sdram_bankmachine2_refresh_req = sdram_cmd_valid; assign sdram_bankmachine3_refresh_req = sdram_cmd_valid; assign sdram_bankmachine4_refresh_req = sdram_cmd_valid; assign sdram_bankmachine5_refresh_req = sdram_cmd_valid; assign sdram_bankmachine6_refresh_req = sdram_cmd_valid; assign sdram_bankmachine7_refresh_req = sdram_cmd_valid; assign sdram_go_to_refresh = (((((((sdram_bankmachine0_refresh_gnt & sdram_bankmachine1_refresh_gnt) & sdram_bankmachine2_refresh_gnt) & sdram_bankmachine3_refresh_gnt) & sdram_bankmachine4_refresh_gnt) & sdram_bankmachine5_refresh_gnt) & sdram_bankmachine6_refresh_gnt) & sdram_bankmachine7_refresh_gnt); assign sdram_interface_rdata = {sdram_dfi_p3_rddata, sdram_dfi_p2_rddata, sdram_dfi_p1_rddata, sdram_dfi_p0_rddata}; assign {sdram_dfi_p3_wrdata, sdram_dfi_p2_wrdata, sdram_dfi_p1_wrdata, sdram_dfi_p0_wrdata} = sdram_interface_wdata; assign {sdram_dfi_p3_wrdata_mask, sdram_dfi_p2_wrdata_mask, sdram_dfi_p1_wrdata_mask, sdram_dfi_p0_wrdata_mask} = (~sdram_interface_wdata_we); always @(*) begin sdram_choose_cmd_valids <= 8'd0; sdram_choose_cmd_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[4] <= (sdram_bankmachine4_cmd_valid & (((sdram_bankmachine4_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine4_cmd_payload_ras & (~sdram_bankmachine4_cmd_payload_cas)) & (~sdram_bankmachine4_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine4_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine4_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[5] <= (sdram_bankmachine5_cmd_valid & (((sdram_bankmachine5_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine5_cmd_payload_ras & (~sdram_bankmachine5_cmd_payload_cas)) & (~sdram_bankmachine5_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine5_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine5_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[6] <= (sdram_bankmachine6_cmd_valid & (((sdram_bankmachine6_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine6_cmd_payload_ras & (~sdram_bankmachine6_cmd_payload_cas)) & (~sdram_bankmachine6_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine6_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine6_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[7] <= (sdram_bankmachine7_cmd_valid & (((sdram_bankmachine7_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine7_cmd_payload_ras & (~sdram_bankmachine7_cmd_payload_cas)) & (~sdram_bankmachine7_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine7_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine7_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); end assign sdram_choose_cmd_request = sdram_choose_cmd_valids; assign sdram_choose_cmd_cmd_valid = rhs_array_muxed0; assign sdram_choose_cmd_cmd_payload_a = rhs_array_muxed1; assign sdram_choose_cmd_cmd_payload_ba = rhs_array_muxed2; assign sdram_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign sdram_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign sdram_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin sdram_choose_cmd_cmd_payload_cas <= 1'd0; if (sdram_choose_cmd_cmd_valid) begin sdram_choose_cmd_cmd_payload_cas <= t_array_muxed0; end end always @(*) begin sdram_choose_cmd_cmd_payload_ras <= 1'd0; if (sdram_choose_cmd_cmd_valid) begin sdram_choose_cmd_cmd_payload_ras <= t_array_muxed1; end end always @(*) begin sdram_choose_cmd_cmd_payload_we <= 1'd0; if (sdram_choose_cmd_cmd_valid) begin sdram_choose_cmd_cmd_payload_we <= t_array_muxed2; end end assign sdram_choose_cmd_ce = (sdram_choose_cmd_cmd_ready | (~sdram_choose_cmd_cmd_valid)); always @(*) begin sdram_choose_req_valids <= 8'd0; sdram_choose_req_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[4] <= (sdram_bankmachine4_cmd_valid & (((sdram_bankmachine4_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine4_cmd_payload_ras & (~sdram_bankmachine4_cmd_payload_cas)) & (~sdram_bankmachine4_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine4_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine4_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[5] <= (sdram_bankmachine5_cmd_valid & (((sdram_bankmachine5_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine5_cmd_payload_ras & (~sdram_bankmachine5_cmd_payload_cas)) & (~sdram_bankmachine5_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine5_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine5_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[6] <= (sdram_bankmachine6_cmd_valid & (((sdram_bankmachine6_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine6_cmd_payload_ras & (~sdram_bankmachine6_cmd_payload_cas)) & (~sdram_bankmachine6_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine6_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine6_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[7] <= (sdram_bankmachine7_cmd_valid & (((sdram_bankmachine7_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine7_cmd_payload_ras & (~sdram_bankmachine7_cmd_payload_cas)) & (~sdram_bankmachine7_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine7_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine7_cmd_payload_is_write == sdram_choose_req_want_writes)))); end assign sdram_choose_req_request = sdram_choose_req_valids; assign sdram_choose_req_cmd_valid = rhs_array_muxed6; assign sdram_choose_req_cmd_payload_a = rhs_array_muxed7; assign sdram_choose_req_cmd_payload_ba = rhs_array_muxed8; assign sdram_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign sdram_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign sdram_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin sdram_choose_req_cmd_payload_cas <= 1'd0; if (sdram_choose_req_cmd_valid) begin sdram_choose_req_cmd_payload_cas <= t_array_muxed3; end end always @(*) begin sdram_choose_req_cmd_payload_ras <= 1'd0; if (sdram_choose_req_cmd_valid) begin sdram_choose_req_cmd_payload_ras <= t_array_muxed4; end end always @(*) begin sdram_choose_req_cmd_payload_we <= 1'd0; if (sdram_choose_req_cmd_valid) begin sdram_choose_req_cmd_payload_we <= t_array_muxed5; end end always @(*) begin sdram_bankmachine0_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd0))) begin sdram_bankmachine0_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd0))) begin sdram_bankmachine0_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine1_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd1))) begin sdram_bankmachine1_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd1))) begin sdram_bankmachine1_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine2_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd2))) begin sdram_bankmachine2_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd2))) begin sdram_bankmachine2_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine3_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd3))) begin sdram_bankmachine3_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd3))) begin sdram_bankmachine3_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine4_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 3'd4))) begin sdram_bankmachine4_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 3'd4))) begin sdram_bankmachine4_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine5_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 3'd5))) begin sdram_bankmachine5_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 3'd5))) begin sdram_bankmachine5_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine6_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 3'd6))) begin sdram_bankmachine6_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 3'd6))) begin sdram_bankmachine6_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine7_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 3'd7))) begin sdram_bankmachine7_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 3'd7))) begin sdram_bankmachine7_cmd_ready <= 1'd1; end end assign sdram_choose_req_ce = (sdram_choose_req_cmd_ready | (~sdram_choose_req_cmd_valid)); assign sdram_dfi_p0_reset_n = 1'd1; assign sdram_dfi_p0_cke = {1{sdram_steerer0}}; assign sdram_dfi_p0_odt = {1{sdram_steerer1}}; assign sdram_dfi_p1_reset_n = 1'd1; assign sdram_dfi_p1_cke = {1{sdram_steerer2}}; assign sdram_dfi_p1_odt = {1{sdram_steerer3}}; assign sdram_dfi_p2_reset_n = 1'd1; assign sdram_dfi_p2_cke = {1{sdram_steerer4}}; assign sdram_dfi_p2_odt = {1{sdram_steerer5}}; assign sdram_dfi_p3_reset_n = 1'd1; assign sdram_dfi_p3_cke = {1{sdram_steerer6}}; assign sdram_dfi_p3_odt = {1{sdram_steerer7}}; assign sdram_tfawcon_count = (((sdram_tfawcon_window[0] + sdram_tfawcon_window[1]) + sdram_tfawcon_window[2]) + sdram_tfawcon_window[3]); always @(*) begin sdram_choose_cmd_cmd_ready <= 1'd0; sdram_choose_req_want_reads <= 1'd0; sdram_choose_req_want_writes <= 1'd0; sdram_steerer_sel3 <= 2'd0; sdram_en1 <= 1'd0; sdram_choose_req_cmd_ready <= 1'd0; sdram_en0 <= 1'd0; subfragments_multiplexer_next_state <= 4'd0; sdram_steerer_sel0 <= 2'd0; sdram_cmd_ready <= 1'd0; sdram_steerer_sel1 <= 2'd0; sdram_steerer_sel2 <= 2'd0; sdram_choose_cmd_want_activates <= 1'd0; subfragments_multiplexer_next_state <= subfragments_multiplexer_state; case (subfragments_multiplexer_state) 1'd1: begin sdram_en1 <= 1'd1; sdram_choose_req_want_writes <= 1'd1; if (1'd0) begin sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed)); end else begin sdram_choose_cmd_want_activates <= sdram_ras_allowed; sdram_choose_cmd_cmd_ready <= ((~((sdram_choose_cmd_cmd_payload_ras & (~sdram_choose_cmd_cmd_payload_cas)) & (~sdram_choose_cmd_cmd_payload_we))) | sdram_ras_allowed); sdram_choose_req_cmd_ready <= sdram_cas_allowed; end sdram_steerer_sel0 <= 1'd0; if ((a7ddrphy_wrphase_storage == 1'd0)) begin sdram_steerer_sel0 <= 2'd2; end if ((sdram_wrcmdphase == 1'd0)) begin sdram_steerer_sel0 <= 1'd1; end sdram_steerer_sel1 <= 1'd0; if ((a7ddrphy_wrphase_storage == 1'd1)) begin sdram_steerer_sel1 <= 2'd2; end if ((sdram_wrcmdphase == 1'd1)) begin sdram_steerer_sel1 <= 1'd1; end sdram_steerer_sel2 <= 1'd0; if ((a7ddrphy_wrphase_storage == 2'd2)) begin sdram_steerer_sel2 <= 2'd2; end if ((sdram_wrcmdphase == 2'd2)) begin sdram_steerer_sel2 <= 1'd1; end sdram_steerer_sel3 <= 1'd0; if ((a7ddrphy_wrphase_storage == 2'd3)) begin sdram_steerer_sel3 <= 2'd2; end if ((sdram_wrcmdphase == 2'd3)) begin sdram_steerer_sel3 <= 1'd1; end if (sdram_read_available) begin if (((~sdram_write_available) | sdram_max_time1)) begin subfragments_multiplexer_next_state <= 2'd3; end end if (sdram_go_to_refresh) begin subfragments_multiplexer_next_state <= 2'd2; end end 2'd2: begin sdram_steerer_sel0 <= 2'd3; sdram_cmd_ready <= 1'd1; if (sdram_cmd_last) begin subfragments_multiplexer_next_state <= 1'd0; end end 2'd3: begin if (sdram_twtrcon_ready) begin subfragments_multiplexer_next_state <= 1'd0; end end 3'd4: begin subfragments_multiplexer_next_state <= 3'd5; end 3'd5: begin subfragments_multiplexer_next_state <= 3'd6; end 3'd6: begin subfragments_multiplexer_next_state <= 3'd7; end 3'd7: begin subfragments_multiplexer_next_state <= 4'd8; end 4'd8: begin subfragments_multiplexer_next_state <= 4'd9; end 4'd9: begin subfragments_multiplexer_next_state <= 4'd10; end 4'd10: begin subfragments_multiplexer_next_state <= 1'd1; end default: begin sdram_en0 <= 1'd1; sdram_choose_req_want_reads <= 1'd1; if (1'd0) begin sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed)); end else begin sdram_choose_cmd_want_activates <= sdram_ras_allowed; sdram_choose_cmd_cmd_ready <= ((~((sdram_choose_cmd_cmd_payload_ras & (~sdram_choose_cmd_cmd_payload_cas)) & (~sdram_choose_cmd_cmd_payload_we))) | sdram_ras_allowed); sdram_choose_req_cmd_ready <= sdram_cas_allowed; end sdram_steerer_sel0 <= 1'd0; if ((a7ddrphy_rdphase_storage == 1'd0)) begin sdram_steerer_sel0 <= 2'd2; end if ((sdram_rdcmdphase == 1'd0)) begin sdram_steerer_sel0 <= 1'd1; end sdram_steerer_sel1 <= 1'd0; if ((a7ddrphy_rdphase_storage == 1'd1)) begin sdram_steerer_sel1 <= 2'd2; end if ((sdram_rdcmdphase == 1'd1)) begin sdram_steerer_sel1 <= 1'd1; end sdram_steerer_sel2 <= 1'd0; if ((a7ddrphy_rdphase_storage == 2'd2)) begin sdram_steerer_sel2 <= 2'd2; end if ((sdram_rdcmdphase == 2'd2)) begin sdram_steerer_sel2 <= 1'd1; end sdram_steerer_sel3 <= 1'd0; if ((a7ddrphy_rdphase_storage == 2'd3)) begin sdram_steerer_sel3 <= 2'd2; end if ((sdram_rdcmdphase == 2'd3)) begin sdram_steerer_sel3 <= 1'd1; end if (sdram_write_available) begin if (((~sdram_read_available) | sdram_max_time0)) begin subfragments_multiplexer_next_state <= 3'd4; end end if (sdram_go_to_refresh) begin subfragments_multiplexer_next_state <= 2'd2; end end endcase end assign subfragments_roundrobin0_request = {(((port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin0_ce = ((~sdram_interface_bank0_valid) & (~sdram_interface_bank0_lock)); assign sdram_interface_bank0_addr = rhs_array_muxed12; assign sdram_interface_bank0_we = rhs_array_muxed13; assign sdram_interface_bank0_valid = rhs_array_muxed14; assign subfragments_roundrobin1_request = {(((port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin1_ce = ((~sdram_interface_bank1_valid) & (~sdram_interface_bank1_lock)); assign sdram_interface_bank1_addr = rhs_array_muxed15; assign sdram_interface_bank1_we = rhs_array_muxed16; assign sdram_interface_bank1_valid = rhs_array_muxed17; assign subfragments_roundrobin2_request = {(((port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin2_ce = ((~sdram_interface_bank2_valid) & (~sdram_interface_bank2_lock)); assign sdram_interface_bank2_addr = rhs_array_muxed18; assign sdram_interface_bank2_we = rhs_array_muxed19; assign sdram_interface_bank2_valid = rhs_array_muxed20; assign subfragments_roundrobin3_request = {(((port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin3_ce = ((~sdram_interface_bank3_valid) & (~sdram_interface_bank3_lock)); assign sdram_interface_bank3_addr = rhs_array_muxed21; assign sdram_interface_bank3_we = rhs_array_muxed22; assign sdram_interface_bank3_valid = rhs_array_muxed23; assign subfragments_roundrobin4_request = {(((port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((subfragments_locked4 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin4_ce = ((~sdram_interface_bank4_valid) & (~sdram_interface_bank4_lock)); assign sdram_interface_bank4_addr = rhs_array_muxed24; assign sdram_interface_bank4_we = rhs_array_muxed25; assign sdram_interface_bank4_valid = rhs_array_muxed26; assign subfragments_roundrobin5_request = {(((port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((subfragments_locked5 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin5_ce = ((~sdram_interface_bank5_valid) & (~sdram_interface_bank5_lock)); assign sdram_interface_bank5_addr = rhs_array_muxed27; assign sdram_interface_bank5_we = rhs_array_muxed28; assign sdram_interface_bank5_valid = rhs_array_muxed29; assign subfragments_roundrobin6_request = {(((port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((subfragments_locked6 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin6_ce = ((~sdram_interface_bank6_valid) & (~sdram_interface_bank6_lock)); assign sdram_interface_bank6_addr = rhs_array_muxed30; assign sdram_interface_bank6_we = rhs_array_muxed31; assign sdram_interface_bank6_valid = rhs_array_muxed32; assign subfragments_roundrobin7_request = {(((port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((subfragments_locked7 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin7_ce = ((~sdram_interface_bank7_valid) & (~sdram_interface_bank7_lock)); assign sdram_interface_bank7_addr = rhs_array_muxed33; assign sdram_interface_bank7_we = rhs_array_muxed34; assign sdram_interface_bank7_valid = rhs_array_muxed35; assign port_cmd_ready = ((((((((1'd0 | (((subfragments_roundrobin0_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank0_ready)) | (((subfragments_roundrobin1_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank1_ready)) | (((subfragments_roundrobin2_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank2_ready)) | (((subfragments_roundrobin3_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank3_ready)) | (((subfragments_roundrobin4_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((subfragments_locked4 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank4_ready)) | (((subfragments_roundrobin5_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((subfragments_locked5 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank5_ready)) | (((subfragments_roundrobin6_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((subfragments_locked6 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0)))))) & sdram_interface_bank6_ready)) | (((subfragments_roundrobin7_grant == 1'd0) & ((port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((subfragments_locked7 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0)))))) & sdram_interface_bank7_ready)); assign port_wdata_ready = subfragments_new_master_wdata_ready1; assign port_rdata_valid = subfragments_new_master_rdata_valid8; always @(*) begin sdram_interface_wdata <= 128'd0; sdram_interface_wdata_we <= 16'd0; case ({subfragments_new_master_wdata_ready1}) 1'd1: begin sdram_interface_wdata <= port_wdata_payload_data; sdram_interface_wdata_we <= port_wdata_payload_we; end default: begin sdram_interface_wdata <= 1'd0; sdram_interface_wdata_we <= 1'd0; end endcase end assign port_rdata_payload_data = sdram_interface_rdata; assign subfragments_roundrobin0_grant = 1'd0; assign subfragments_roundrobin1_grant = 1'd0; assign subfragments_roundrobin2_grant = 1'd0; assign subfragments_roundrobin3_grant = 1'd0; assign subfragments_roundrobin4_grant = 1'd0; assign subfragments_roundrobin5_grant = 1'd0; assign subfragments_roundrobin6_grant = 1'd0; assign subfragments_roundrobin7_grant = 1'd0; assign data_port_adr = wb_sdram_adr[10:2]; always @(*) begin data_port_we <= 16'd0; data_port_dat_w <= 128'd0; if (write_from_slave) begin data_port_dat_w <= interface_dat_r; data_port_we <= {16{1'd1}}; end else begin data_port_dat_w <= {4{wb_sdram_dat_w}}; if ((((wb_sdram_cyc & wb_sdram_stb) & wb_sdram_we) & wb_sdram_ack)) begin data_port_we <= {({4{(wb_sdram_adr[1:0] == 1'd0)}} & wb_sdram_sel), ({4{(wb_sdram_adr[1:0] == 1'd1)}} & wb_sdram_sel), ({4{(wb_sdram_adr[1:0] == 2'd2)}} & wb_sdram_sel), ({4{(wb_sdram_adr[1:0] == 2'd3)}} & wb_sdram_sel)}; end end end assign interface_dat_w = data_port_dat_r; assign interface_sel = 16'd65535; always @(*) begin wb_sdram_dat_r <= 32'd0; case (adr_offset_r) 1'd0: begin wb_sdram_dat_r <= data_port_dat_r[127:96]; end 1'd1: begin wb_sdram_dat_r <= data_port_dat_r[95:64]; end 2'd2: begin wb_sdram_dat_r <= data_port_dat_r[63:32]; end default: begin wb_sdram_dat_r <= data_port_dat_r[31:0]; end endcase end assign {tag_do_dirty, tag_do_tag} = tag_port_dat_r; assign tag_port_dat_w = {tag_di_dirty, tag_di_tag}; assign tag_port_adr = wb_sdram_adr[10:2]; assign tag_di_tag = wb_sdram_adr[29:11]; assign interface_adr = {tag_do_tag, wb_sdram_adr[10:2]}; always @(*) begin write_from_slave <= 1'd0; subfragments_fullmemorywe_next_state <= 2'd0; interface_cyc <= 1'd0; interface_stb <= 1'd0; tag_port_we <= 1'd0; interface_we <= 1'd0; wb_sdram_ack <= 1'd0; tag_di_dirty <= 1'd0; word_clr <= 1'd0; word_inc <= 1'd0; subfragments_fullmemorywe_next_state <= subfragments_fullmemorywe_state; case (subfragments_fullmemorywe_state) 1'd1: begin word_clr <= 1'd1; if ((tag_do_tag == wb_sdram_adr[29:11])) begin wb_sdram_ack <= 1'd1; if (wb_sdram_we) begin tag_di_dirty <= 1'd1; tag_port_we <= 1'd1; end subfragments_fullmemorywe_next_state <= 1'd0; end else begin if (tag_do_dirty) begin subfragments_fullmemorywe_next_state <= 2'd2; end else begin tag_port_we <= 1'd1; word_clr <= 1'd1; subfragments_fullmemorywe_next_state <= 2'd3; end end end 2'd2: begin interface_stb <= 1'd1; interface_cyc <= 1'd1; interface_we <= 1'd1; if (interface_ack) begin word_inc <= 1'd1; if (1'd1) begin tag_port_we <= 1'd1; word_clr <= 1'd1; subfragments_fullmemorywe_next_state <= 2'd3; end end end 2'd3: begin interface_stb <= 1'd1; interface_cyc <= 1'd1; interface_we <= 1'd0; if (interface_ack) begin write_from_slave <= 1'd1; word_inc <= 1'd1; if (1'd1) begin subfragments_fullmemorywe_next_state <= 1'd1; end else begin subfragments_fullmemorywe_next_state <= 2'd3; end end end default: begin if ((wb_sdram_cyc & wb_sdram_stb)) begin subfragments_fullmemorywe_next_state <= 1'd1; end end endcase end assign port_cmd_payload_addr = (interface_adr - 27'd67108864); assign port_cmd_payload_we = interface_we; assign port_wdata_payload_data = interface_dat_w; assign port_wdata_payload_we = interface_sel; assign interface_dat_r = port_rdata_payload_data; assign port_flush = (~interface_cyc); assign port_cmd_last = (~interface_we); assign port_cmd_valid = ((interface_cyc & interface_stb) & (~cmd_consumed)); assign port_wdata_valid = (((port_cmd_valid | cmd_consumed) & port_cmd_payload_we) & (~wdata_consumed)); assign port_rdata_ready = ((port_cmd_valid | cmd_consumed) & (~port_cmd_payload_we)); assign interface_ack = (ack_cmd & ((interface_we & ack_wdata) | ((~interface_we) & ack_rdata))); assign ack_cmd = ((port_cmd_valid & port_cmd_ready) | cmd_consumed); assign ack_wdata = ((port_wdata_valid & port_wdata_ready) | wdata_consumed); assign ack_rdata = (port_rdata_valid & port_rdata_ready); assign ctrl_rx_idle = datapath_rx_idle; assign ctrl_misalign = datapath_misalign; assign a7litesataphy_tx_init_restart = (~enable); assign a7litesataphy_rx_init_restart = ((~enable) | ctrl_rx_reset); assign ready = (a7litesataphy_ready & ctrl_ready); assign enable = litesataphy_enable_storage; assign litesataphy_ready = (a7litesataphy_ready & ctrl_ready); assign litesataphy_tx_ready = a7litesataphy_tx_init_done; assign litesataphy_rx_ready = a7litesataphy_rx_init_done; assign litesataphy_ctrl_ready = ctrl_ready; assign a7litesataphy_tx_init_plllock0 = a7litesataphy_qplllock; assign a7litesataphy_rx_init_plllock0 = a7litesataphy_qplllock; assign a7litesataphy_ready = (a7litesataphy_tx_init_done & a7litesataphy_rx_init_done); assign a7litesataphy_txelecidle0 = (a7litesataphy_tx_idle | a7litesataphy_txpd0); assign a7litesataphy_tx_cominit_ack = (a7litesataphy_tx_cominit_stb & a7litesataphy_txcomfinish0); assign a7litesataphy_tx_comwake_ack = (a7litesataphy_tx_comwake_stb & a7litesataphy_txcomfinish0); assign a7litesataphy_rx_cominit_stb = a7litesataphy_rxcominitdet0; assign a7litesataphy_rx_comwake_stb = a7litesataphy_rxcomwakedet0; assign a7litesataphy_qplllock = a7litesataphy_qpll_lock; assign a7litesataphy_qpll_reset = a7litesataphy_tx_init_pllreset; assign a7litesataphy_tx_init_txphaligndone_rising = (a7litesataphy_tx_init_txphaligndone1 & (~a7litesataphy_tx_init_txphaligndone_r)); assign a7litesataphy_tx_init_init_delay_wait = 1'd1; assign a7litesataphy_tx_init_watchdog_wait = ((~a7litesataphy_tx_init_reset) & (~a7litesataphy_tx_init_done)); assign a7litesataphy_tx_init_reset = (a7litesataphy_tx_init_restart | a7litesataphy_tx_init_watchdog_done); always @(*) begin a7litesataphy_tx_init_txdlysreset1 <= 1'd0; a7litesataphy_tx_init_txphinit1 <= 1'd0; a7litesataphy_tx_init_txphalign1 <= 1'd0; a7litesataphy_tx_init_txdlyen1 <= 1'd0; a7litesataphy_tx_init_txuserrdy1 <= 1'd0; a7litesataphy_tx_init_drp_start <= 1'd0; a7litesataphy_tx_init_done <= 1'd0; a7litesataphy_tx_init_pllreset <= 1'd0; subfragments_litesataphy_gtptxinit_next_state <= 4'd0; a7litesataphy_tx_init_gttxreset1 <= 1'd0; a7litesataphy_tx_init_gttxpd1 <= 1'd0; subfragments_litesataphy_gtptxinit_next_state <= subfragments_litesataphy_gtptxinit_state; case (subfragments_litesataphy_gtptxinit_state) 1'd1: begin a7litesataphy_tx_init_gttxreset1 <= 1'd1; a7litesataphy_tx_init_pllreset <= 1'd1; a7litesataphy_tx_init_drp_start <= 1'd1; if (a7litesataphy_tx_init_drp_done) begin subfragments_litesataphy_gtptxinit_next_state <= 2'd2; end end 2'd2: begin a7litesataphy_tx_init_gttxreset1 <= 1'd1; if (a7litesataphy_tx_init_plllock1) begin subfragments_litesataphy_gtptxinit_next_state <= 2'd3; end end 2'd3: begin a7litesataphy_tx_init_gttxreset1 <= 1'd1; if (a7litesataphy_tx_init_init_delay_done) begin subfragments_litesataphy_gtptxinit_next_state <= 3'd4; end end 3'd4: begin a7litesataphy_tx_init_txuserrdy1 <= 1'd1; if (a7litesataphy_tx_init_txresetdone1) begin if (1'd1) begin subfragments_litesataphy_gtptxinit_next_state <= 4'd9; end else begin subfragments_litesataphy_gtptxinit_next_state <= 3'd5; end end end 3'd5: begin a7litesataphy_tx_init_txuserrdy1 <= 1'd1; a7litesataphy_tx_init_txdlysreset1 <= 1'd1; if (a7litesataphy_tx_init_txdlysresetdone1) begin subfragments_litesataphy_gtptxinit_next_state <= 3'd6; end end 3'd6: begin a7litesataphy_tx_init_txuserrdy1 <= 1'd1; a7litesataphy_tx_init_txphinit1 <= 1'd1; if (a7litesataphy_tx_init_txphinitdone1) begin subfragments_litesataphy_gtptxinit_next_state <= 3'd7; end end 3'd7: begin a7litesataphy_tx_init_txuserrdy1 <= 1'd1; a7litesataphy_tx_init_txphalign1 <= 1'd1; if (a7litesataphy_tx_init_txphaligndone_rising) begin subfragments_litesataphy_gtptxinit_next_state <= 4'd8; end end 4'd8: begin a7litesataphy_tx_init_txuserrdy1 <= 1'd1; a7litesataphy_tx_init_txdlyen1 <= 1'd1; if (a7litesataphy_tx_init_txphaligndone_rising) begin subfragments_litesataphy_gtptxinit_next_state <= 4'd9; end end 4'd9: begin a7litesataphy_tx_init_txuserrdy1 <= 1'd1; a7litesataphy_tx_init_txdlyen1 <= 1'd1; a7litesataphy_tx_init_done <= 1'd1; if (a7litesataphy_tx_init_restart) begin subfragments_litesataphy_gtptxinit_next_state <= 1'd0; end end default: begin a7litesataphy_tx_init_gttxreset1 <= 1'd1; a7litesataphy_tx_init_gttxpd1 <= 1'd1; a7litesataphy_tx_init_pllreset <= 1'd1; subfragments_litesataphy_gtptxinit_next_state <= 1'd1; end endcase end assign a7litesataphy_tx_init_init_delay_done = (a7litesataphy_tx_init_init_delay_count == 1'd0); assign a7litesataphy_tx_init_watchdog_done = (a7litesataphy_tx_init_watchdog_count == 1'd0); assign a7litesataphy_rx_init_drp_clk = sys_clk; assign a7litesataphy_rx_init_drp_addr = 5'd17; always @(*) begin a7litesataphy_rx_init_drp_di <= 16'd0; if (a7litesataphy_rx_init_drpmask) begin a7litesataphy_rx_init_drp_di <= (a7litesataphy_rx_init_drpvalue & 16'd63487); end else begin a7litesataphy_rx_init_drp_di <= a7litesataphy_rx_init_drpvalue; end end assign a7litesataphy_rx_init_init_delay_wait = 1'd1; assign a7litesataphy_rx_init_watchdog_wait = ((~a7litesataphy_rx_init_reset) & (~a7litesataphy_rx_init_done)); assign a7litesataphy_rx_init_reset = (a7litesataphy_rx_init_restart | a7litesataphy_rx_init_watchdog_done); always @(*) begin a7litesataphy_rx_init_gtrxreset1 <= 1'd0; a7litesataphy_rx_init_done <= 1'd0; a7litesataphy_rx_init_gtrxpd1 <= 1'd0; a7litesataphy_rx_init_rxdlysreset1 <= 1'd0; a7litesataphy_rx_init_drp_we <= 1'd0; a7litesataphy_rx_init_rxuserrdy1 <= 1'd0; a7litesataphy_rx_init_drpmask <= 1'd0; a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value_ce <= 1'd0; subfragments_litesataphy_gtprxinit_next_state <= 4'd0; a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value <= 16'd0; a7litesataphy_rx_init_drp_en <= 1'd0; subfragments_litesataphy_gtprxinit_next_state <= subfragments_litesataphy_gtprxinit_state; case (subfragments_litesataphy_gtprxinit_state) 1'd1: begin a7litesataphy_rx_init_gtrxreset1 <= 1'd1; if ((a7litesataphy_rx_init_plllock1 & a7litesataphy_rx_init_init_delay_done)) begin subfragments_litesataphy_gtprxinit_next_state <= 2'd2; end end 2'd2: begin a7litesataphy_rx_init_gtrxreset1 <= 1'd1; a7litesataphy_rx_init_drp_en <= 1'd1; subfragments_litesataphy_gtprxinit_next_state <= 2'd3; end 2'd3: begin a7litesataphy_rx_init_gtrxreset1 <= 1'd1; if (a7litesataphy_rx_init_drp_rdy) begin a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value <= a7litesataphy_rx_init_drp_do; a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value_ce <= 1'd1; subfragments_litesataphy_gtprxinit_next_state <= 3'd4; end end 3'd4: begin a7litesataphy_rx_init_gtrxreset1 <= 1'd1; a7litesataphy_rx_init_drpmask <= 1'd1; a7litesataphy_rx_init_drp_en <= 1'd1; a7litesataphy_rx_init_drp_we <= 1'd1; subfragments_litesataphy_gtprxinit_next_state <= 3'd5; end 3'd5: begin a7litesataphy_rx_init_gtrxreset1 <= 1'd1; if (a7litesataphy_rx_init_drp_rdy) begin subfragments_litesataphy_gtprxinit_next_state <= 3'd6; end end 3'd6: begin a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; if ((a7litesataphy_rx_init_rxpmaresetdone_r & (~a7litesataphy_rx_init_rxpmaresetdone1))) begin subfragments_litesataphy_gtprxinit_next_state <= 3'd7; end end 3'd7: begin a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; a7litesataphy_rx_init_drp_en <= 1'd1; a7litesataphy_rx_init_drp_we <= 1'd1; subfragments_litesataphy_gtprxinit_next_state <= 4'd8; end 4'd8: begin a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; if (a7litesataphy_rx_init_drp_rdy) begin subfragments_litesataphy_gtprxinit_next_state <= 4'd9; end end 4'd9: begin a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; if (a7litesataphy_rx_init_rxresetdone1) begin if (1'd0) begin subfragments_litesataphy_gtprxinit_next_state <= 4'd12; end else begin subfragments_litesataphy_gtprxinit_next_state <= 4'd10; end end end 4'd10: begin a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; a7litesataphy_rx_init_rxdlysreset1 <= 1'd1; if (a7litesataphy_rx_init_rxdlysresetdone1) begin subfragments_litesataphy_gtprxinit_next_state <= 4'd11; end end 4'd11: begin a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; if (a7litesataphy_rx_init_rxsyncdone1) begin subfragments_litesataphy_gtprxinit_next_state <= 4'd12; end end 4'd12: begin a7litesataphy_rx_init_rxuserrdy1 <= 1'd1; a7litesataphy_rx_init_done <= 1'd1; if (a7litesataphy_rx_init_restart) begin subfragments_litesataphy_gtprxinit_next_state <= 1'd0; end end default: begin a7litesataphy_rx_init_gtrxreset1 <= 1'd1; a7litesataphy_rx_init_gtrxpd1 <= 1'd1; subfragments_litesataphy_gtprxinit_next_state <= 1'd1; end endcase end assign a7litesataphy_rx_init_init_delay_done = (a7litesataphy_rx_init_init_delay_count == 1'd0); assign a7litesataphy_rx_init_watchdog_done = (a7litesataphy_rx_init_watchdog_count == 1'd0); assign a7litesataphy_txcominit0 = (a7litesataphy_tx_cominit_stb & (~a7litesataphy_i_d0)); assign a7litesataphy_txcomwake0 = (a7litesataphy_tx_comwake_stb & (~a7litesataphy_i_d1)); assign a7litesataphy_pulsesynchronizer0_o = (a7litesataphy_pulsesynchronizer0_toggle_o ^ a7litesataphy_pulsesynchronizer0_toggle_o_r); assign a7litesataphy_pulsesynchronizer0_i = a7litesataphy_txcominit0; assign a7litesataphy_txcominit1 = a7litesataphy_pulsesynchronizer0_o; assign a7litesataphy_pulsesynchronizer1_o = (a7litesataphy_pulsesynchronizer1_toggle_o ^ a7litesataphy_pulsesynchronizer1_toggle_o_r); assign a7litesataphy_pulsesynchronizer1_i = a7litesataphy_txcomwake0; assign a7litesataphy_txcomwake1 = a7litesataphy_pulsesynchronizer1_o; assign a7litesataphy_pulsesynchronizer2_o = (a7litesataphy_pulsesynchronizer2_toggle_o ^ a7litesataphy_pulsesynchronizer2_toggle_o_r); assign a7litesataphy_pulsesynchronizer2_i = a7litesataphy_txcomfinish1; assign a7litesataphy_txcomfinish0 = a7litesataphy_pulsesynchronizer2_o; assign a7litesataphy_gtrefclk0 = crg_refclk; assign a7litesataphy_txusrclk = sata_tx_clk; assign a7litesataphy_txusrclk2 = sata_tx_clk; assign a7litesataphy_rxusrclk = sata_rx_clk; assign a7litesataphy_rxusrclk2 = sata_rx_clk; assign ctrl_source_valid = 1'd1; assign ctrl_sink_ready = 1'd1; assign ctrl_reset = (ctrl_retry_timer_done | ctrl_align_timer_done); assign ctrl_align_timer_done = (ctrl_align_timer_count == 1'd0); assign ctrl_retry_timer_done = (ctrl_retry_timer_count == 1'd0); always @(*) begin ctrl_stability_timer_wait <= 1'd0; ctrl_ready <= 1'd0; a7litesataphy_tx_cominit_stb <= 1'd0; a7litesataphy_tx_comwake_stb <= 1'd0; a7litesataphy_rx_cdrhold <= 1'd0; subfragments_litesataphy_next_state <= 4'd0; ctrl_source_payload_data <= 32'd0; ctrl_align_count_subfragments_litesataphyctrl_next_value0 <= 4'd0; ctrl_source_payload_charisk <= 4'd0; ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 <= 1'd0; ctrl_tx_idle <= 1'd0; ctrl_rx_reset <= 1'd0; a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 <= 1'd0; ctrl_tx_reset <= 1'd0; a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 <= 1'd0; a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value2 <= 1'd0; a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value_ce2 <= 1'd0; ctrl_retry_timer_wait <= 1'd0; ctrl_align_timer_wait <= 1'd0; subfragments_litesataphy_next_state <= subfragments_litesataphy_state; case (subfragments_litesataphy_state) 1'd1: begin ctrl_tx_idle <= 1'd1; a7litesataphy_rx_cdrhold <= 1'd1; ctrl_align_count_subfragments_litesataphyctrl_next_value0 <= 2'd3; ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 <= 1'd1; if (a7litesataphy_ready) begin a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 <= 1'd0; a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 <= 1'd1; a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value2 <= (~a7litesataphy_tx_polarity); a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value_ce2 <= 1'd1; subfragments_litesataphy_next_state <= 2'd2; end end 2'd2: begin ctrl_tx_idle <= 1'd1; a7litesataphy_rx_cdrhold <= 1'd1; a7litesataphy_tx_cominit_stb <= 1'd1; if ((a7litesataphy_tx_cominit_ack & (~a7litesataphy_rx_cominit_stb))) begin subfragments_litesataphy_next_state <= 2'd3; end end 2'd3: begin ctrl_tx_idle <= 1'd1; a7litesataphy_rx_cdrhold <= 1'd1; ctrl_retry_timer_wait <= 1'd1; if (a7litesataphy_rx_cominit_stb) begin subfragments_litesataphy_next_state <= 3'd4; end end 3'd4: begin ctrl_tx_idle <= 1'd1; a7litesataphy_rx_cdrhold <= 1'd1; ctrl_retry_timer_wait <= 1'd1; if ((~a7litesataphy_rx_cominit_stb)) begin subfragments_litesataphy_next_state <= 3'd5; end end 3'd5: begin ctrl_tx_idle <= 1'd1; a7litesataphy_rx_cdrhold <= 1'd1; subfragments_litesataphy_next_state <= 3'd6; end 3'd6: begin ctrl_tx_idle <= 1'd1; a7litesataphy_rx_cdrhold <= 1'd1; a7litesataphy_tx_comwake_stb <= 1'd1; if (a7litesataphy_tx_comwake_ack) begin subfragments_litesataphy_next_state <= 3'd7; end end 3'd7: begin ctrl_tx_idle <= 1'd1; a7litesataphy_rx_cdrhold <= 1'd1; ctrl_retry_timer_wait <= 1'd1; if (a7litesataphy_rx_comwake_stb) begin subfragments_litesataphy_next_state <= 4'd8; end end 4'd8: begin ctrl_tx_idle <= 1'd1; a7litesataphy_rx_cdrhold <= 1'd1; if ((~a7litesataphy_rx_comwake_stb)) begin subfragments_litesataphy_next_state <= 4'd9; end end 4'd9: begin a7litesataphy_rx_cdrhold <= 1'd1; ctrl_source_payload_data <= 31'd1246382666; ctrl_source_payload_charisk <= 1'd0; ctrl_align_timer_wait <= 1'd1; if ((~a7litesataphy_rx_idle)) begin if (((ctrl_sink_valid & (ctrl_sink_payload_charisk == 1'd1)) & (ctrl_sink_payload_data == 31'd2068466364))) begin a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 <= 1'd0; a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 <= 1'd1; subfragments_litesataphy_next_state <= 4'd10; end if (((ctrl_sink_valid & (ctrl_sink_payload_charisk == 1'd1)) & (ctrl_sink_payload_data == 31'd2075506108))) begin a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1 <= 1'd1; a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1 <= 1'd1; subfragments_litesataphy_next_state <= 4'd10; end end end 4'd10: begin ctrl_align_timer_wait <= 1'd1; ctrl_source_payload_data <= 31'd2068466364; ctrl_source_payload_charisk <= 1'd1; if ((ctrl_sink_valid & (ctrl_sink_payload_charisk == 1'd1))) begin if ((ctrl_sink_payload_data[7:0] == 7'd124)) begin ctrl_align_count_subfragments_litesataphyctrl_next_value0 <= (ctrl_align_count - 1'd1); ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 <= 1'd1; end else begin ctrl_align_count_subfragments_litesataphyctrl_next_value0 <= 2'd3; ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0 <= 1'd1; end end if ((ctrl_align_count == 1'd0)) begin subfragments_litesataphy_next_state <= 4'd11; end end 4'd11: begin ctrl_source_payload_data <= 32'd3048576380; ctrl_source_payload_charisk <= 1'd1; ctrl_stability_timer_wait <= 1'd1; ctrl_ready <= ctrl_stability_timer_done; if (ctrl_rx_idle) begin subfragments_litesataphy_next_state <= 1'd0; end else begin if (ctrl_misalign) begin ctrl_rx_reset <= 1'd1; subfragments_litesataphy_next_state <= 4'd12; end end end 4'd12: begin if (a7litesataphy_ready) begin subfragments_litesataphy_next_state <= 4'd11; end end default: begin ctrl_tx_idle <= 1'd1; a7litesataphy_rx_cdrhold <= 1'd1; ctrl_rx_reset <= 1'd1; ctrl_tx_reset <= 1'd1; subfragments_litesataphy_next_state <= 1'd1; end endcase end assign ctrl_stability_timer_done = (ctrl_stability_timer_count == 1'd0); assign datapath_mux_sel = ctrl_ready; assign datapath_mux_endpoint0_sink_valid = ctrl_source_valid; assign ctrl_source_ready = datapath_mux_endpoint0_sink_ready; assign datapath_mux_endpoint0_sink_first = ctrl_source_first; assign datapath_mux_endpoint0_sink_last = ctrl_source_last; assign datapath_mux_endpoint0_sink_payload_data = ctrl_source_payload_data; assign datapath_mux_endpoint0_sink_payload_charisk = ctrl_source_payload_charisk; assign datapath_mux_endpoint1_sink_valid = datapath_sink_sink_valid; assign datapath_sink_sink_ready = datapath_mux_endpoint1_sink_ready; assign datapath_mux_endpoint1_sink_first = datapath_sink_sink_first; assign datapath_mux_endpoint1_sink_last = datapath_sink_sink_last; assign datapath_mux_endpoint1_sink_payload_data = datapath_sink_sink_payload_data; assign datapath_mux_endpoint1_sink_payload_charisk = datapath_sink_sink_payload_charisk; assign datapath_tx_sink_sink_valid = datapath_mux_source_valid; assign datapath_mux_source_ready = datapath_tx_sink_sink_ready; assign datapath_tx_sink_sink_first = datapath_mux_source_first; assign datapath_tx_sink_sink_last = datapath_mux_source_last; assign datapath_tx_sink_sink_payload_data = datapath_mux_source_payload_data; assign datapath_tx_sink_sink_payload_charisk = datapath_mux_source_payload_charisk; assign a7litesataphy_sink_valid = datapath_tx_source_source_valid; assign datapath_tx_source_source_ready = a7litesataphy_sink_ready; assign a7litesataphy_sink_first = datapath_tx_source_source_first; assign a7litesataphy_sink_last = datapath_tx_source_source_last; assign a7litesataphy_sink_payload_data = datapath_tx_source_source_payload_data; assign a7litesataphy_sink_payload_charisk = datapath_tx_source_source_payload_charisk; assign datapath_demux_sel = ctrl_ready; assign datapath_rx_sink_sink_valid = a7litesataphy_source_valid; assign a7litesataphy_source_ready = datapath_rx_sink_sink_ready; assign datapath_rx_sink_sink_first = a7litesataphy_source_first; assign datapath_rx_sink_sink_last = a7litesataphy_source_last; assign datapath_rx_sink_sink_payload_data = a7litesataphy_source_payload_data; assign datapath_rx_sink_sink_payload_charisk = a7litesataphy_source_payload_charisk; assign datapath_demux_sink_valid = datapath_rx_source_source_valid; assign datapath_rx_source_source_ready = datapath_demux_sink_ready; assign datapath_demux_sink_first = datapath_rx_source_source_first; assign datapath_demux_sink_last = datapath_rx_source_source_last; assign datapath_demux_sink_payload_data = datapath_rx_source_source_payload_data; assign datapath_demux_sink_payload_charisk = datapath_rx_source_source_payload_charisk; assign datapath_align_timer_sink_valid = datapath_rx_source_source_valid; assign datapath_align_timer_sink_first = datapath_rx_source_source_first; assign datapath_align_timer_sink_last = datapath_rx_source_source_last; assign datapath_align_timer_sink_payload_data = datapath_rx_source_source_payload_data; assign datapath_align_timer_sink_payload_charisk = datapath_rx_source_source_payload_charisk; assign ctrl_sink_valid = datapath_demux_endpoint0_source_valid; assign datapath_demux_endpoint0_source_ready = ctrl_sink_ready; assign ctrl_sink_first = datapath_demux_endpoint0_source_first; assign ctrl_sink_last = datapath_demux_endpoint0_source_last; assign ctrl_sink_payload_data = datapath_demux_endpoint0_source_payload_data; assign ctrl_sink_payload_charisk = datapath_demux_endpoint0_source_payload_charisk; assign datapath_source_source_valid = datapath_demux_endpoint1_source_valid; assign datapath_demux_endpoint1_source_ready = datapath_source_source_ready; assign datapath_source_source_first = datapath_demux_endpoint1_source_first; assign datapath_source_source_last = datapath_demux_endpoint1_source_last; assign datapath_source_source_payload_data = datapath_demux_endpoint1_source_payload_data; assign datapath_source_source_payload_charisk = datapath_demux_endpoint1_source_payload_charisk; assign datapath_misalign = (datapath_rx_source_source_valid & ((datapath_rx_source_source_payload_charisk & 4'd14) != 1'd0)); assign datapath_rx_idle = datapath_align_timer_done; always @(*) begin datapath_mux_source_payload_charisk <= 4'd0; datapath_mux_endpoint0_sink_ready <= 1'd0; datapath_mux_source_valid <= 1'd0; datapath_mux_source_first <= 1'd0; datapath_mux_source_last <= 1'd0; datapath_mux_source_payload_data <= 32'd0; datapath_mux_endpoint1_sink_ready <= 1'd0; case (datapath_mux_sel) 1'd0: begin datapath_mux_source_valid <= datapath_mux_endpoint0_sink_valid; datapath_mux_endpoint0_sink_ready <= datapath_mux_source_ready; datapath_mux_source_first <= datapath_mux_endpoint0_sink_first; datapath_mux_source_last <= datapath_mux_endpoint0_sink_last; datapath_mux_source_payload_data <= datapath_mux_endpoint0_sink_payload_data; datapath_mux_source_payload_charisk <= datapath_mux_endpoint0_sink_payload_charisk; end 1'd1: begin datapath_mux_source_valid <= datapath_mux_endpoint1_sink_valid; datapath_mux_endpoint1_sink_ready <= datapath_mux_source_ready; datapath_mux_source_first <= datapath_mux_endpoint1_sink_first; datapath_mux_source_last <= datapath_mux_endpoint1_sink_last; datapath_mux_source_payload_data <= datapath_mux_endpoint1_sink_payload_data; datapath_mux_source_payload_charisk <= datapath_mux_endpoint1_sink_payload_charisk; end endcase end assign datapath_tx_fifo_sink_valid = datapath_tx_sink_sink_valid; assign datapath_tx_sink_sink_ready = datapath_tx_fifo_sink_ready; assign datapath_tx_fifo_sink_first = datapath_tx_sink_sink_first; assign datapath_tx_fifo_sink_last = datapath_tx_sink_sink_last; assign datapath_tx_fifo_sink_payload_data = datapath_tx_sink_sink_payload_data; assign datapath_tx_fifo_sink_payload_charisk = datapath_tx_sink_sink_payload_charisk; assign datapath_tx_converter_sink_valid = datapath_tx_fifo_source_valid; assign datapath_tx_fifo_source_ready = datapath_tx_converter_sink_ready; assign datapath_tx_converter_sink_first = datapath_tx_fifo_source_first; assign datapath_tx_converter_sink_last = datapath_tx_fifo_source_last; assign datapath_tx_converter_sink_payload_data = datapath_tx_fifo_source_payload_data; assign datapath_tx_converter_sink_payload_charisk = datapath_tx_fifo_source_payload_charisk; assign datapath_tx_source_source_valid = datapath_tx_converter_source_valid; assign datapath_tx_converter_source_ready = datapath_tx_source_source_ready; assign datapath_tx_source_source_first = datapath_tx_converter_source_first; assign datapath_tx_source_source_last = datapath_tx_converter_source_last; assign datapath_tx_source_source_payload_data = datapath_tx_converter_source_payload_data; assign datapath_tx_source_source_payload_charisk = datapath_tx_converter_source_payload_charisk; assign datapath_tx_fifo_asyncfifo_din = {datapath_tx_fifo_fifo_in_last, datapath_tx_fifo_fifo_in_first, datapath_tx_fifo_fifo_in_payload_charisk, datapath_tx_fifo_fifo_in_payload_data}; assign {datapath_tx_fifo_fifo_out_last, datapath_tx_fifo_fifo_out_first, datapath_tx_fifo_fifo_out_payload_charisk, datapath_tx_fifo_fifo_out_payload_data} = datapath_tx_fifo_asyncfifo_dout; assign datapath_tx_fifo_sink_ready = datapath_tx_fifo_asyncfifo_writable; assign datapath_tx_fifo_asyncfifo_we = datapath_tx_fifo_sink_valid; assign datapath_tx_fifo_fifo_in_first = datapath_tx_fifo_sink_first; assign datapath_tx_fifo_fifo_in_last = datapath_tx_fifo_sink_last; assign datapath_tx_fifo_fifo_in_payload_data = datapath_tx_fifo_sink_payload_data; assign datapath_tx_fifo_fifo_in_payload_charisk = datapath_tx_fifo_sink_payload_charisk; assign datapath_tx_fifo_source_valid = datapath_tx_fifo_asyncfifo_readable; assign datapath_tx_fifo_source_first = datapath_tx_fifo_fifo_out_first; assign datapath_tx_fifo_source_last = datapath_tx_fifo_fifo_out_last; assign datapath_tx_fifo_source_payload_data = datapath_tx_fifo_fifo_out_payload_data; assign datapath_tx_fifo_source_payload_charisk = datapath_tx_fifo_fifo_out_payload_charisk; assign datapath_tx_fifo_asyncfifo_re = datapath_tx_fifo_source_ready; assign datapath_tx_fifo_graycounter0_ce = (datapath_tx_fifo_asyncfifo_writable & datapath_tx_fifo_asyncfifo_we); assign datapath_tx_fifo_graycounter1_ce = (datapath_tx_fifo_asyncfifo_readable & datapath_tx_fifo_asyncfifo_re); assign datapath_tx_fifo_asyncfifo_writable = (((datapath_tx_fifo_graycounter0_q[3] == datapath_tx_fifo_consume_wdomain[3]) | (datapath_tx_fifo_graycounter0_q[2] == datapath_tx_fifo_consume_wdomain[2])) | (datapath_tx_fifo_graycounter0_q[1:0] != datapath_tx_fifo_consume_wdomain[1:0])); assign datapath_tx_fifo_asyncfifo_readable = (datapath_tx_fifo_graycounter1_q != datapath_tx_fifo_produce_rdomain); assign datapath_tx_fifo_wrport_adr = datapath_tx_fifo_graycounter0_q_binary[2:0]; assign datapath_tx_fifo_wrport_dat_w = datapath_tx_fifo_asyncfifo_din; assign datapath_tx_fifo_wrport_we = datapath_tx_fifo_graycounter0_ce; assign datapath_tx_fifo_rdport_adr = datapath_tx_fifo_graycounter1_q_next_binary[2:0]; assign datapath_tx_fifo_asyncfifo_dout = datapath_tx_fifo_rdport_dat_r; always @(*) begin datapath_tx_fifo_graycounter0_q_next_binary <= 4'd0; if (datapath_tx_fifo_graycounter0_ce) begin datapath_tx_fifo_graycounter0_q_next_binary <= (datapath_tx_fifo_graycounter0_q_binary + 1'd1); end else begin datapath_tx_fifo_graycounter0_q_next_binary <= datapath_tx_fifo_graycounter0_q_binary; end end assign datapath_tx_fifo_graycounter0_q_next = (datapath_tx_fifo_graycounter0_q_next_binary ^ datapath_tx_fifo_graycounter0_q_next_binary[3:1]); always @(*) begin datapath_tx_fifo_graycounter1_q_next_binary <= 4'd0; if (datapath_tx_fifo_graycounter1_ce) begin datapath_tx_fifo_graycounter1_q_next_binary <= (datapath_tx_fifo_graycounter1_q_binary + 1'd1); end else begin datapath_tx_fifo_graycounter1_q_next_binary <= datapath_tx_fifo_graycounter1_q_binary; end end assign datapath_tx_fifo_graycounter1_q_next = (datapath_tx_fifo_graycounter1_q_next_binary ^ datapath_tx_fifo_graycounter1_q_next_binary[3:1]); assign datapath_tx_converter_converter_sink_valid = datapath_tx_converter_sink_valid; assign datapath_tx_converter_converter_sink_first = datapath_tx_converter_sink_first; assign datapath_tx_converter_converter_sink_last = datapath_tx_converter_sink_last; assign datapath_tx_converter_sink_ready = datapath_tx_converter_converter_sink_ready; always @(*) begin datapath_tx_converter_converter_sink_payload_data <= 36'd0; datapath_tx_converter_converter_sink_payload_data[15:0] <= datapath_tx_converter_sink_payload_data[15:0]; datapath_tx_converter_converter_sink_payload_data[17:16] <= datapath_tx_converter_sink_payload_charisk[1:0]; datapath_tx_converter_converter_sink_payload_data[33:18] <= datapath_tx_converter_sink_payload_data[31:16]; datapath_tx_converter_converter_sink_payload_data[35:34] <= datapath_tx_converter_sink_payload_charisk[3:2]; end assign datapath_tx_converter_source_valid = datapath_tx_converter_source_source_valid; assign datapath_tx_converter_source_first = datapath_tx_converter_source_source_first; assign datapath_tx_converter_source_last = datapath_tx_converter_source_source_last; assign datapath_tx_converter_source_source_ready = datapath_tx_converter_source_ready; assign {datapath_tx_converter_source_payload_charisk, datapath_tx_converter_source_payload_data} = datapath_tx_converter_source_source_payload_data; assign datapath_tx_converter_source_source_valid = datapath_tx_converter_converter_source_valid; assign datapath_tx_converter_converter_source_ready = datapath_tx_converter_source_source_ready; assign datapath_tx_converter_source_source_first = datapath_tx_converter_converter_source_first; assign datapath_tx_converter_source_source_last = datapath_tx_converter_converter_source_last; assign datapath_tx_converter_source_source_payload_data = datapath_tx_converter_converter_source_payload_data; assign datapath_tx_converter_converter_first = (datapath_tx_converter_converter_mux == 1'd0); assign datapath_tx_converter_converter_last = (datapath_tx_converter_converter_mux == 1'd1); assign datapath_tx_converter_converter_source_valid = datapath_tx_converter_converter_sink_valid; assign datapath_tx_converter_converter_source_first = (datapath_tx_converter_converter_sink_first & datapath_tx_converter_converter_first); assign datapath_tx_converter_converter_source_last = (datapath_tx_converter_converter_sink_last & datapath_tx_converter_converter_last); assign datapath_tx_converter_converter_sink_ready = (datapath_tx_converter_converter_last & datapath_tx_converter_converter_source_ready); always @(*) begin datapath_tx_converter_converter_source_payload_data <= 18'd0; case (datapath_tx_converter_converter_mux) 1'd0: begin datapath_tx_converter_converter_source_payload_data <= datapath_tx_converter_converter_sink_payload_data[17:0]; end default: begin datapath_tx_converter_converter_source_payload_data <= datapath_tx_converter_converter_sink_payload_data[35:18]; end endcase end assign datapath_tx_converter_converter_source_payload_valid_token_count = datapath_tx_converter_converter_last; assign datapath_rx_sr_charisk = {datapath_rx_sink_sink_payload_charisk, datapath_rx_last_charisk}; assign datapath_rx_sr_data = {datapath_rx_sink_sink_payload_data, datapath_rx_last_data}; assign datapath_rx_converter_sink_valid = datapath_rx_sink_sink_valid; always @(*) begin datapath_rx_converter_sink_payload_data <= 16'd0; datapath_rx_converter_sink_payload_charisk <= 2'd0; case (datapath_rx_byte_alignment) 1'd1: begin datapath_rx_converter_sink_payload_charisk <= datapath_rx_sr_charisk[3:2]; datapath_rx_converter_sink_payload_data <= datapath_rx_sr_data[31:16]; end 2'd2: begin datapath_rx_converter_sink_payload_charisk <= datapath_rx_sr_charisk[2:1]; datapath_rx_converter_sink_payload_data <= datapath_rx_sr_data[23:8]; end endcase end assign datapath_rx_sink_sink_ready = datapath_rx_converter_sink_ready; assign datapath_rx_converter_reset = (datapath_rx_converter_source_payload_charisk[3:2] != 1'd0); assign datapath_rx_fifo_sink_valid = datapath_rx_converter_source_valid; assign datapath_rx_converter_source_ready = datapath_rx_fifo_sink_ready; assign datapath_rx_fifo_sink_first = datapath_rx_converter_source_first; assign datapath_rx_fifo_sink_last = datapath_rx_converter_source_last; assign datapath_rx_fifo_sink_payload_data = datapath_rx_converter_source_payload_data; assign datapath_rx_fifo_sink_payload_charisk = datapath_rx_converter_source_payload_charisk; assign datapath_rx_source_source_valid = datapath_rx_fifo_source_valid; assign datapath_rx_fifo_source_ready = datapath_rx_source_source_ready; assign datapath_rx_source_source_first = datapath_rx_fifo_source_first; assign datapath_rx_source_source_last = datapath_rx_fifo_source_last; assign datapath_rx_source_source_payload_data = datapath_rx_fifo_source_payload_data; assign datapath_rx_source_source_payload_charisk = datapath_rx_fifo_source_payload_charisk; assign datapath_rx_converter_converter_sink_valid = datapath_rx_converter_sink_valid; assign datapath_rx_converter_converter_sink_first = datapath_rx_converter_sink_first; assign datapath_rx_converter_converter_sink_last = datapath_rx_converter_sink_last; assign datapath_rx_converter_sink_ready = datapath_rx_converter_converter_sink_ready; assign datapath_rx_converter_converter_sink_payload_data = {datapath_rx_converter_sink_payload_charisk, datapath_rx_converter_sink_payload_data}; assign datapath_rx_converter_source_valid = datapath_rx_converter_source_source_valid; assign datapath_rx_converter_source_first = datapath_rx_converter_source_source_first; assign datapath_rx_converter_source_last = datapath_rx_converter_source_source_last; assign datapath_rx_converter_source_source_ready = datapath_rx_converter_source_ready; always @(*) begin datapath_rx_converter_source_payload_data <= 32'd0; datapath_rx_converter_source_payload_data[15:0] <= datapath_rx_converter_source_source_payload_data[15:0]; datapath_rx_converter_source_payload_data[31:16] <= datapath_rx_converter_source_source_payload_data[33:18]; end always @(*) begin datapath_rx_converter_source_payload_charisk <= 4'd0; datapath_rx_converter_source_payload_charisk[1:0] <= datapath_rx_converter_source_source_payload_data[17:16]; datapath_rx_converter_source_payload_charisk[3:2] <= datapath_rx_converter_source_source_payload_data[35:34]; end assign datapath_rx_converter_source_source_valid = datapath_rx_converter_converter_source_valid; assign datapath_rx_converter_converter_source_ready = datapath_rx_converter_source_source_ready; assign datapath_rx_converter_source_source_first = datapath_rx_converter_converter_source_first; assign datapath_rx_converter_source_source_last = datapath_rx_converter_converter_source_last; assign datapath_rx_converter_source_source_payload_data = datapath_rx_converter_converter_source_payload_data; assign datapath_rx_converter_converter_sink_ready = ((~datapath_rx_converter_converter_strobe_all) | datapath_rx_converter_converter_source_ready); assign datapath_rx_converter_converter_source_valid = datapath_rx_converter_converter_strobe_all; assign datapath_rx_converter_converter_load_part = (datapath_rx_converter_converter_sink_valid & datapath_rx_converter_converter_sink_ready); assign datapath_rx_fifo_asyncfifo_din = {datapath_rx_fifo_fifo_in_last, datapath_rx_fifo_fifo_in_first, datapath_rx_fifo_fifo_in_payload_charisk, datapath_rx_fifo_fifo_in_payload_data}; assign {datapath_rx_fifo_fifo_out_last, datapath_rx_fifo_fifo_out_first, datapath_rx_fifo_fifo_out_payload_charisk, datapath_rx_fifo_fifo_out_payload_data} = datapath_rx_fifo_asyncfifo_dout; assign datapath_rx_fifo_sink_ready = datapath_rx_fifo_asyncfifo_writable; assign datapath_rx_fifo_asyncfifo_we = datapath_rx_fifo_sink_valid; assign datapath_rx_fifo_fifo_in_first = datapath_rx_fifo_sink_first; assign datapath_rx_fifo_fifo_in_last = datapath_rx_fifo_sink_last; assign datapath_rx_fifo_fifo_in_payload_data = datapath_rx_fifo_sink_payload_data; assign datapath_rx_fifo_fifo_in_payload_charisk = datapath_rx_fifo_sink_payload_charisk; assign datapath_rx_fifo_source_valid = datapath_rx_fifo_asyncfifo_readable; assign datapath_rx_fifo_source_first = datapath_rx_fifo_fifo_out_first; assign datapath_rx_fifo_source_last = datapath_rx_fifo_fifo_out_last; assign datapath_rx_fifo_source_payload_data = datapath_rx_fifo_fifo_out_payload_data; assign datapath_rx_fifo_source_payload_charisk = datapath_rx_fifo_fifo_out_payload_charisk; assign datapath_rx_fifo_asyncfifo_re = datapath_rx_fifo_source_ready; assign datapath_rx_fifo_graycounter0_ce = (datapath_rx_fifo_asyncfifo_writable & datapath_rx_fifo_asyncfifo_we); assign datapath_rx_fifo_graycounter1_ce = (datapath_rx_fifo_asyncfifo_readable & datapath_rx_fifo_asyncfifo_re); assign datapath_rx_fifo_asyncfifo_writable = (((datapath_rx_fifo_graycounter0_q[3] == datapath_rx_fifo_consume_wdomain[3]) | (datapath_rx_fifo_graycounter0_q[2] == datapath_rx_fifo_consume_wdomain[2])) | (datapath_rx_fifo_graycounter0_q[1:0] != datapath_rx_fifo_consume_wdomain[1:0])); assign datapath_rx_fifo_asyncfifo_readable = (datapath_rx_fifo_graycounter1_q != datapath_rx_fifo_produce_rdomain); assign datapath_rx_fifo_wrport_adr = datapath_rx_fifo_graycounter0_q_binary[2:0]; assign datapath_rx_fifo_wrport_dat_w = datapath_rx_fifo_asyncfifo_din; assign datapath_rx_fifo_wrport_we = datapath_rx_fifo_graycounter0_ce; assign datapath_rx_fifo_rdport_adr = datapath_rx_fifo_graycounter1_q_next_binary[2:0]; assign datapath_rx_fifo_asyncfifo_dout = datapath_rx_fifo_rdport_dat_r; always @(*) begin datapath_rx_fifo_graycounter0_q_next_binary <= 4'd0; if (datapath_rx_fifo_graycounter0_ce) begin datapath_rx_fifo_graycounter0_q_next_binary <= (datapath_rx_fifo_graycounter0_q_binary + 1'd1); end else begin datapath_rx_fifo_graycounter0_q_next_binary <= datapath_rx_fifo_graycounter0_q_binary; end end assign datapath_rx_fifo_graycounter0_q_next = (datapath_rx_fifo_graycounter0_q_next_binary ^ datapath_rx_fifo_graycounter0_q_next_binary[3:1]); always @(*) begin datapath_rx_fifo_graycounter1_q_next_binary <= 4'd0; if (datapath_rx_fifo_graycounter1_ce) begin datapath_rx_fifo_graycounter1_q_next_binary <= (datapath_rx_fifo_graycounter1_q_binary + 1'd1); end else begin datapath_rx_fifo_graycounter1_q_next_binary <= datapath_rx_fifo_graycounter1_q_binary; end end assign datapath_rx_fifo_graycounter1_q_next = (datapath_rx_fifo_graycounter1_q_next_binary ^ datapath_rx_fifo_graycounter1_q_next_binary[3:1]); always @(*) begin datapath_demux_endpoint0_source_first <= 1'd0; datapath_demux_endpoint0_source_last <= 1'd0; datapath_demux_endpoint0_source_payload_data <= 32'd0; datapath_demux_endpoint0_source_payload_charisk <= 4'd0; datapath_demux_endpoint1_source_valid <= 1'd0; datapath_demux_endpoint1_source_first <= 1'd0; datapath_demux_endpoint1_source_last <= 1'd0; datapath_demux_endpoint1_source_payload_data <= 32'd0; datapath_demux_sink_ready <= 1'd0; datapath_demux_endpoint1_source_payload_charisk <= 4'd0; datapath_demux_endpoint0_source_valid <= 1'd0; case (datapath_demux_sel) 1'd0: begin datapath_demux_endpoint0_source_valid <= datapath_demux_sink_valid; datapath_demux_sink_ready <= datapath_demux_endpoint0_source_ready; datapath_demux_endpoint0_source_first <= datapath_demux_sink_first; datapath_demux_endpoint0_source_last <= datapath_demux_sink_last; datapath_demux_endpoint0_source_payload_data <= datapath_demux_sink_payload_data; datapath_demux_endpoint0_source_payload_charisk <= datapath_demux_sink_payload_charisk; end 1'd1: begin datapath_demux_endpoint1_source_valid <= datapath_demux_sink_valid; datapath_demux_sink_ready <= datapath_demux_endpoint1_source_ready; datapath_demux_endpoint1_source_first <= datapath_demux_sink_first; datapath_demux_endpoint1_source_last <= datapath_demux_sink_last; datapath_demux_endpoint1_source_payload_data <= datapath_demux_sink_payload_data; datapath_demux_endpoint1_source_payload_charisk <= datapath_demux_sink_payload_charisk; end endcase end always @(*) begin datapath_align_timer_wait <= 1'd0; if (((datapath_align_timer_sink_valid & (datapath_align_timer_sink_payload_charisk == 1'd1)) & (datapath_align_timer_sink_payload_data == 31'd2068466364))) begin datapath_align_timer_wait <= 1'd0; end else begin datapath_align_timer_wait <= 1'd1; end end assign datapath_align_timer_done = (datapath_align_timer_count == 1'd0); assign link_litesatalinktx_from_rx_valid = link_litesatalinkrx_to_tx_valid; assign link_litesatalinkrx_to_tx_ready = link_litesatalinktx_from_rx_ready; assign link_litesatalinktx_from_rx_first = link_litesatalinkrx_to_tx_first; assign link_litesatalinktx_from_rx_last = link_litesatalinkrx_to_tx_last; assign link_litesatalinktx_from_rx_payload_idle = link_litesatalinkrx_to_tx_payload_idle; assign link_litesatalinktx_from_rx_payload_insert = link_litesatalinkrx_to_tx_payload_insert; assign link_litesatalinktx_from_rx_payload_primitive_valid = link_litesatalinkrx_to_tx_payload_primitive_valid; assign link_litesatalinktx_from_rx_payload_primitive = link_litesatalinkrx_to_tx_payload_primitive; assign link_litesatalinkrx_hold = (link_rx_buffer_level > 7'd64); always @(*) begin link_litesatalinktx_scrambler_source_ready <= 1'd0; link_litesatalinktx_source_source_valid <= 1'd0; link_litesatalinktx_source_source_payload_charisk <= 4'd0; link_litesatalinktx_source_source_payload_data <= 32'd0; if (link_litesatalinktx_from_rx_payload_insert) begin link_litesatalinktx_source_source_valid <= 1'd1; link_litesatalinktx_source_source_payload_data <= link_litesatalinktx_from_rx_payload_insert; link_litesatalinktx_source_source_payload_charisk <= 1'd1; end else begin if (link_litesatalinktx_insert) begin link_litesatalinktx_source_source_valid <= 1'd1; link_litesatalinktx_source_source_payload_data <= link_litesatalinktx_insert; link_litesatalinktx_source_source_payload_charisk <= 1'd1; end else begin if (link_litesatalinktx_copy) begin link_litesatalinktx_source_source_valid <= 1'd1; link_litesatalinktx_scrambler_source_ready <= link_litesatalinktx_source_source_ready; if (link_litesatalinktx_scrambler_source_valid) begin link_litesatalinktx_source_source_payload_data <= link_litesatalinktx_scrambler_source_payload_data; link_litesatalinktx_source_source_payload_charisk <= 1'd0; end else begin link_litesatalinktx_source_source_payload_data <= 32'd3587549820; link_litesatalinktx_source_source_payload_charisk <= 1'd1; end end end end end assign link_tx_sink_valid = link_litesatalinktx_source_source_valid; assign link_litesatalinktx_source_source_ready = link_tx_sink_ready; assign link_tx_sink_first = link_litesatalinktx_source_source_first; assign link_tx_sink_last = link_litesatalinktx_source_source_last; assign link_tx_sink_payload_data = link_litesatalinktx_source_source_payload_data; assign link_tx_sink_payload_charisk = link_litesatalinktx_source_source_payload_charisk; assign link_litesatalinktx_crc_busy = (~link_litesatalinktx_crc_is_ongoing); assign link_litesatalinktx_crc_data1 = link_litesatalinktx_crc_data0; assign link_litesatalinktx_crc_last = link_litesatalinktx_crc_reg_i; assign link_litesatalinktx_crc_value = link_litesatalinktx_crc_reg_i; assign link_litesatalinktx_crc_error = (link_litesatalinktx_crc_next != 1'd0); assign link_litesatalinktx_crc_new = (link_litesatalinktx_crc_last ^ link_litesatalinktx_crc_data1); always @(*) begin link_litesatalinktx_crc_next <= 32'd0; link_litesatalinktx_crc_next[0] <= ((((((((((((link_litesatalinktx_crc_new[0] ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); link_litesatalinktx_crc_next[1] <= ((((((((((((link_litesatalinktx_crc_new[1] ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[12]); link_litesatalinktx_crc_next[2] <= (((((((((((((((link_litesatalinktx_crc_new[2] ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]); link_litesatalinktx_crc_next[3] <= ((((((((((((((link_litesatalinktx_crc_new[3] ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[17]); link_litesatalinktx_crc_next[4] <= ((((((((((((((((link_litesatalinktx_crc_new[4] ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); link_litesatalinktx_crc_next[5] <= ((((((((((((((link_litesatalinktx_crc_new[5] ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[6]); link_litesatalinktx_crc_next[6] <= ((((((((((((((link_litesatalinktx_crc_new[6] ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[7]); link_litesatalinktx_crc_next[7] <= (((((((((((((((link_litesatalinktx_crc_new[7] ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[16]); link_litesatalinktx_crc_next[8] <= ((((((((((((link_litesatalinktx_crc_new[8] ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); link_litesatalinktx_crc_next[9] <= (((((((((((link_litesatalinktx_crc_new[9] ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[12]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[13]); link_litesatalinktx_crc_next[10] <= ((((((((((((link_litesatalinktx_crc_new[5] ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]); link_litesatalinktx_crc_next[11] <= ((((((((((((((((link_litesatalinktx_crc_new[4] ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); link_litesatalinktx_crc_next[12] <= ((((((((((((((((link_litesatalinktx_crc_new[5] ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); link_litesatalinktx_crc_next[13] <= (((((((((((((((link_litesatalinktx_crc_new[6] ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[13]); link_litesatalinktx_crc_next[14] <= ((((((((((((((link_litesatalinktx_crc_new[7] ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[14]); link_litesatalinktx_crc_next[15] <= ((((((((((((((link_litesatalinktx_crc_new[8] ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[12]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[15]); link_litesatalinktx_crc_next[16] <= (((((((((((((link_litesatalinktx_crc_new[19] ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[12]); link_litesatalinktx_crc_next[17] <= (((((((((((((link_litesatalinktx_crc_new[20] ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[13]); link_litesatalinktx_crc_next[18] <= ((((((((((((link_litesatalinktx_crc_new[21] ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[14]); link_litesatalinktx_crc_next[19] <= (((((((((((link_litesatalinktx_crc_new[22] ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[15]); link_litesatalinktx_crc_next[20] <= (((((((((((link_litesatalinktx_crc_new[23] ^ link_litesatalinktx_crc_new[12]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[16]); link_litesatalinktx_crc_next[21] <= (((((((((((link_litesatalinktx_crc_new[24] ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[17]); link_litesatalinktx_crc_next[22] <= (((((((((((((link_litesatalinktx_crc_new[14] ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[12]); link_litesatalinktx_crc_next[23] <= (((((((((((((link_litesatalinktx_crc_new[15] ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[17]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[16]) ^ link_litesatalinktx_crc_new[31]); link_litesatalinktx_crc_next[24] <= ((((((((((((link_litesatalinktx_crc_new[16] ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[18]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[17]); link_litesatalinktx_crc_next[25] <= ((((((((((((link_litesatalinktx_crc_new[17] ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[18]); link_litesatalinktx_crc_next[26] <= ((((((((((((((link_litesatalinktx_crc_new[18] ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[19]) ^ link_litesatalinktx_crc_new[0]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[10]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[31]); link_litesatalinktx_crc_next[27] <= (((((((((((((link_litesatalinktx_crc_new[19] ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[20]) ^ link_litesatalinktx_crc_new[1]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[11]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[7]); link_litesatalinktx_crc_next[28] <= (((((((((((((link_litesatalinktx_crc_new[20] ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[21]) ^ link_litesatalinktx_crc_new[2]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[12]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[8]); link_litesatalinktx_crc_next[29] <= (((((((((((((link_litesatalinktx_crc_new[21] ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[6]) ^ link_litesatalinktx_crc_new[22]) ^ link_litesatalinktx_crc_new[3]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[13]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[9]); link_litesatalinktx_crc_next[30] <= ((((((((((((link_litesatalinktx_crc_new[22] ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[26]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[7]) ^ link_litesatalinktx_crc_new[23]) ^ link_litesatalinktx_crc_new[4]) ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[14]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[10]); link_litesatalinktx_crc_next[31] <= ((((((((((((link_litesatalinktx_crc_new[23] ^ link_litesatalinktx_crc_new[28]) ^ link_litesatalinktx_crc_new[27]) ^ link_litesatalinktx_crc_new[9]) ^ link_litesatalinktx_crc_new[25]) ^ link_litesatalinktx_crc_new[8]) ^ link_litesatalinktx_crc_new[24]) ^ link_litesatalinktx_crc_new[5]) ^ link_litesatalinktx_crc_new[29]) ^ link_litesatalinktx_crc_new[15]) ^ link_litesatalinktx_crc_new[31]) ^ link_litesatalinktx_crc_new[30]) ^ link_litesatalinktx_crc_new[11]); end always @(*) begin link_litesatalinktx_crc_data0 <= 32'd0; link_litesatalinktx_crc_sink_ready <= 1'd0; link_litesatalinktx_crc_is_ongoing <= 1'd0; subfragments_litesatalinktx_litesatacrcinserter_next_state <= 2'd0; link_litesatalinktx_crc_source_valid <= 1'd0; link_litesatalinktx_crc_source_first <= 1'd0; link_litesatalinktx_crc_source_last <= 1'd0; link_litesatalinktx_crc_source_payload_data <= 32'd0; link_litesatalinktx_crc_ce <= 1'd0; link_litesatalinktx_crc_source_payload_error <= 1'd0; link_litesatalinktx_crc_reset <= 1'd0; subfragments_litesatalinktx_litesatacrcinserter_next_state <= subfragments_litesatalinktx_litesatacrcinserter_state; case (subfragments_litesatalinktx_litesatacrcinserter_state) 1'd1: begin link_litesatalinktx_crc_ce <= (link_litesatalinktx_crc_sink_valid & link_litesatalinktx_crc_source_ready); link_litesatalinktx_crc_data0 <= link_litesatalinktx_crc_sink_payload_data; link_litesatalinktx_crc_source_valid <= link_litesatalinktx_crc_sink_valid; link_litesatalinktx_crc_sink_ready <= link_litesatalinktx_crc_source_ready; link_litesatalinktx_crc_source_first <= link_litesatalinktx_crc_sink_first; link_litesatalinktx_crc_source_last <= link_litesatalinktx_crc_sink_last; link_litesatalinktx_crc_source_payload_data <= link_litesatalinktx_crc_sink_payload_data; link_litesatalinktx_crc_source_payload_error <= link_litesatalinktx_crc_sink_payload_error; link_litesatalinktx_crc_source_last <= 1'd0; if (((link_litesatalinktx_crc_sink_valid & link_litesatalinktx_crc_sink_last) & link_litesatalinktx_crc_source_ready)) begin subfragments_litesatalinktx_litesatacrcinserter_next_state <= 2'd2; end end 2'd2: begin link_litesatalinktx_crc_source_valid <= 1'd1; link_litesatalinktx_crc_source_last <= 1'd1; link_litesatalinktx_crc_source_payload_data <= link_litesatalinktx_crc_value; if (link_litesatalinktx_crc_source_ready) begin subfragments_litesatalinktx_litesatacrcinserter_next_state <= 1'd0; end end default: begin link_litesatalinktx_crc_reset <= 1'd1; link_litesatalinktx_crc_sink_ready <= 1'd1; if (link_litesatalinktx_crc_sink_valid) begin link_litesatalinktx_crc_sink_ready <= 1'd0; subfragments_litesatalinktx_litesatacrcinserter_next_state <= 1'd1; end link_litesatalinktx_crc_is_ongoing <= 1'd1; end endcase end assign link_litesatalinktx_scrambler_ce = (link_litesatalinktx_scrambler_sink_valid & link_litesatalinktx_scrambler_sink_ready); assign link_litesatalinktx_scrambler_source_valid = link_litesatalinktx_scrambler_sink_valid; assign link_litesatalinktx_scrambler_sink_ready = link_litesatalinktx_scrambler_source_ready; assign link_litesatalinktx_scrambler_source_first = link_litesatalinktx_scrambler_sink_first; assign link_litesatalinktx_scrambler_source_last = link_litesatalinktx_scrambler_sink_last; assign link_litesatalinktx_scrambler_source_payload_error = link_litesatalinktx_scrambler_sink_payload_error; always @(*) begin link_litesatalinktx_scrambler_source_payload_data <= 32'd0; link_litesatalinktx_scrambler_source_payload_data <= link_litesatalinktx_scrambler_sink_payload_data; link_litesatalinktx_scrambler_source_payload_data <= (link_litesatalinktx_scrambler_sink_payload_data ^ link_litesatalinktx_scrambler_value); end always @(*) begin link_litesatalinktx_scrambler_next_value <= 32'd0; link_litesatalinktx_scrambler_next_value[0] <= (((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[1] <= ((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[2] <= (((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[3] <= (((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); link_litesatalinktx_scrambler_next_value[4] <= ((((((link_litesatalinktx_scrambler_context[13] ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[5] <= ((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[1]); link_litesatalinktx_scrambler_next_value[6] <= ((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]); link_litesatalinktx_scrambler_next_value[7] <= (((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[8] <= ((((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[9] <= (((((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[10] <= (((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); link_litesatalinktx_scrambler_next_value[11] <= ((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[12] <= (((((((link_litesatalinktx_scrambler_context[13] ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[13] <= (((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); link_litesatalinktx_scrambler_next_value[14] <= (((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]); link_litesatalinktx_scrambler_next_value[15] <= ((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[16] <= (((link_litesatalinktx_scrambler_context[11] ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[17] <= (((link_litesatalinktx_scrambler_context[12] ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); link_litesatalinktx_scrambler_next_value[18] <= (((link_litesatalinktx_scrambler_context[13] ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]); link_litesatalinktx_scrambler_next_value[19] <= (((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[3]); link_litesatalinktx_scrambler_next_value[20] <= (((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]); link_litesatalinktx_scrambler_next_value[21] <= ((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[22] <= (((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[23] <= ((((((((link_litesatalinktx_scrambler_context[13] ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[24] <= ((((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); link_litesatalinktx_scrambler_next_value[25] <= ((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]); link_litesatalinktx_scrambler_next_value[26] <= (((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[27] <= ((((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[28] <= (((((((((link_litesatalinktx_scrambler_context[14] ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[4]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[29] <= (((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[13]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[8]) ^ link_litesatalinktx_scrambler_context[5]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[1]); link_litesatalinktx_scrambler_next_value[30] <= ((((((((link_litesatalinktx_scrambler_context[15] ^ link_litesatalinktx_scrambler_context[14]) ^ link_litesatalinktx_scrambler_context[12]) ^ link_litesatalinktx_scrambler_context[11]) ^ link_litesatalinktx_scrambler_context[9]) ^ link_litesatalinktx_scrambler_context[6]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[2]) ^ link_litesatalinktx_scrambler_context[0]); link_litesatalinktx_scrambler_next_value[31] <= (((((link_litesatalinktx_scrambler_context[12] ^ link_litesatalinktx_scrambler_context[10]) ^ link_litesatalinktx_scrambler_context[7]) ^ link_litesatalinktx_scrambler_context[3]) ^ link_litesatalinktx_scrambler_context[1]) ^ link_litesatalinktx_scrambler_context[0]); end assign link_litesatalinktx_scrambler_value = link_litesatalinktx_scrambler_next_value; assign link_litesatalinktx_crc_sink_valid = link_litesatalinktx_sink_sink_valid; assign link_litesatalinktx_sink_sink_ready = link_litesatalinktx_crc_sink_ready; assign link_litesatalinktx_crc_sink_first = link_litesatalinktx_sink_sink_first; assign link_litesatalinktx_crc_sink_last = link_litesatalinktx_sink_sink_last; assign link_litesatalinktx_crc_sink_payload_data = link_litesatalinktx_sink_sink_payload_data; assign link_litesatalinktx_crc_sink_payload_error = link_litesatalinktx_sink_sink_payload_error; assign link_litesatalinktx_scrambler_sink_valid = link_litesatalinktx_crc_source_valid; assign link_litesatalinktx_crc_source_ready = link_litesatalinktx_scrambler_sink_ready; assign link_litesatalinktx_scrambler_sink_first = link_litesatalinktx_crc_source_first; assign link_litesatalinktx_scrambler_sink_last = link_litesatalinktx_crc_source_last; assign link_litesatalinktx_scrambler_sink_payload_data = link_litesatalinktx_crc_source_payload_data; assign link_litesatalinktx_scrambler_sink_payload_error = link_litesatalinktx_crc_source_payload_error; always @(*) begin link_litesatalinktx_insert <= 32'd0; link_litesatalinktx_copy <= 1'd0; link_litesatalinktx_fsm_is_ongoing0 <= 1'd0; link_litesatalinktx_fsm_is_ongoing1 <= 1'd0; subfragments_litesatalinktx_fsm_next_state <= 3'd0; link_litesatalinktx_scrambler_reset <= 1'd0; subfragments_litesatalinktx_fsm_next_state <= subfragments_litesatalinktx_fsm_state; case (subfragments_litesatalinktx_fsm_state) 1'd1: begin link_litesatalinktx_insert <= 31'd1465365884; if ((~link_litesatalinktx_from_rx_payload_idle)) begin subfragments_litesatalinktx_fsm_next_state <= 1'd0; end else begin if ((link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive == 31'd1246401916))) begin subfragments_litesatalinktx_fsm_next_state <= 2'd2; end end link_litesatalinktx_fsm_is_ongoing1 <= 1'd1; end 2'd2: begin link_litesatalinktx_insert <= 30'd926397820; if (link_litesatalinktx_source_source_ready) begin subfragments_litesatalinktx_fsm_next_state <= 2'd3; end end 2'd3: begin link_litesatalinktx_copy <= 1'd1; if (((link_litesatalinktx_scrambler_source_valid & link_litesatalinktx_scrambler_source_last) & link_litesatalinktx_scrambler_source_ready)) begin subfragments_litesatalinktx_fsm_next_state <= 3'd5; end else begin if ((link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive == 32'd3587549820))) begin subfragments_litesatalinktx_fsm_next_state <= 3'd4; end end end 3'd4: begin link_litesatalinktx_insert <= 32'd2509613692; if ((link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive != 32'd3587549820))) begin subfragments_litesatalinktx_fsm_next_state <= 2'd3; end else begin if (link_litesatalinktx_error) begin subfragments_litesatalinktx_fsm_next_state <= 1'd0; end end end 3'd5: begin link_litesatalinktx_insert <= 32'd3587552636; if (link_litesatalinktx_source_source_ready) begin subfragments_litesatalinktx_fsm_next_state <= 3'd6; end end 3'd6: begin link_litesatalinktx_insert <= 31'd1482208636; if (link_litesatalinktx_from_rx_payload_primitive_valid) begin if ((link_litesatalinktx_from_rx_payload_primitive == 30'd892712316)) begin subfragments_litesatalinktx_fsm_next_state <= 1'd0; end else begin if ((link_litesatalinktx_from_rx_payload_primitive == 31'd1448523132)) begin subfragments_litesatalinktx_fsm_next_state <= 1'd0; end end end else begin if (link_litesatalinktx_error) begin subfragments_litesatalinktx_fsm_next_state <= 1'd0; end end end default: begin link_litesatalinktx_scrambler_reset <= 1'd1; if (link_litesatalinktx_from_rx_payload_idle) begin link_litesatalinktx_insert <= 32'd3048576380; if (link_litesatalinktx_scrambler_source_valid) begin if ((link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive == 32'd3048576380))) begin subfragments_litesatalinktx_fsm_next_state <= 1'd1; end end end link_litesatalinktx_fsm_is_ongoing0 <= 1'd1; end endcase end assign link_tx_sink_ready = ((~link_tx_source_valid) | link_tx_source_ready); assign link_tx_align_send = (link_tx_align_cnt < 2'd2); always @(*) begin link_tx_align_sink_ready <= 1'd0; link_tx_align_source_valid <= 1'd0; link_tx_align_source_payload_charisk <= 4'd0; link_tx_align_source_payload_data <= 32'd0; if (link_tx_align_send) begin link_tx_align_source_valid <= 1'd1; link_tx_align_source_payload_charisk <= 1'd1; link_tx_align_source_payload_data <= 31'd2068466364; link_tx_align_sink_ready <= 1'd0; end else begin link_tx_align_source_valid <= link_tx_align_sink_valid; link_tx_align_source_payload_data <= link_tx_align_sink_payload_data; link_tx_align_source_payload_charisk <= link_tx_align_sink_payload_charisk; link_tx_align_sink_ready <= link_tx_align_source_ready; end end assign link_tx_align_sink_valid = link_tx_source_valid; assign link_tx_source_ready = link_tx_align_sink_ready; assign link_tx_align_sink_first = link_tx_source_first; assign link_tx_align_sink_last = link_tx_source_last; assign link_tx_align_sink_payload_data = link_tx_source_payload_data; assign link_tx_align_sink_payload_charisk = link_tx_source_payload_charisk; assign datapath_sink_sink_valid = link_tx_align_source_valid; assign link_tx_align_source_ready = datapath_sink_sink_ready; assign datapath_sink_sink_first = link_tx_align_source_first; assign datapath_sink_sink_last = link_tx_align_source_last; assign datapath_sink_sink_payload_data = link_tx_align_source_payload_data; assign datapath_sink_sink_payload_charisk = link_tx_align_source_payload_charisk; always @(*) begin link_rx_align_source_valid <= 1'd0; link_rx_align_source_first <= 1'd0; link_rx_align_source_last <= 1'd0; link_rx_align_sink_ready <= 1'd0; link_rx_align_source_payload_data <= 32'd0; link_rx_align_source_payload_charisk <= 4'd0; if (((link_rx_align_sink_valid & (link_rx_align_sink_payload_charisk == 1'd1)) & (link_rx_align_sink_payload_data == 31'd2068466364))) begin link_rx_align_sink_ready <= 1'd1; end else begin link_rx_align_source_valid <= link_rx_align_sink_valid; link_rx_align_sink_ready <= link_rx_align_source_ready; link_rx_align_source_first <= link_rx_align_sink_first; link_rx_align_source_last <= link_rx_align_sink_last; link_rx_align_source_payload_data <= link_rx_align_sink_payload_data; link_rx_align_source_payload_charisk <= link_rx_align_sink_payload_charisk; end end assign link_rx_cont_is_data = (link_rx_cont_sink_payload_charisk == 1'd0); assign link_rx_cont_is_cont = ((~link_rx_cont_is_data) & (link_rx_cont_sink_payload_data == 32'd2576984700)); assign link_rx_cont_cont_ongoing = (link_rx_cont_is_cont | (link_rx_cont_in_cont & link_rx_cont_is_data)); assign link_rx_cont_source_valid = link_rx_cont_sink_valid; assign link_rx_cont_sink_ready = link_rx_cont_source_ready; assign link_rx_cont_source_first = link_rx_cont_sink_first; assign link_rx_cont_source_last = link_rx_cont_sink_last; always @(*) begin link_rx_cont_source_payload_charisk <= 4'd0; link_rx_cont_source_payload_data <= 32'd0; link_rx_cont_source_payload_data <= link_rx_cont_sink_payload_data; link_rx_cont_source_payload_charisk <= link_rx_cont_sink_payload_charisk; if (link_rx_cont_cont_ongoing) begin link_rx_cont_source_payload_charisk <= 1'd1; link_rx_cont_source_payload_data <= link_rx_cont_last_primitive; end end assign link_litesatalinkrx_sink_sink_ready = 1'd1; always @(*) begin link_litesatalinkrx_data_valid <= 1'd0; link_litesatalinkrx_primitive_valid <= 1'd0; if (link_litesatalinkrx_sink_sink_valid) begin link_litesatalinkrx_data_valid <= (link_litesatalinkrx_sink_sink_payload_charisk == 1'd0); link_litesatalinkrx_primitive_valid <= (link_litesatalinkrx_sink_sink_payload_charisk == 1'd1); end end assign link_litesatalinkrx_primitive = link_litesatalinkrx_sink_sink_payload_data; assign link_litesatalinkrx_to_tx_payload_idle = link_litesatalinkrx_fsm_is_ongoing; assign link_litesatalinkrx_to_tx_payload_insert = link_litesatalinkrx_insert; assign link_litesatalinkrx_to_tx_payload_primitive_valid = link_litesatalinkrx_primitive_valid; assign link_litesatalinkrx_to_tx_payload_primitive = link_litesatalinkrx_primitive; assign link_litesatalinkrx_sink_sink_valid = link_rx_source_valid; assign link_rx_source_ready = link_litesatalinkrx_sink_sink_ready; assign link_litesatalinkrx_sink_sink_first = link_rx_source_first; assign link_litesatalinkrx_sink_sink_last = link_rx_source_last; assign link_litesatalinkrx_sink_sink_payload_data = link_rx_source_payload_data; assign link_litesatalinkrx_sink_sink_payload_charisk = link_rx_source_payload_charisk; assign link_litesatalinkrx_descrambler_ce = (link_litesatalinkrx_descrambler_sink_valid & link_litesatalinkrx_descrambler_sink_ready); assign link_litesatalinkrx_descrambler_source_valid = link_litesatalinkrx_descrambler_sink_valid; assign link_litesatalinkrx_descrambler_sink_ready = link_litesatalinkrx_descrambler_source_ready; assign link_litesatalinkrx_descrambler_source_first = link_litesatalinkrx_descrambler_sink_first; assign link_litesatalinkrx_descrambler_source_last = link_litesatalinkrx_descrambler_sink_last; assign link_litesatalinkrx_descrambler_source_payload_error = link_litesatalinkrx_descrambler_sink_payload_error; always @(*) begin link_litesatalinkrx_descrambler_source_payload_data <= 32'd0; link_litesatalinkrx_descrambler_source_payload_data <= link_litesatalinkrx_descrambler_sink_payload_data; link_litesatalinkrx_descrambler_source_payload_data <= (link_litesatalinkrx_descrambler_sink_payload_data ^ link_litesatalinkrx_descrambler_value); end always @(*) begin link_litesatalinkrx_descrambler_next_value <= 32'd0; link_litesatalinkrx_descrambler_next_value[0] <= (((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[1] <= ((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[2] <= (((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[3] <= (((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); link_litesatalinkrx_descrambler_next_value[4] <= ((((((link_litesatalinkrx_descrambler_context[13] ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[5] <= ((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[1]); link_litesatalinkrx_descrambler_next_value[6] <= ((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]); link_litesatalinkrx_descrambler_next_value[7] <= (((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[8] <= ((((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[9] <= (((((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[10] <= (((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); link_litesatalinkrx_descrambler_next_value[11] <= ((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[12] <= (((((((link_litesatalinkrx_descrambler_context[13] ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[13] <= (((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); link_litesatalinkrx_descrambler_next_value[14] <= (((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]); link_litesatalinkrx_descrambler_next_value[15] <= ((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[16] <= (((link_litesatalinkrx_descrambler_context[11] ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[17] <= (((link_litesatalinkrx_descrambler_context[12] ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); link_litesatalinkrx_descrambler_next_value[18] <= (((link_litesatalinkrx_descrambler_context[13] ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]); link_litesatalinkrx_descrambler_next_value[19] <= (((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[3]); link_litesatalinkrx_descrambler_next_value[20] <= (((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]); link_litesatalinkrx_descrambler_next_value[21] <= ((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[22] <= (((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[23] <= ((((((((link_litesatalinkrx_descrambler_context[13] ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[24] <= ((((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); link_litesatalinkrx_descrambler_next_value[25] <= ((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]); link_litesatalinkrx_descrambler_next_value[26] <= (((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[27] <= ((((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[28] <= (((((((((link_litesatalinkrx_descrambler_context[14] ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[4]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[29] <= (((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[13]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[8]) ^ link_litesatalinkrx_descrambler_context[5]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[1]); link_litesatalinkrx_descrambler_next_value[30] <= ((((((((link_litesatalinkrx_descrambler_context[15] ^ link_litesatalinkrx_descrambler_context[14]) ^ link_litesatalinkrx_descrambler_context[12]) ^ link_litesatalinkrx_descrambler_context[11]) ^ link_litesatalinkrx_descrambler_context[9]) ^ link_litesatalinkrx_descrambler_context[6]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[2]) ^ link_litesatalinkrx_descrambler_context[0]); link_litesatalinkrx_descrambler_next_value[31] <= (((((link_litesatalinkrx_descrambler_context[12] ^ link_litesatalinkrx_descrambler_context[10]) ^ link_litesatalinkrx_descrambler_context[7]) ^ link_litesatalinkrx_descrambler_context[3]) ^ link_litesatalinkrx_descrambler_context[1]) ^ link_litesatalinkrx_descrambler_context[0]); end assign link_litesatalinkrx_descrambler_value = link_litesatalinkrx_descrambler_next_value; assign link_litesatalinkrx_crc_fifo_full = (link_litesatalinkrx_crc_syncfifo_level == 1'd1); assign link_litesatalinkrx_crc_fifo_in = (link_litesatalinkrx_crc_sink_sink_valid & ((~link_litesatalinkrx_crc_fifo_full) | link_litesatalinkrx_crc_fifo_out)); assign link_litesatalinkrx_crc_fifo_out = (link_litesatalinkrx_crc_source_source_valid & link_litesatalinkrx_crc_source_source_ready); assign link_litesatalinkrx_crc_syncfifo_sink_first = link_litesatalinkrx_crc_sink_sink_first; assign link_litesatalinkrx_crc_syncfifo_sink_last = link_litesatalinkrx_crc_sink_sink_last; assign link_litesatalinkrx_crc_syncfifo_sink_payload_data = link_litesatalinkrx_crc_sink_sink_payload_data; assign link_litesatalinkrx_crc_syncfifo_sink_payload_error = link_litesatalinkrx_crc_sink_sink_payload_error; always @(*) begin link_litesatalinkrx_crc_syncfifo_sink_valid <= 1'd0; link_litesatalinkrx_crc_syncfifo_sink_valid <= link_litesatalinkrx_crc_sink_sink_valid; link_litesatalinkrx_crc_syncfifo_sink_valid <= link_litesatalinkrx_crc_fifo_in; end always @(*) begin link_litesatalinkrx_crc_sink_sink_ready <= 1'd0; link_litesatalinkrx_crc_sink_sink_ready <= link_litesatalinkrx_crc_syncfifo_sink_ready; link_litesatalinkrx_crc_sink_sink_ready <= link_litesatalinkrx_crc_fifo_in; end assign link_litesatalinkrx_crc_source_source_valid = (link_litesatalinkrx_crc_sink_sink_valid & link_litesatalinkrx_crc_fifo_full); assign link_litesatalinkrx_crc_source_source_last = link_litesatalinkrx_crc_sink_sink_last; assign link_litesatalinkrx_crc_syncfifo_source_ready = link_litesatalinkrx_crc_fifo_out; assign link_litesatalinkrx_crc_source_source_payload_data = link_litesatalinkrx_crc_syncfifo_source_payload_data; always @(*) begin link_litesatalinkrx_crc_source_source_payload_error <= 1'd0; link_litesatalinkrx_crc_source_source_payload_error <= link_litesatalinkrx_crc_syncfifo_source_payload_error; link_litesatalinkrx_crc_source_source_payload_error <= (link_litesatalinkrx_crc_sink_sink_payload_error | (link_litesatalinkrx_crc_crc_error & link_litesatalinkrx_crc_source_source_last)); end assign link_litesatalinkrx_crc_busy = (~link_litesatalinkrx_crc_is_ongoing); assign link_litesatalinkrx_crc_crc_data1 = link_litesatalinkrx_crc_crc_data0; assign link_litesatalinkrx_crc_crc_last = link_litesatalinkrx_crc_crc_reg_i; assign link_litesatalinkrx_crc_crc_value = link_litesatalinkrx_crc_crc_reg_i; assign link_litesatalinkrx_crc_crc_error = (link_litesatalinkrx_crc_crc_next != 1'd0); assign link_litesatalinkrx_crc_crc_new = (link_litesatalinkrx_crc_crc_last ^ link_litesatalinkrx_crc_crc_data1); always @(*) begin link_litesatalinkrx_crc_crc_next <= 32'd0; link_litesatalinkrx_crc_crc_next[0] <= ((((((((((((link_litesatalinkrx_crc_crc_new[0] ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); link_litesatalinkrx_crc_crc_next[1] <= ((((((((((((link_litesatalinkrx_crc_crc_new[1] ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[12]); link_litesatalinkrx_crc_crc_next[2] <= (((((((((((((((link_litesatalinkrx_crc_crc_new[2] ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]); link_litesatalinkrx_crc_crc_next[3] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[3] ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[17]); link_litesatalinkrx_crc_crc_next[4] <= ((((((((((((((((link_litesatalinkrx_crc_crc_new[4] ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); link_litesatalinkrx_crc_crc_next[5] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[5] ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[6]); link_litesatalinkrx_crc_crc_next[6] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[6] ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[7]); link_litesatalinkrx_crc_crc_next[7] <= (((((((((((((((link_litesatalinkrx_crc_crc_new[7] ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[16]); link_litesatalinkrx_crc_crc_next[8] <= ((((((((((((link_litesatalinkrx_crc_crc_new[8] ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); link_litesatalinkrx_crc_crc_next[9] <= (((((((((((link_litesatalinkrx_crc_crc_new[9] ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[12]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[13]); link_litesatalinkrx_crc_crc_next[10] <= ((((((((((((link_litesatalinkrx_crc_crc_new[5] ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]); link_litesatalinkrx_crc_crc_next[11] <= ((((((((((((((((link_litesatalinkrx_crc_crc_new[4] ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); link_litesatalinkrx_crc_crc_next[12] <= ((((((((((((((((link_litesatalinkrx_crc_crc_new[5] ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); link_litesatalinkrx_crc_crc_next[13] <= (((((((((((((((link_litesatalinkrx_crc_crc_new[6] ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[13]); link_litesatalinkrx_crc_crc_next[14] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[7] ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[14]); link_litesatalinkrx_crc_crc_next[15] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[8] ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[12]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[15]); link_litesatalinkrx_crc_crc_next[16] <= (((((((((((((link_litesatalinkrx_crc_crc_new[19] ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[12]); link_litesatalinkrx_crc_crc_next[17] <= (((((((((((((link_litesatalinkrx_crc_crc_new[20] ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[13]); link_litesatalinkrx_crc_crc_next[18] <= ((((((((((((link_litesatalinkrx_crc_crc_new[21] ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[14]); link_litesatalinkrx_crc_crc_next[19] <= (((((((((((link_litesatalinkrx_crc_crc_new[22] ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[15]); link_litesatalinkrx_crc_crc_next[20] <= (((((((((((link_litesatalinkrx_crc_crc_new[23] ^ link_litesatalinkrx_crc_crc_new[12]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[16]); link_litesatalinkrx_crc_crc_next[21] <= (((((((((((link_litesatalinkrx_crc_crc_new[24] ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[17]); link_litesatalinkrx_crc_crc_next[22] <= (((((((((((((link_litesatalinkrx_crc_crc_new[14] ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[12]); link_litesatalinkrx_crc_crc_next[23] <= (((((((((((((link_litesatalinkrx_crc_crc_new[15] ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[17]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[16]) ^ link_litesatalinkrx_crc_crc_new[31]); link_litesatalinkrx_crc_crc_next[24] <= ((((((((((((link_litesatalinkrx_crc_crc_new[16] ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[18]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[17]); link_litesatalinkrx_crc_crc_next[25] <= ((((((((((((link_litesatalinkrx_crc_crc_new[17] ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[18]); link_litesatalinkrx_crc_crc_next[26] <= ((((((((((((((link_litesatalinkrx_crc_crc_new[18] ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[19]) ^ link_litesatalinkrx_crc_crc_new[0]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[10]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[31]); link_litesatalinkrx_crc_crc_next[27] <= (((((((((((((link_litesatalinkrx_crc_crc_new[19] ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[20]) ^ link_litesatalinkrx_crc_crc_new[1]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[11]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[7]); link_litesatalinkrx_crc_crc_next[28] <= (((((((((((((link_litesatalinkrx_crc_crc_new[20] ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[21]) ^ link_litesatalinkrx_crc_crc_new[2]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[12]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[8]); link_litesatalinkrx_crc_crc_next[29] <= (((((((((((((link_litesatalinkrx_crc_crc_new[21] ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[6]) ^ link_litesatalinkrx_crc_crc_new[22]) ^ link_litesatalinkrx_crc_crc_new[3]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[13]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[9]); link_litesatalinkrx_crc_crc_next[30] <= ((((((((((((link_litesatalinkrx_crc_crc_new[22] ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[26]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[7]) ^ link_litesatalinkrx_crc_crc_new[23]) ^ link_litesatalinkrx_crc_crc_new[4]) ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[14]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[10]); link_litesatalinkrx_crc_crc_next[31] <= ((((((((((((link_litesatalinkrx_crc_crc_new[23] ^ link_litesatalinkrx_crc_crc_new[28]) ^ link_litesatalinkrx_crc_crc_new[27]) ^ link_litesatalinkrx_crc_crc_new[9]) ^ link_litesatalinkrx_crc_crc_new[25]) ^ link_litesatalinkrx_crc_crc_new[8]) ^ link_litesatalinkrx_crc_crc_new[24]) ^ link_litesatalinkrx_crc_crc_new[5]) ^ link_litesatalinkrx_crc_crc_new[29]) ^ link_litesatalinkrx_crc_crc_new[15]) ^ link_litesatalinkrx_crc_crc_new[31]) ^ link_litesatalinkrx_crc_crc_new[30]) ^ link_litesatalinkrx_crc_crc_new[11]); end assign link_litesatalinkrx_crc_syncfifo_syncfifo_din = {link_litesatalinkrx_crc_syncfifo_fifo_in_last, link_litesatalinkrx_crc_syncfifo_fifo_in_first, link_litesatalinkrx_crc_syncfifo_fifo_in_payload_error, link_litesatalinkrx_crc_syncfifo_fifo_in_payload_data}; assign {link_litesatalinkrx_crc_syncfifo_fifo_out_last, link_litesatalinkrx_crc_syncfifo_fifo_out_first, link_litesatalinkrx_crc_syncfifo_fifo_out_payload_error, link_litesatalinkrx_crc_syncfifo_fifo_out_payload_data} = link_litesatalinkrx_crc_syncfifo_syncfifo_dout; assign link_litesatalinkrx_crc_syncfifo_sink_ready = link_litesatalinkrx_crc_syncfifo_syncfifo_writable; assign link_litesatalinkrx_crc_syncfifo_syncfifo_we = link_litesatalinkrx_crc_syncfifo_sink_valid; assign link_litesatalinkrx_crc_syncfifo_fifo_in_first = link_litesatalinkrx_crc_syncfifo_sink_first; assign link_litesatalinkrx_crc_syncfifo_fifo_in_last = link_litesatalinkrx_crc_syncfifo_sink_last; assign link_litesatalinkrx_crc_syncfifo_fifo_in_payload_data = link_litesatalinkrx_crc_syncfifo_sink_payload_data; assign link_litesatalinkrx_crc_syncfifo_fifo_in_payload_error = link_litesatalinkrx_crc_syncfifo_sink_payload_error; assign link_litesatalinkrx_crc_syncfifo_source_valid = link_litesatalinkrx_crc_syncfifo_syncfifo_readable; assign link_litesatalinkrx_crc_syncfifo_source_first = link_litesatalinkrx_crc_syncfifo_fifo_out_first; assign link_litesatalinkrx_crc_syncfifo_source_last = link_litesatalinkrx_crc_syncfifo_fifo_out_last; assign link_litesatalinkrx_crc_syncfifo_source_payload_data = link_litesatalinkrx_crc_syncfifo_fifo_out_payload_data; assign link_litesatalinkrx_crc_syncfifo_source_payload_error = link_litesatalinkrx_crc_syncfifo_fifo_out_payload_error; assign link_litesatalinkrx_crc_syncfifo_syncfifo_re = link_litesatalinkrx_crc_syncfifo_source_ready; always @(*) begin link_litesatalinkrx_crc_syncfifo_wrport_adr <= 1'd0; if (link_litesatalinkrx_crc_syncfifo_replace) begin link_litesatalinkrx_crc_syncfifo_wrport_adr <= (link_litesatalinkrx_crc_syncfifo_produce - 1'd1); end else begin link_litesatalinkrx_crc_syncfifo_wrport_adr <= link_litesatalinkrx_crc_syncfifo_produce; end end assign link_litesatalinkrx_crc_syncfifo_wrport_dat_w = link_litesatalinkrx_crc_syncfifo_syncfifo_din; assign link_litesatalinkrx_crc_syncfifo_wrport_we = (link_litesatalinkrx_crc_syncfifo_syncfifo_we & (link_litesatalinkrx_crc_syncfifo_syncfifo_writable | link_litesatalinkrx_crc_syncfifo_replace)); assign link_litesatalinkrx_crc_syncfifo_do_read = (link_litesatalinkrx_crc_syncfifo_syncfifo_readable & link_litesatalinkrx_crc_syncfifo_syncfifo_re); assign link_litesatalinkrx_crc_syncfifo_rdport_adr = link_litesatalinkrx_crc_syncfifo_consume; assign link_litesatalinkrx_crc_syncfifo_syncfifo_dout = link_litesatalinkrx_crc_syncfifo_rdport_dat_r; assign link_litesatalinkrx_crc_syncfifo_syncfifo_writable = (link_litesatalinkrx_crc_syncfifo_level != 2'd2); assign link_litesatalinkrx_crc_syncfifo_syncfifo_readable = (link_litesatalinkrx_crc_syncfifo_level != 1'd0); always @(*) begin link_litesatalinkrx_crc_fifo_reset <= 1'd0; link_litesatalinkrx_crc_crc_ce <= 1'd0; subfragments_litesatalinkrx_litesatacrcchecker_next_state <= 2'd0; link_litesatalinkrx_crc_crc_reset <= 1'd0; link_litesatalinkrx_crc_crc_data0 <= 32'd0; link_litesatalinkrx_crc_is_ongoing <= 1'd0; subfragments_litesatalinkrx_litesatacrcchecker_next_state <= subfragments_litesatalinkrx_litesatacrcchecker_state; case (subfragments_litesatalinkrx_litesatacrcchecker_state) 1'd1: begin link_litesatalinkrx_crc_crc_data0 <= link_litesatalinkrx_crc_sink_sink_payload_data; if ((link_litesatalinkrx_crc_sink_sink_valid & link_litesatalinkrx_crc_sink_sink_ready)) begin link_litesatalinkrx_crc_crc_ce <= 1'd1; subfragments_litesatalinkrx_litesatacrcchecker_next_state <= 2'd2; end link_litesatalinkrx_crc_is_ongoing <= 1'd1; end 2'd2: begin link_litesatalinkrx_crc_crc_data0 <= link_litesatalinkrx_crc_sink_sink_payload_data; if ((link_litesatalinkrx_crc_sink_sink_valid & link_litesatalinkrx_crc_sink_sink_ready)) begin link_litesatalinkrx_crc_crc_ce <= 1'd1; if (link_litesatalinkrx_crc_sink_sink_last) begin subfragments_litesatalinkrx_litesatacrcchecker_next_state <= 1'd0; end end end default: begin link_litesatalinkrx_crc_crc_reset <= 1'd1; link_litesatalinkrx_crc_fifo_reset <= 1'd1; subfragments_litesatalinkrx_litesatacrcchecker_next_state <= 1'd1; end endcase end assign link_litesatalinkrx_crc_sink_sink_valid = link_litesatalinkrx_descrambler_source_valid; assign link_litesatalinkrx_descrambler_source_ready = link_litesatalinkrx_crc_sink_sink_ready; assign link_litesatalinkrx_crc_sink_sink_first = link_litesatalinkrx_descrambler_source_first; assign link_litesatalinkrx_crc_sink_sink_last = link_litesatalinkrx_descrambler_source_last; assign link_litesatalinkrx_crc_sink_sink_payload_data = link_litesatalinkrx_descrambler_source_payload_data; assign link_litesatalinkrx_crc_sink_sink_payload_error = link_litesatalinkrx_descrambler_source_payload_error; assign link_litesatalinkrx_source_source_valid = link_litesatalinkrx_crc_source_source_valid; assign link_litesatalinkrx_crc_source_source_ready = link_litesatalinkrx_source_source_ready; assign link_litesatalinkrx_source_source_first = link_litesatalinkrx_crc_source_source_first; assign link_litesatalinkrx_source_source_last = link_litesatalinkrx_crc_source_source_last; assign link_litesatalinkrx_source_source_payload_data = link_litesatalinkrx_crc_source_source_payload_data; assign link_litesatalinkrx_source_source_payload_error = link_litesatalinkrx_crc_source_source_payload_error; always @(*) begin link_litesatalinkrx_insert <= 32'd0; link_litesatalinkrx_descrambler_sink_last <= 1'd0; link_litesatalinkrx_fsm_is_ongoing <= 1'd0; subfragments_litesatalinkrx_fsm_next_state <= 3'd0; link_litesatalinkrx_descrambler_sink_valid <= 1'd0; link_litesatalinkrx_descrambler_reset <= 1'd0; subfragments_litesatalinkrx_fsm_next_state <= subfragments_litesatalinkrx_fsm_state; case (subfragments_litesatalinkrx_fsm_state) 1'd1: begin link_litesatalinkrx_insert <= 31'd1246401916; if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 30'd926397820))) begin subfragments_litesatalinkrx_fsm_next_state <= 2'd2; end end 2'd2: begin link_litesatalinkrx_insert <= 31'd1431680380; if (link_litesatalinkrx_data_valid) begin subfragments_litesatalinkrx_fsm_next_state <= 2'd3; end end 2'd3: begin link_litesatalinkrx_descrambler_sink_valid <= link_litesatalinkrx_data_valid; link_litesatalinkrx_insert <= 31'd1431680380; if (link_litesatalinkrx_primitive_valid) begin if ((link_litesatalinkrx_primitive == 32'd3587549820)) begin link_litesatalinkrx_insert <= 32'd2509613692; end else begin if ((link_litesatalinkrx_primitive == 32'd3587552636)) begin link_litesatalinkrx_descrambler_sink_valid <= 1'd1; link_litesatalinkrx_descrambler_sink_last <= 1'd1; subfragments_litesatalinkrx_fsm_next_state <= 3'd5; end end end else begin if (link_litesatalinkrx_hold) begin link_litesatalinkrx_insert <= 32'd3587549820; end end end 3'd4: begin link_litesatalinkrx_insert <= 31'd1431680380; if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 31'd1482208636))) begin subfragments_litesatalinkrx_fsm_next_state <= 3'd5; end end 3'd5: begin link_litesatalinkrx_insert <= 31'd1431680380; if ((~link_litesatalinkrx_crc_error)) begin subfragments_litesatalinkrx_fsm_next_state <= 3'd6; end else begin subfragments_litesatalinkrx_fsm_next_state <= 3'd7; end end 3'd6: begin link_litesatalinkrx_insert <= 30'd892712316; if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 32'd3048576380))) begin subfragments_litesatalinkrx_fsm_next_state <= 1'd0; end end 3'd7: begin link_litesatalinkrx_insert <= 31'd1448523132; if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 32'd3048576380))) begin subfragments_litesatalinkrx_fsm_next_state <= 1'd0; end end default: begin link_litesatalinkrx_descrambler_reset <= 1'd1; if ((link_litesatalinkrx_primitive_valid & (link_litesatalinkrx_primitive == 31'd1465365884))) begin subfragments_litesatalinkrx_fsm_next_state <= 1'd1; end link_litesatalinkrx_fsm_is_ongoing <= 1'd1; end endcase end assign link_rx_sink_ready = ((~link_rx_source_valid) | link_rx_source_ready); assign link_rx_buffer_syncfifo_din = {link_rx_buffer_fifo_in_last, link_rx_buffer_fifo_in_first, link_rx_buffer_fifo_in_payload_error, link_rx_buffer_fifo_in_payload_data}; assign {link_rx_buffer_fifo_out_last, link_rx_buffer_fifo_out_first, link_rx_buffer_fifo_out_payload_error, link_rx_buffer_fifo_out_payload_data} = link_rx_buffer_syncfifo_dout; assign link_rx_buffer_sink_ready = link_rx_buffer_syncfifo_writable; assign link_rx_buffer_syncfifo_we = link_rx_buffer_sink_valid; assign link_rx_buffer_fifo_in_first = link_rx_buffer_sink_first; assign link_rx_buffer_fifo_in_last = link_rx_buffer_sink_last; assign link_rx_buffer_fifo_in_payload_data = link_rx_buffer_sink_payload_data; assign link_rx_buffer_fifo_in_payload_error = link_rx_buffer_sink_payload_error; assign link_rx_buffer_source_valid = link_rx_buffer_syncfifo_readable; assign link_rx_buffer_source_first = link_rx_buffer_fifo_out_first; assign link_rx_buffer_source_last = link_rx_buffer_fifo_out_last; assign link_rx_buffer_source_payload_data = link_rx_buffer_fifo_out_payload_data; assign link_rx_buffer_source_payload_error = link_rx_buffer_fifo_out_payload_error; assign link_rx_buffer_syncfifo_re = link_rx_buffer_source_ready; always @(*) begin link_rx_buffer_wrport_adr <= 7'd0; if (link_rx_buffer_replace) begin link_rx_buffer_wrport_adr <= (link_rx_buffer_produce - 1'd1); end else begin link_rx_buffer_wrport_adr <= link_rx_buffer_produce; end end assign link_rx_buffer_wrport_dat_w = link_rx_buffer_syncfifo_din; assign link_rx_buffer_wrport_we = (link_rx_buffer_syncfifo_we & (link_rx_buffer_syncfifo_writable | link_rx_buffer_replace)); assign link_rx_buffer_do_read = (link_rx_buffer_syncfifo_readable & link_rx_buffer_syncfifo_re); assign link_rx_buffer_rdport_adr = link_rx_buffer_consume; assign link_rx_buffer_syncfifo_dout = link_rx_buffer_rdport_dat_r; assign link_rx_buffer_syncfifo_writable = (link_rx_buffer_level != 8'd128); assign link_rx_buffer_syncfifo_readable = (link_rx_buffer_level != 1'd0); assign link_rx_align_sink_valid = datapath_source_source_valid; assign datapath_source_source_ready = link_rx_align_sink_ready; assign link_rx_align_sink_first = datapath_source_source_first; assign link_rx_align_sink_last = datapath_source_source_last; assign link_rx_align_sink_payload_data = datapath_source_source_payload_data; assign link_rx_align_sink_payload_charisk = datapath_source_source_payload_charisk; assign link_rx_cont_sink_valid = link_rx_align_source_valid; assign link_rx_align_source_ready = link_rx_cont_sink_ready; assign link_rx_cont_sink_first = link_rx_align_source_first; assign link_rx_cont_sink_last = link_rx_align_source_last; assign link_rx_cont_sink_payload_data = link_rx_align_source_payload_data; assign link_rx_cont_sink_payload_charisk = link_rx_align_source_payload_charisk; assign link_rx_sink_valid = link_rx_cont_source_valid; assign link_rx_cont_source_ready = link_rx_sink_ready; assign link_rx_sink_first = link_rx_cont_source_first; assign link_rx_sink_last = link_rx_cont_source_last; assign link_rx_sink_payload_data = link_rx_cont_source_payload_data; assign link_rx_sink_payload_charisk = link_rx_cont_source_payload_charisk; assign link_rx_buffer_sink_valid = link_litesatalinkrx_source_source_valid; assign link_litesatalinkrx_source_source_ready = link_rx_buffer_sink_ready; assign link_rx_buffer_sink_first = link_litesatalinkrx_source_source_first; assign link_rx_buffer_sink_last = link_litesatalinkrx_source_source_last; assign link_rx_buffer_sink_payload_data = link_litesatalinkrx_source_source_payload_data; assign link_rx_buffer_sink_payload_error = link_litesatalinkrx_source_source_payload_error; assign transport_tx_counter_ce = (transport_tx_sink_valid & link_litesatalinktx_sink_sink_ready); assign transport_tx_cmd_done = (((transport_tx_counter == transport_tx_cmd_len) & link_litesatalinktx_sink_sink_valid) & link_litesatalinktx_sink_sink_ready); always @(*) begin link_litesatalinktx_sink_sink_payload_data <= 32'd0; link_litesatalinktx_sink_sink_last <= 1'd0; link_litesatalinktx_sink_sink_valid <= 1'd0; if (transport_tx_cmd_send) begin link_litesatalinktx_sink_sink_valid <= transport_tx_sink_valid; link_litesatalinktx_sink_sink_last <= ((transport_tx_counter == transport_tx_cmd_len) & (~transport_tx_cmd_with_data)); case (transport_tx_counter) 1'd0: begin link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[31:0]; end 1'd1: begin link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[63:32]; end 2'd2: begin link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[95:64]; end 2'd3: begin link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[127:96]; end 3'd4: begin link_litesatalinktx_sink_sink_payload_data <= transport_tx_encoded_cmd[159:128]; end endcase end else begin if (transport_tx_data_send) begin link_litesatalinktx_sink_sink_valid <= transport_tx_sink_valid; link_litesatalinktx_sink_sink_last <= transport_tx_sink_last; link_litesatalinktx_sink_sink_payload_data <= transport_tx_sink_payload_data; end end end always @(*) begin transport_tx_counter_reset <= 1'd0; transport_tx_cmd_len <= 3'd0; transport_tx_cmd_with_data <= 1'd0; transport_tx_cmd_send <= 1'd0; transport_tx_data_send <= 1'd0; transport_tx_update_fis_type <= 1'd0; subfragments_litesatatransporttx_next_state <= 2'd0; transport_tx_encoded_cmd <= 160'd0; transport_tx_sink_ready <= 1'd0; subfragments_litesatatransporttx_next_state <= subfragments_litesatatransporttx_state; case (subfragments_litesatatransporttx_state) 1'd1: begin transport_tx_encoded_cmd[15] <= transport_tx_sink_param_c; transport_tx_encoded_cmd[23:16] <= transport_tx_sink_param_command; transport_tx_encoded_cmd[127:120] <= transport_tx_sink_param_control; transport_tx_encoded_cmd[111:96] <= transport_tx_sink_param_count; transport_tx_encoded_cmd[63:56] <= transport_tx_sink_param_device; transport_tx_encoded_cmd[31:24] <= transport_tx_sink_param_features[7:0]; transport_tx_encoded_cmd[95:88] <= transport_tx_sink_param_features[15:8]; transport_tx_encoded_cmd[119:112] <= transport_tx_sink_param_icc; transport_tx_encoded_cmd[55:32] <= transport_tx_sink_param_lba[23:0]; transport_tx_encoded_cmd[87:64] <= transport_tx_sink_param_lba[47:24]; transport_tx_encoded_cmd[11:8] <= transport_tx_sink_param_pm_port; transport_tx_encoded_cmd[7:0] <= transport_tx_sink_param_type; transport_tx_cmd_len <= 3'd4; transport_tx_cmd_send <= 1'd1; if (transport_tx_cmd_done) begin transport_tx_sink_ready <= 1'd1; subfragments_litesatatransporttx_next_state <= 1'd0; end end 2'd2: begin transport_tx_sink_ready <= 1'd0; transport_tx_encoded_cmd[7:0] <= transport_tx_sink_param_type; transport_tx_cmd_len <= 1'd0; transport_tx_cmd_with_data <= 1'd1; transport_tx_cmd_send <= 1'd1; if (transport_tx_cmd_done) begin subfragments_litesatatransporttx_next_state <= 2'd3; end end 2'd3: begin transport_tx_data_send <= 1'd1; transport_tx_sink_ready <= link_litesatalinktx_sink_sink_ready; if (((transport_tx_sink_valid & transport_tx_sink_last) & transport_tx_sink_ready)) begin subfragments_litesatatransporttx_next_state <= 1'd0; end end default: begin transport_tx_sink_ready <= 1'd0; transport_tx_counter_reset <= 1'd1; transport_tx_update_fis_type <= 1'd1; if (transport_tx_sink_valid) begin if ((transport_tx_sink_param_type == 6'd39)) begin subfragments_litesatatransporttx_next_state <= 1'd1; end else begin if ((transport_tx_sink_param_type == 7'd70)) begin subfragments_litesatatransporttx_next_state <= 2'd2; end else begin transport_tx_sink_ready <= 1'd1; end end end else begin transport_tx_sink_ready <= 1'd1; end end endcase end always @(*) begin transport_rx_counter_ce <= 1'd0; if ((transport_rx_cmd_receive & link_rx_buffer_source_valid)) begin transport_rx_counter_ce <= 1'd1; end end assign transport_rx_cmd_done = ((transport_rx_counter == transport_rx_cmd_len) & link_rx_buffer_source_ready); always @(*) begin transport_rx_source_param_errors <= 8'd0; transport_rx_source_param_lba <= 48'd0; transport_rx_source_param_device <= 8'd0; transport_rx_source_param_count <= 16'd0; transport_rx_source_param_status <= 8'd0; transport_rx_source_param_transfer_count <= 16'd0; transport_rx_source_param_error <= 1'd0; transport_rx_counter_reset <= 1'd0; transport_rx_cmd_len <= 3'd0; transport_rx_cmd_receive <= 1'd0; transport_rx_data_receive <= 1'd0; link_rx_buffer_source_ready <= 1'd0; transport_rx_update_fis_type <= 1'd0; transport_rx_source_valid <= 1'd0; transport_rx_source_last <= 1'd0; transport_rx_source_payload_data <= 32'd0; transport_rx_source_param_type <= 8'd0; transport_rx_source_param_pm_port <= 4'd0; transport_rx_source_param_d <= 1'd0; transport_rx_source_param_i <= 1'd0; subfragments_litesatatransportrx_next_state <= 3'd0; subfragments_litesatatransportrx_next_state <= subfragments_litesatatransportrx_state; case (subfragments_litesatatransportrx_state) 1'd1: begin if ((transport_rx_fis_type == 6'd52)) begin transport_rx_cmd_len <= 3'd4; end else begin if ((transport_rx_fis_type == 6'd57)) begin transport_rx_cmd_len <= 1'd0; end else begin transport_rx_cmd_len <= 3'd4; end end transport_rx_cmd_receive <= 1'd1; link_rx_buffer_source_ready <= 1'd1; if (transport_rx_cmd_done) begin subfragments_litesatatransportrx_next_state <= 2'd2; end end 2'd2: begin transport_rx_source_valid <= 1'd1; transport_rx_source_last <= 1'd1; if ((transport_rx_fis_type == 6'd52)) begin transport_rx_source_param_count <= transport_rx_encoded_cmd[111:96]; transport_rx_source_param_device <= transport_rx_encoded_cmd[63:56]; transport_rx_source_param_errors <= transport_rx_encoded_cmd[31:24]; transport_rx_source_param_i <= transport_rx_encoded_cmd[14]; transport_rx_source_param_lba[23:0] <= transport_rx_encoded_cmd[55:32]; transport_rx_source_param_lba[47:24] <= transport_rx_encoded_cmd[87:64]; transport_rx_source_param_pm_port <= transport_rx_encoded_cmd[11:8]; transport_rx_source_param_status <= transport_rx_encoded_cmd[23:16]; transport_rx_source_param_type <= transport_rx_encoded_cmd[7:0]; end else begin if ((transport_rx_fis_type == 6'd57)) begin transport_rx_source_param_pm_port <= transport_rx_encoded_cmd[11:8]; transport_rx_source_param_type <= transport_rx_encoded_cmd[7:0]; end else begin transport_rx_source_param_count <= transport_rx_encoded_cmd[111:96]; transport_rx_source_param_d <= transport_rx_encoded_cmd[13]; transport_rx_source_param_errors <= transport_rx_encoded_cmd[31:24]; transport_rx_source_param_i <= transport_rx_encoded_cmd[14]; transport_rx_source_param_lba[23:0] <= transport_rx_encoded_cmd[55:32]; transport_rx_source_param_lba[47:24] <= transport_rx_encoded_cmd[87:64]; transport_rx_source_param_pm_port <= transport_rx_encoded_cmd[11:8]; transport_rx_source_param_status <= transport_rx_encoded_cmd[23:16]; transport_rx_source_param_transfer_count <= transport_rx_encoded_cmd[143:128]; transport_rx_source_param_type <= transport_rx_encoded_cmd[7:0]; end end if ((transport_rx_source_valid & transport_rx_source_ready)) begin subfragments_litesatatransportrx_next_state <= 1'd0; end end 2'd3: begin transport_rx_cmd_len <= 1'd0; transport_rx_cmd_receive <= 1'd1; link_rx_buffer_source_ready <= 1'd1; if (transport_rx_cmd_done) begin subfragments_litesatatransportrx_next_state <= 3'd4; end end 3'd4: begin transport_rx_data_receive <= 1'd1; transport_rx_source_valid <= link_rx_buffer_source_valid; transport_rx_source_param_type <= transport_rx_encoded_cmd[7:0]; transport_rx_source_last <= link_rx_buffer_source_last; transport_rx_source_param_error <= link_rx_buffer_source_payload_error; transport_rx_source_payload_data <= link_rx_buffer_source_payload_data; link_rx_buffer_source_ready <= transport_rx_source_ready; if (((transport_rx_source_valid & transport_rx_source_last) & transport_rx_source_ready)) begin subfragments_litesatatransportrx_next_state <= 1'd0; end end default: begin link_rx_buffer_source_ready <= 1'd0; transport_rx_counter_reset <= 1'd1; transport_rx_update_fis_type <= 1'd1; if (link_rx_buffer_source_valid) begin if ((link_rx_buffer_source_payload_data[7:0] == 6'd52)) begin subfragments_litesatatransportrx_next_state <= 1'd1; end else begin if ((link_rx_buffer_source_payload_data[7:0] == 6'd57)) begin subfragments_litesatatransportrx_next_state <= 1'd1; end else begin if ((link_rx_buffer_source_payload_data[7:0] == 7'd95)) begin subfragments_litesatatransportrx_next_state <= 1'd1; end else begin if ((link_rx_buffer_source_payload_data[7:0] == 7'd70)) begin subfragments_litesatatransportrx_next_state <= 2'd3; end else begin link_rx_buffer_source_ready <= 1'd1; end end end end end else begin link_rx_buffer_source_ready <= 1'd1; end end endcase end assign command_tx_from_rx_valid = command_rx_to_tx_valid; assign command_rx_to_tx_ready = command_tx_from_rx_ready; assign command_tx_from_rx_first = command_rx_to_tx_first; assign command_tx_from_rx_last = command_rx_to_tx_last; assign command_tx_from_rx_payload_dma_activate = command_rx_to_tx_payload_dma_activate; assign command_tx_from_rx_payload_d2h_error = command_rx_to_tx_payload_d2h_error; assign command_rx_from_tx_valid = command_tx_to_rx_valid; assign command_tx_to_rx_ready = command_rx_from_tx_ready; assign command_rx_from_tx_first = command_tx_to_rx_first; assign command_rx_from_tx_last = command_tx_to_rx_last; assign command_rx_from_tx_payload_write = command_tx_to_rx_payload_write; assign command_rx_from_tx_payload_read = command_tx_to_rx_payload_read; assign command_rx_from_tx_payload_identify = command_tx_to_rx_payload_identify; assign command_rx_from_tx_payload_count = command_tx_to_rx_payload_count; assign transport_tx_sink_param_pm_port = 1'd0; assign transport_tx_sink_param_features = 1'd0; assign transport_tx_sink_param_lba = command_tx_sink_param_sector; assign transport_tx_sink_param_device = 8'd224; assign transport_tx_sink_param_count = command_tx_sink_param_count; assign transport_tx_sink_param_icc = 1'd0; assign transport_tx_sink_param_control = 1'd0; assign transport_tx_sink_payload_data = command_tx_sink_payload_data; always @(*) begin transport_tx_sink_param_command <= 8'd0; transport_tx_sink_param_type <= 8'd0; if (command_tx_is_ongoing1) begin transport_tx_sink_param_type <= 7'd70; end else begin transport_tx_sink_param_type <= 6'd39; if (command_tx_is_write) begin transport_tx_sink_param_command <= 6'd53; end else begin if (command_tx_is_read) begin transport_tx_sink_param_command <= 6'd37; end else begin transport_tx_sink_param_command <= 8'd236; end end end end always @(*) begin command_tx_to_rx_payload_write <= 1'd0; command_tx_to_rx_payload_read <= 1'd0; command_tx_to_rx_payload_identify <= 1'd0; command_tx_to_rx_payload_count <= 16'd0; if (command_tx_sink_valid) begin command_tx_to_rx_payload_write <= command_tx_sink_param_write; command_tx_to_rx_payload_read <= command_tx_sink_param_read; command_tx_to_rx_payload_identify <= command_tx_sink_param_identify; command_tx_to_rx_payload_count <= command_tx_sink_param_count; end end always @(*) begin command_tx_dwords_counter_subfragments_litesatacommandtx_next_value <= 11'd0; transport_tx_sink_last <= 1'd0; command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce <= 1'd0; command_tx_is_ongoing1 <= 1'd0; transport_tx_sink_param_c <= 1'd0; command_tx_is_ongoing0 <= 1'd0; command_tx_sink_ready <= 1'd0; subfragments_litesatacommandtx_next_state <= 2'd0; transport_tx_sink_valid <= 1'd0; subfragments_litesatacommandtx_next_state <= subfragments_litesatacommandtx_state; case (subfragments_litesatacommandtx_state) 1'd1: begin transport_tx_sink_valid <= command_tx_sink_valid; transport_tx_sink_last <= 1'd1; transport_tx_sink_param_c <= 1'd1; if ((transport_tx_sink_valid & transport_tx_sink_ready)) begin if (command_tx_is_write) begin subfragments_litesatacommandtx_next_state <= 2'd2; end else begin command_tx_sink_ready <= 1'd1; subfragments_litesatacommandtx_next_state <= 1'd0; end end end 2'd2: begin command_tx_dwords_counter_subfragments_litesatacommandtx_next_value <= 1'd0; command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce <= 1'd1; if (command_tx_from_rx_payload_dma_activate) begin subfragments_litesatacommandtx_next_state <= 2'd3; end else begin if (command_tx_from_rx_payload_d2h_error) begin command_tx_sink_ready <= 1'd1; subfragments_litesatacommandtx_next_state <= 1'd0; end end end 2'd3: begin transport_tx_sink_valid <= command_tx_sink_valid; transport_tx_sink_last <= ((command_tx_dwords_counter == 11'd2047) | command_tx_sink_last); command_tx_sink_ready <= transport_tx_sink_ready; if ((command_tx_sink_valid & command_tx_sink_ready)) begin command_tx_dwords_counter_subfragments_litesatacommandtx_next_value <= (command_tx_dwords_counter + 1'd1); command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce <= 1'd1; if (command_tx_sink_last) begin subfragments_litesatacommandtx_next_state <= 1'd0; end else begin if ((command_tx_dwords_counter == 11'd2047)) begin subfragments_litesatacommandtx_next_state <= 2'd2; end end end command_tx_is_ongoing1 <= 1'd1; end default: begin command_tx_sink_ready <= 1'd0; if (command_tx_sink_valid) begin subfragments_litesatacommandtx_next_state <= 1'd1; end else begin command_tx_sink_ready <= 1'd1; end command_tx_is_ongoing0 <= 1'd1; end endcase end assign command_rx_read_done = (command_rx_dwords_counter == command_rx_read_ndwords); assign command_rx_to_tx_payload_dma_activate = command_rx_is_dma_activate; assign command_rx_to_tx_payload_d2h_error = command_rx_d2h_error; always @(*) begin command_rx_is_dma_activate <= 1'd0; command_rx_source_valid <= 1'd0; command_rx_clr_d2h_error <= 1'd0; command_rx_source_last <= 1'd0; command_rx_set_d2h_error <= 1'd0; command_rx_source_payload_data <= 32'd0; command_rx_source_param_write <= 1'd0; command_rx_source_param_read <= 1'd0; command_rx_clr_read_error <= 1'd0; subfragments_litesatacommandrx_next_state <= 4'd0; command_rx_set_read_error <= 1'd0; command_rx_dwords_counter_subfragments_litesatacommandrx_next_value <= 23'd0; command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce <= 1'd0; command_rx_source_param_identify <= 1'd0; command_rx_update_d2h <= 1'd0; command_rx_source_param_end <= 1'd0; command_rx_source_param_failed <= 1'd0; command_rx_is_ongoing <= 1'd0; transport_rx_source_ready <= 1'd0; subfragments_litesatacommandrx_next_state <= subfragments_litesatacommandrx_state; case (subfragments_litesatacommandrx_state) 1'd1: begin transport_rx_source_ready <= 1'd1; if (transport_rx_source_valid) begin if ((transport_rx_source_param_type == 6'd57)) begin command_rx_is_dma_activate <= 1'd1; end else begin if ((transport_rx_source_param_type == 6'd52)) begin command_rx_update_d2h <= 1'd1; command_rx_set_d2h_error <= transport_rx_source_param_status[0]; subfragments_litesatacommandrx_next_state <= 2'd2; end end end end 2'd2: begin command_rx_source_valid <= 1'd1; command_rx_source_last <= 1'd1; command_rx_source_param_write <= 1'd1; command_rx_source_param_end <= 1'd1; command_rx_source_param_failed <= (transport_rx_source_param_error | command_rx_d2h_error); if ((command_rx_source_valid & command_rx_source_ready)) begin subfragments_litesatacommandrx_next_state <= 1'd0; end end 2'd3: begin transport_rx_source_ready <= 1'd1; if (transport_rx_source_valid) begin transport_rx_source_ready <= 1'd0; if ((transport_rx_source_param_type == 7'd70)) begin subfragments_litesatacommandrx_next_state <= 3'd6; end else begin if ((transport_rx_source_param_type == 6'd52)) begin command_rx_update_d2h <= 1'd1; command_rx_set_d2h_error <= transport_rx_source_param_status[0]; subfragments_litesatacommandrx_next_state <= 3'd7; end end end end 3'd4: begin transport_rx_source_ready <= 1'd1; if (transport_rx_source_valid) begin transport_rx_source_ready <= 1'd0; if ((transport_rx_source_param_type == 7'd95)) begin subfragments_litesatacommandrx_next_state <= 3'd5; end else begin subfragments_litesatacommandrx_next_state <= 4'd8; end end end 3'd5: begin transport_rx_source_ready <= 1'd1; if ((transport_rx_source_valid & transport_rx_source_last)) begin subfragments_litesatacommandrx_next_state <= 2'd3; end end 3'd6: begin command_rx_set_read_error <= transport_rx_source_param_error; command_rx_source_valid <= transport_rx_source_valid; command_rx_source_last <= transport_rx_source_last; command_rx_source_param_read <= (~command_rx_is_identify); command_rx_source_param_identify <= command_rx_is_identify; command_rx_source_param_failed <= transport_rx_source_param_error; command_rx_source_param_end <= command_rx_is_identify; command_rx_source_payload_data <= transport_rx_source_payload_data; transport_rx_source_ready <= command_rx_source_ready; if ((command_rx_source_valid & command_rx_source_ready)) begin if ((~command_rx_read_done)) begin command_rx_dwords_counter_subfragments_litesatacommandrx_next_value <= (command_rx_dwords_counter + 1'd1); command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce <= 1'd1; end if (command_rx_source_last) begin if (command_rx_is_identify) begin subfragments_litesatacommandrx_next_state <= 1'd0; end else begin subfragments_litesatacommandrx_next_state <= 2'd3; end end end end 3'd7: begin command_rx_source_valid <= 1'd1; command_rx_source_last <= 1'd1; command_rx_source_param_read <= 1'd1; command_rx_source_param_end <= 1'd1; command_rx_source_param_failed <= (((~command_rx_read_done) | command_rx_read_error) | command_rx_d2h_error); if ((command_rx_source_valid & command_rx_source_ready)) begin subfragments_litesatacommandrx_next_state <= 1'd0; end end 4'd8: begin transport_rx_source_ready <= 1'd1; if ((transport_rx_source_valid & transport_rx_source_last)) begin subfragments_litesatacommandrx_next_state <= 3'd4; end end default: begin command_rx_dwords_counter_subfragments_litesatacommandrx_next_value <= 1'd0; command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce <= 1'd1; transport_rx_source_ready <= 1'd1; command_rx_clr_d2h_error <= 1'd1; command_rx_clr_read_error <= 1'd1; if (command_rx_from_tx_payload_write) begin subfragments_litesatacommandrx_next_state <= 1'd1; end else begin if (command_rx_from_tx_payload_read) begin subfragments_litesatacommandrx_next_state <= 2'd3; end else begin if (command_rx_from_tx_payload_identify) begin subfragments_litesatacommandrx_next_state <= 3'd4; end end end command_rx_is_ongoing <= 1'd1; end endcase end assign command_tx_sink_valid = source_valid; assign source_ready = command_tx_sink_ready; assign command_tx_sink_first = source_first; assign command_tx_sink_last = source_last; assign command_tx_sink_payload_data = source_payload_data; assign command_tx_sink_param_write = source_param_write; assign command_tx_sink_param_read = source_param_read; assign command_tx_sink_param_identify = source_param_identify; assign command_tx_sink_param_sector = source_param_sector; assign command_tx_sink_param_count = source_param_count; assign sink_valid = command_rx_source_valid; assign command_rx_source_ready = sink_ready; assign sink_first = command_rx_source_first; assign sink_last = command_rx_source_last; assign sink_payload_data = command_rx_source_payload_data; assign sink_param_write = command_rx_source_param_write; assign sink_param_read = command_rx_source_param_read; assign sink_param_identify = command_rx_source_param_identify; assign sink_param_end = command_rx_source_param_end; assign sink_param_failed = command_rx_source_param_failed; assign subfragments_done0 = (((litesatauserport0_source_valid & litesatauserport0_source_last) & litesatauserport0_source_param_end) & litesatauserport0_source_ready); assign subfragments_done1 = (((litesatauserport1_source_valid & litesatauserport1_source_last) & litesatauserport1_source_param_end) & litesatauserport1_source_ready); always @(*) begin subfragments_request <= 2'd0; subfragments_request[0] <= ((litesatauserport0_sink_valid | subfragments_ongoing0) & (~subfragments_done0)); subfragments_request[1] <= ((litesatauserport1_sink_valid | subfragments_ongoing1) & (~subfragments_done1)); end always @(*) begin litesatauserport1_sink_ready <= 1'd0; litesatauserport0_sink_ready <= 1'd0; source_valid <= 1'd0; litesatauserport1_source_valid <= 1'd0; source_first <= 1'd0; source_last <= 1'd0; litesatauserport1_source_first <= 1'd0; source_payload_data <= 32'd0; litesatauserport1_source_last <= 1'd0; source_param_write <= 1'd0; litesatauserport1_source_payload_data <= 32'd0; source_param_read <= 1'd0; litesatauserport1_source_param_write <= 1'd0; source_param_identify <= 1'd0; litesatauserport1_source_param_read <= 1'd0; source_param_sector <= 48'd0; litesatauserport1_source_param_identify <= 1'd0; litesatauserport0_source_valid <= 1'd0; source_param_count <= 16'd0; litesatauserport1_source_param_end <= 1'd0; litesatauserport1_source_param_failed <= 1'd0; litesatauserport0_source_first <= 1'd0; sink_ready <= 1'd0; litesatauserport0_source_last <= 1'd0; litesatauserport0_source_payload_data <= 32'd0; litesatauserport0_source_param_write <= 1'd0; litesatauserport0_source_param_read <= 1'd0; litesatauserport0_source_param_identify <= 1'd0; litesatauserport0_source_param_end <= 1'd0; litesatauserport0_source_param_failed <= 1'd0; case (subfragments_grant) 1'd0: begin source_valid <= litesatauserport0_sink_valid; litesatauserport0_sink_ready <= source_ready; source_first <= litesatauserport0_sink_first; source_last <= litesatauserport0_sink_last; source_payload_data <= litesatauserport0_sink_payload_data; source_param_write <= litesatauserport0_sink_param_write; source_param_read <= litesatauserport0_sink_param_read; source_param_identify <= litesatauserport0_sink_param_identify; source_param_sector <= litesatauserport0_sink_param_sector; source_param_count <= litesatauserport0_sink_param_count; litesatauserport0_source_valid <= sink_valid; sink_ready <= litesatauserport0_source_ready; litesatauserport0_source_first <= sink_first; litesatauserport0_source_last <= sink_last; litesatauserport0_source_payload_data <= sink_payload_data; litesatauserport0_source_param_write <= sink_param_write; litesatauserport0_source_param_read <= sink_param_read; litesatauserport0_source_param_identify <= sink_param_identify; litesatauserport0_source_param_end <= sink_param_end; litesatauserport0_source_param_failed <= sink_param_failed; end 1'd1: begin source_valid <= litesatauserport1_sink_valid; litesatauserport1_sink_ready <= source_ready; source_first <= litesatauserport1_sink_first; source_last <= litesatauserport1_sink_last; source_payload_data <= litesatauserport1_sink_payload_data; source_param_write <= litesatauserport1_sink_param_write; source_param_read <= litesatauserport1_sink_param_read; source_param_identify <= litesatauserport1_sink_param_identify; source_param_sector <= litesatauserport1_sink_param_sector; source_param_count <= litesatauserport1_sink_param_count; litesatauserport1_source_valid <= sink_valid; sink_ready <= litesatauserport1_source_ready; litesatauserport1_source_first <= sink_first; litesatauserport1_source_last <= sink_last; litesatauserport1_source_payload_data <= sink_payload_data; litesatauserport1_source_param_write <= sink_param_write; litesatauserport1_source_param_read <= sink_param_read; litesatauserport1_source_param_identify <= sink_param_identify; litesatauserport1_source_param_end <= sink_param_end; litesatauserport1_source_param_failed <= sink_param_failed; end endcase end assign sata_sector2mem_buf_sink_valid = litesatauserport0_source_valid; assign litesatauserport0_source_ready = sata_sector2mem_buf_sink_ready; assign sata_sector2mem_buf_sink_last = litesatauserport0_source_last; assign sata_sector2mem_buf_sink_payload_data = litesatauserport0_source_payload_data; assign sata_sector2mem_converter_sink_valid = sata_sector2mem_buf_source_valid; assign sata_sector2mem_buf_source_ready = sata_sector2mem_converter_sink_ready; assign sata_sector2mem_converter_sink_first = sata_sector2mem_buf_source_first; assign sata_sector2mem_converter_sink_last = sata_sector2mem_buf_source_last; assign sata_sector2mem_converter_sink_payload_data = sata_sector2mem_buf_source_payload_data; assign sata_sector2mem_buf_syncfifo_din = {sata_sector2mem_buf_fifo_in_last, sata_sector2mem_buf_fifo_in_first, sata_sector2mem_buf_fifo_in_payload_data}; assign {sata_sector2mem_buf_fifo_out_last, sata_sector2mem_buf_fifo_out_first, sata_sector2mem_buf_fifo_out_payload_data} = sata_sector2mem_buf_syncfifo_dout; assign sata_sector2mem_buf_sink_ready = sata_sector2mem_buf_syncfifo_writable; assign sata_sector2mem_buf_syncfifo_we = sata_sector2mem_buf_sink_valid; assign sata_sector2mem_buf_fifo_in_first = sata_sector2mem_buf_sink_first; assign sata_sector2mem_buf_fifo_in_last = sata_sector2mem_buf_sink_last; assign sata_sector2mem_buf_fifo_in_payload_data = sata_sector2mem_buf_sink_payload_data; assign sata_sector2mem_buf_source_valid = sata_sector2mem_buf_syncfifo_readable; assign sata_sector2mem_buf_source_first = sata_sector2mem_buf_fifo_out_first; assign sata_sector2mem_buf_source_last = sata_sector2mem_buf_fifo_out_last; assign sata_sector2mem_buf_source_payload_data = sata_sector2mem_buf_fifo_out_payload_data; assign sata_sector2mem_buf_syncfifo_re = sata_sector2mem_buf_source_ready; always @(*) begin sata_sector2mem_buf_wrport_adr <= 7'd0; if (sata_sector2mem_buf_replace) begin sata_sector2mem_buf_wrport_adr <= (sata_sector2mem_buf_produce - 1'd1); end else begin sata_sector2mem_buf_wrport_adr <= sata_sector2mem_buf_produce; end end assign sata_sector2mem_buf_wrport_dat_w = sata_sector2mem_buf_syncfifo_din; assign sata_sector2mem_buf_wrport_we = (sata_sector2mem_buf_syncfifo_we & (sata_sector2mem_buf_syncfifo_writable | sata_sector2mem_buf_replace)); assign sata_sector2mem_buf_do_read = (sata_sector2mem_buf_syncfifo_readable & sata_sector2mem_buf_syncfifo_re); assign sata_sector2mem_buf_rdport_adr = sata_sector2mem_buf_consume; assign sata_sector2mem_buf_syncfifo_dout = sata_sector2mem_buf_rdport_dat_r; assign sata_sector2mem_buf_syncfifo_writable = (sata_sector2mem_buf_level != 8'd128); assign sata_sector2mem_buf_syncfifo_readable = (sata_sector2mem_buf_level != 1'd0); assign sata_sector2mem_source_source_valid = sata_sector2mem_converter_source_valid; assign sata_sector2mem_converter_source_ready = sata_sector2mem_source_source_ready; assign sata_sector2mem_source_source_first = sata_sector2mem_converter_source_first; assign sata_sector2mem_source_source_last = sata_sector2mem_converter_source_last; assign sata_sector2mem_source_source_payload_data = sata_sector2mem_converter_source_payload_data; assign sata_sector2mem_converter_source_valid = sata_sector2mem_converter_sink_valid; assign sata_sector2mem_converter_sink_ready = sata_sector2mem_converter_source_ready; assign sata_sector2mem_converter_source_first = sata_sector2mem_converter_sink_first; assign sata_sector2mem_converter_source_last = sata_sector2mem_converter_sink_last; assign sata_sector2mem_converter_source_payload_data = sata_sector2mem_converter_sink_payload_data; assign sata_sector2mem_converter_source_payload_valid_token_count = 1'd1; assign interface0_bus_stb = sata_sector2mem_dma_sink_valid; assign interface0_bus_cyc = sata_sector2mem_dma_sink_valid; assign interface0_bus_we = 1'd1; assign interface0_bus_sel = 4'd15; assign interface0_bus_adr = sata_sector2mem_dma_sink_payload_address; assign interface0_bus_dat_w = {sata_sector2mem_dma_sink_payload_data[7:0], sata_sector2mem_dma_sink_payload_data[15:8], sata_sector2mem_dma_sink_payload_data[23:16], sata_sector2mem_dma_sink_payload_data[31:24]}; assign sata_sector2mem_dma_sink_ready = interface0_bus_ack; always @(*) begin sata_sector2mem_error_status_subfragments_next_value1 <= 1'd0; sata_sector2mem_error_status_subfragments_next_value_ce1 <= 1'd0; sata_sector2mem_dma_sink_valid <= 1'd0; sata_sector2mem_dma_sink_last <= 1'd0; sata_sector2mem_dma_sink_payload_address <= 32'd0; sata_sector2mem_dma_sink_payload_data <= 32'd0; litesatauserport0_sink_valid <= 1'd0; litesatauserport0_sink_last <= 1'd0; litesatauserport0_sink_param_read <= 1'd0; litesatauserport0_sink_param_sector <= 48'd0; litesatauserport0_sink_param_count <= 16'd0; sata_sector2mem_done_status <= 1'd0; subfragments_litesatasector2memdma_next_state <= 2'd0; sata_sector2mem_count_subfragments_next_value0 <= 7'd0; sata_sector2mem_source_source_ready <= 1'd0; sata_sector2mem_count_subfragments_next_value_ce0 <= 1'd0; subfragments_litesatasector2memdma_next_state <= subfragments_litesatasector2memdma_state; case (subfragments_litesatasector2memdma_state) 1'd1: begin litesatauserport0_sink_valid <= 1'd1; litesatauserport0_sink_last <= 1'd1; litesatauserport0_sink_param_read <= 1'd1; litesatauserport0_sink_param_sector <= sata_sector2mem_sector_storage; litesatauserport0_sink_param_count <= 1'd1; if (litesatauserport0_sink_ready) begin subfragments_litesatasector2memdma_next_state <= 2'd2; end end 2'd2: begin sata_sector2mem_dma_sink_valid <= sata_sector2mem_source_source_valid; sata_sector2mem_dma_sink_last <= sata_sector2mem_source_source_last; sata_sector2mem_dma_sink_payload_address <= (sata_sector2mem_base_storage[63:2] + sata_sector2mem_count); sata_sector2mem_dma_sink_payload_data <= {sata_sector2mem_source_source_payload_data[7:0], sata_sector2mem_source_source_payload_data[15:8], sata_sector2mem_source_source_payload_data[23:16], sata_sector2mem_source_source_payload_data[31:24]}; sata_sector2mem_source_source_ready <= sata_sector2mem_dma_sink_ready; if ((sata_sector2mem_dma_sink_valid & sata_sector2mem_dma_sink_ready)) begin sata_sector2mem_count_subfragments_next_value0 <= (sata_sector2mem_count + 1'd1); sata_sector2mem_count_subfragments_next_value_ce0 <= 1'd1; if (sata_sector2mem_dma_sink_last) begin subfragments_litesatasector2memdma_next_state <= 1'd0; end end if ((litesatauserport0_source_valid & litesatauserport0_source_ready)) begin if (litesatauserport0_source_param_failed) begin sata_sector2mem_error_status_subfragments_next_value1 <= 1'd1; sata_sector2mem_error_status_subfragments_next_value_ce1 <= 1'd1; subfragments_litesatasector2memdma_next_state <= 1'd0; end end end default: begin if (sata_sector2mem_start_re) begin sata_sector2mem_count_subfragments_next_value0 <= 1'd0; sata_sector2mem_count_subfragments_next_value_ce0 <= 1'd1; sata_sector2mem_error_status_subfragments_next_value1 <= 1'd0; sata_sector2mem_error_status_subfragments_next_value_ce1 <= 1'd1; subfragments_litesatasector2memdma_next_state <= 1'd1; end else begin sata_sector2mem_done_status <= 1'd1; end sata_sector2mem_source_source_ready <= 1'd1; end endcase end assign sata_mem2sector_buf_sink_valid = sata_mem2sector_dma_source_valid; assign sata_mem2sector_dma_source_ready = sata_mem2sector_buf_sink_ready; assign sata_mem2sector_buf_sink_first = sata_mem2sector_dma_source_first; assign sata_mem2sector_buf_sink_last = sata_mem2sector_dma_source_last; assign sata_mem2sector_buf_sink_payload_data = sata_mem2sector_dma_source_payload_data; assign sata_mem2sector_converter_sink_valid = sata_mem2sector_buf_source_valid; assign sata_mem2sector_buf_source_ready = sata_mem2sector_converter_sink_ready; assign sata_mem2sector_converter_sink_first = sata_mem2sector_buf_source_first; assign sata_mem2sector_converter_sink_last = sata_mem2sector_buf_source_last; assign sata_mem2sector_converter_sink_payload_data = sata_mem2sector_buf_source_payload_data; always @(*) begin subfragments_wishbonedmareader_next_state <= 1'd0; sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value <= 32'd0; sata_mem2sector_dma_source_last <= 1'd0; sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value_ce <= 1'd0; sata_mem2sector_dma_source_payload_data <= 32'd0; interface1_bus_adr <= 32'd0; interface1_bus_sel <= 4'd0; interface1_bus_cyc <= 1'd0; interface1_bus_stb <= 1'd0; sata_mem2sector_dma_sink_ready <= 1'd0; interface1_bus_we <= 1'd0; sata_mem2sector_dma_source_valid <= 1'd0; subfragments_wishbonedmareader_next_state <= subfragments_wishbonedmareader_state; case (subfragments_wishbonedmareader_state) 1'd1: begin sata_mem2sector_dma_source_valid <= 1'd1; sata_mem2sector_dma_source_last <= sata_mem2sector_dma_sink_last; sata_mem2sector_dma_source_payload_data <= sata_mem2sector_dma_data; if (sata_mem2sector_dma_source_ready) begin sata_mem2sector_dma_sink_ready <= 1'd1; subfragments_wishbonedmareader_next_state <= 1'd0; end end default: begin interface1_bus_stb <= sata_mem2sector_dma_sink_valid; interface1_bus_cyc <= sata_mem2sector_dma_sink_valid; interface1_bus_we <= 1'd0; interface1_bus_sel <= 4'd15; interface1_bus_adr <= sata_mem2sector_dma_sink_payload_address; if ((interface1_bus_stb & interface1_bus_ack)) begin sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value <= {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value_ce <= 1'd1; subfragments_wishbonedmareader_next_state <= 1'd1; end end endcase end assign sata_mem2sector_buf_syncfifo_din = {sata_mem2sector_buf_fifo_in_last, sata_mem2sector_buf_fifo_in_first, sata_mem2sector_buf_fifo_in_payload_data}; assign {sata_mem2sector_buf_fifo_out_last, sata_mem2sector_buf_fifo_out_first, sata_mem2sector_buf_fifo_out_payload_data} = sata_mem2sector_buf_syncfifo_dout; assign sata_mem2sector_buf_sink_ready = sata_mem2sector_buf_syncfifo_writable; assign sata_mem2sector_buf_syncfifo_we = sata_mem2sector_buf_sink_valid; assign sata_mem2sector_buf_fifo_in_first = sata_mem2sector_buf_sink_first; assign sata_mem2sector_buf_fifo_in_last = sata_mem2sector_buf_sink_last; assign sata_mem2sector_buf_fifo_in_payload_data = sata_mem2sector_buf_sink_payload_data; assign sata_mem2sector_buf_source_valid = sata_mem2sector_buf_syncfifo_readable; assign sata_mem2sector_buf_source_first = sata_mem2sector_buf_fifo_out_first; assign sata_mem2sector_buf_source_last = sata_mem2sector_buf_fifo_out_last; assign sata_mem2sector_buf_source_payload_data = sata_mem2sector_buf_fifo_out_payload_data; assign sata_mem2sector_buf_syncfifo_re = sata_mem2sector_buf_source_ready; always @(*) begin sata_mem2sector_buf_wrport_adr <= 7'd0; if (sata_mem2sector_buf_replace) begin sata_mem2sector_buf_wrport_adr <= (sata_mem2sector_buf_produce - 1'd1); end else begin sata_mem2sector_buf_wrport_adr <= sata_mem2sector_buf_produce; end end assign sata_mem2sector_buf_wrport_dat_w = sata_mem2sector_buf_syncfifo_din; assign sata_mem2sector_buf_wrport_we = (sata_mem2sector_buf_syncfifo_we & (sata_mem2sector_buf_syncfifo_writable | sata_mem2sector_buf_replace)); assign sata_mem2sector_buf_do_read = (sata_mem2sector_buf_syncfifo_readable & sata_mem2sector_buf_syncfifo_re); assign sata_mem2sector_buf_rdport_adr = sata_mem2sector_buf_consume; assign sata_mem2sector_buf_syncfifo_dout = sata_mem2sector_buf_rdport_dat_r; assign sata_mem2sector_buf_syncfifo_writable = (sata_mem2sector_buf_level != 8'd128); assign sata_mem2sector_buf_syncfifo_readable = (sata_mem2sector_buf_level != 1'd0); assign sata_mem2sector_source_source_valid = sata_mem2sector_converter_source_valid; assign sata_mem2sector_converter_source_ready = sata_mem2sector_source_source_ready; assign sata_mem2sector_source_source_first = sata_mem2sector_converter_source_first; assign sata_mem2sector_source_source_last = sata_mem2sector_converter_source_last; assign sata_mem2sector_source_source_payload_data = sata_mem2sector_converter_source_payload_data; assign sata_mem2sector_converter_source_valid = sata_mem2sector_converter_sink_valid; assign sata_mem2sector_converter_sink_ready = sata_mem2sector_converter_source_ready; assign sata_mem2sector_converter_source_first = sata_mem2sector_converter_sink_first; assign sata_mem2sector_converter_source_last = sata_mem2sector_converter_sink_last; assign sata_mem2sector_converter_source_payload_data = sata_mem2sector_converter_sink_payload_data; assign sata_mem2sector_converter_source_payload_valid_token_count = 1'd1; always @(*) begin litesatauserport1_sink_valid <= 1'd0; litesatauserport1_sink_last <= 1'd0; litesatauserport1_sink_payload_data <= 32'd0; litesatauserport1_sink_param_write <= 1'd0; sata_mem2sector_source_source_ready <= 1'd0; litesatauserport1_sink_param_sector <= 48'd0; litesatauserport1_sink_param_count <= 16'd0; litesatauserport1_source_ready <= 1'd0; sata_mem2sector_done_status <= 1'd0; subfragments_fsm_next_state <= 2'd0; sata_mem2sector_count_subfragments_fsm_next_value0 <= 7'd0; sata_mem2sector_dma_sink_valid <= 1'd0; sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd0; sata_mem2sector_error_status_subfragments_fsm_next_value1 <= 1'd0; sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 <= 1'd0; sata_mem2sector_dma_sink_payload_address <= 32'd0; subfragments_fsm_next_state <= subfragments_fsm_state; case (subfragments_fsm_state) 1'd1: begin sata_mem2sector_dma_sink_valid <= 1'd1; sata_mem2sector_dma_sink_payload_address <= (sata_mem2sector_base_storage[63:2] + sata_mem2sector_count); if ((sata_mem2sector_dma_sink_valid & sata_mem2sector_dma_sink_ready)) begin sata_mem2sector_count_subfragments_fsm_next_value0 <= (sata_mem2sector_count + 1'd1); sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd1; if ((sata_mem2sector_count == 7'd127)) begin sata_mem2sector_count_subfragments_fsm_next_value0 <= 1'd0; sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd1; subfragments_fsm_next_state <= 2'd2; end end end 2'd2: begin litesatauserport1_sink_valid <= 1'd1; litesatauserport1_sink_last <= (sata_mem2sector_count == 7'd127); litesatauserport1_sink_param_write <= 1'd1; litesatauserport1_sink_param_sector <= sata_mem2sector_sector_storage; litesatauserport1_sink_param_count <= 1'd1; litesatauserport1_sink_payload_data <= {sata_mem2sector_source_source_payload_data[7:0], sata_mem2sector_source_source_payload_data[15:8], sata_mem2sector_source_source_payload_data[23:16], sata_mem2sector_source_source_payload_data[31:24]}; if (litesatauserport1_sink_ready) begin sata_mem2sector_source_source_ready <= 1'd1; sata_mem2sector_count_subfragments_fsm_next_value0 <= (sata_mem2sector_count + 1'd1); sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd1; if (litesatauserport1_sink_last) begin subfragments_fsm_next_state <= 2'd3; end end litesatauserport1_source_ready <= 1'd1; if ((litesatauserport1_source_valid & litesatauserport1_source_ready)) begin if (litesatauserport1_source_param_failed) begin sata_mem2sector_error_status_subfragments_fsm_next_value1 <= 1'd1; sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 <= 1'd1; subfragments_fsm_next_state <= 1'd0; end end end 2'd3: begin litesatauserport1_source_ready <= 1'd1; if (litesatauserport1_source_valid) begin if (litesatauserport1_source_param_failed) begin sata_mem2sector_error_status_subfragments_fsm_next_value1 <= 1'd1; sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 <= 1'd1; end subfragments_fsm_next_state <= 1'd0; end end default: begin if (sata_mem2sector_start_re) begin sata_mem2sector_count_subfragments_fsm_next_value0 <= 1'd0; sata_mem2sector_count_subfragments_fsm_next_value_ce0 <= 1'd1; sata_mem2sector_error_status_subfragments_fsm_next_value1 <= 1'd0; sata_mem2sector_error_status_subfragments_fsm_next_value_ce1 <= 1'd1; subfragments_fsm_next_state <= 1'd1; end else begin sata_mem2sector_done_status <= 1'd1; end sata_mem2sector_source_source_ready <= 1'd1; end endcase end assign wait_1 = (~done); always @(*) begin user_led0 <= 1'd0; user_led1 <= 1'd0; user_led2 <= 1'd0; user_led3 <= 1'd0; user_led4 <= 1'd0; user_led5 <= 1'd0; user_led6 <= 1'd0; user_led7 <= 1'd0; if ((mode == 1'd1)) begin {user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= storage; end else begin {user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= chaser; end end assign done = (count == 1'd0); always @(*) begin basesoc_next_state <= 2'd0; basesoc_basesoc_dat_w_basesoc_next_value0 <= 32'd0; basesoc_basesoc_dat_w_basesoc_next_value_ce0 <= 1'd0; basesoc_basesoc_wishbone_dat_r <= 32'd0; basesoc_basesoc_adr_basesoc_next_value1 <= 14'd0; basesoc_basesoc_adr_basesoc_next_value_ce1 <= 1'd0; basesoc_basesoc_we_basesoc_next_value2 <= 1'd0; basesoc_basesoc_we_basesoc_next_value_ce2 <= 1'd0; basesoc_basesoc_wishbone_ack <= 1'd0; basesoc_next_state <= basesoc_state; case (basesoc_state) 1'd1: begin basesoc_basesoc_adr_basesoc_next_value1 <= 1'd0; basesoc_basesoc_adr_basesoc_next_value_ce1 <= 1'd1; basesoc_basesoc_we_basesoc_next_value2 <= 1'd0; basesoc_basesoc_we_basesoc_next_value_ce2 <= 1'd1; basesoc_next_state <= 2'd2; end 2'd2: begin basesoc_basesoc_wishbone_ack <= 1'd1; basesoc_basesoc_wishbone_dat_r <= basesoc_basesoc_dat_r; basesoc_next_state <= 1'd0; end default: begin basesoc_basesoc_dat_w_basesoc_next_value0 <= basesoc_basesoc_wishbone_dat_w; basesoc_basesoc_dat_w_basesoc_next_value_ce0 <= 1'd1; if ((basesoc_basesoc_wishbone_cyc & basesoc_basesoc_wishbone_stb)) begin basesoc_basesoc_adr_basesoc_next_value1 <= basesoc_basesoc_wishbone_adr; basesoc_basesoc_adr_basesoc_next_value_ce1 <= 1'd1; basesoc_basesoc_we_basesoc_next_value2 <= (basesoc_basesoc_wishbone_we & (basesoc_basesoc_wishbone_sel != 1'd0)); basesoc_basesoc_we_basesoc_next_value_ce2 <= 1'd1; basesoc_next_state <= 1'd1; end end endcase end assign basesoc_shared_adr = rhs_array_muxed36; assign basesoc_shared_dat_w = rhs_array_muxed37; assign basesoc_shared_sel = rhs_array_muxed38; assign basesoc_shared_cyc = rhs_array_muxed39; assign basesoc_shared_stb = rhs_array_muxed40; assign basesoc_shared_we = rhs_array_muxed41; assign basesoc_shared_cti = rhs_array_muxed42; assign basesoc_shared_bte = rhs_array_muxed43; assign cpu_ibus_dat_r = basesoc_shared_dat_r; assign cpu_dbus_dat_r = basesoc_shared_dat_r; assign interface0_bus_dat_r = basesoc_shared_dat_r; assign interface1_bus_dat_r = basesoc_shared_dat_r; assign cpu_ibus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd0)); assign cpu_dbus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd1)); assign interface0_bus_ack = (basesoc_shared_ack & (basesoc_grant == 2'd2)); assign interface1_bus_ack = (basesoc_shared_ack & (basesoc_grant == 2'd3)); assign cpu_ibus_err = (basesoc_shared_err & (basesoc_grant == 1'd0)); assign cpu_dbus_err = (basesoc_shared_err & (basesoc_grant == 1'd1)); assign interface0_bus_err = (basesoc_shared_err & (basesoc_grant == 2'd2)); assign interface1_bus_err = (basesoc_shared_err & (basesoc_grant == 2'd3)); assign basesoc_request = {interface1_bus_cyc, interface0_bus_cyc, cpu_dbus_cyc, cpu_ibus_cyc}; always @(*) begin basesoc_slave_sel <= 4'd0; basesoc_slave_sel[0] <= (basesoc_shared_adr[29:14] == 1'd0); basesoc_slave_sel[1] <= (basesoc_shared_adr[29:11] == 12'd2048); basesoc_slave_sel[2] <= (basesoc_shared_adr[29:26] == 3'd4); basesoc_slave_sel[3] <= (basesoc_shared_adr[29:14] == 16'd33280); end assign basesoc_ram_bus_adr = basesoc_shared_adr; assign basesoc_ram_bus_dat_w = basesoc_shared_dat_w; assign basesoc_ram_bus_sel = basesoc_shared_sel; assign basesoc_ram_bus_stb = basesoc_shared_stb; assign basesoc_ram_bus_we = basesoc_shared_we; assign basesoc_ram_bus_cti = basesoc_shared_cti; assign basesoc_ram_bus_bte = basesoc_shared_bte; assign ram_bus_ram_bus_adr = basesoc_shared_adr; assign ram_bus_ram_bus_dat_w = basesoc_shared_dat_w; assign ram_bus_ram_bus_sel = basesoc_shared_sel; assign ram_bus_ram_bus_stb = basesoc_shared_stb; assign ram_bus_ram_bus_we = basesoc_shared_we; assign ram_bus_ram_bus_cti = basesoc_shared_cti; assign ram_bus_ram_bus_bte = basesoc_shared_bte; assign wb_sdram_adr = basesoc_shared_adr; assign wb_sdram_dat_w = basesoc_shared_dat_w; assign wb_sdram_sel = basesoc_shared_sel; assign wb_sdram_stb = basesoc_shared_stb; assign wb_sdram_we = basesoc_shared_we; assign wb_sdram_cti = basesoc_shared_cti; assign wb_sdram_bte = basesoc_shared_bte; assign basesoc_basesoc_wishbone_adr = basesoc_shared_adr; assign basesoc_basesoc_wishbone_dat_w = basesoc_shared_dat_w; assign basesoc_basesoc_wishbone_sel = basesoc_shared_sel; assign basesoc_basesoc_wishbone_stb = basesoc_shared_stb; assign basesoc_basesoc_wishbone_we = basesoc_shared_we; assign basesoc_basesoc_wishbone_cti = basesoc_shared_cti; assign basesoc_basesoc_wishbone_bte = basesoc_shared_bte; assign basesoc_ram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[0]); assign ram_bus_ram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[1]); assign wb_sdram_cyc = (basesoc_shared_cyc & basesoc_slave_sel[2]); assign basesoc_basesoc_wishbone_cyc = (basesoc_shared_cyc & basesoc_slave_sel[3]); assign basesoc_shared_err = (((basesoc_ram_bus_err | ram_bus_ram_bus_err) | wb_sdram_err) | basesoc_basesoc_wishbone_err); assign basesoc_wait = ((basesoc_shared_stb & basesoc_shared_cyc) & (~basesoc_shared_ack)); always @(*) begin basesoc_error <= 1'd0; basesoc_shared_dat_r <= 32'd0; basesoc_shared_ack <= 1'd0; basesoc_shared_ack <= (((basesoc_ram_bus_ack | ram_bus_ram_bus_ack) | wb_sdram_ack) | basesoc_basesoc_wishbone_ack); basesoc_shared_dat_r <= (((({32{basesoc_slave_sel_r[0]}} & basesoc_ram_bus_dat_r) | ({32{basesoc_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{basesoc_slave_sel_r[2]}} & wb_sdram_dat_r)) | ({32{basesoc_slave_sel_r[3]}} & basesoc_basesoc_wishbone_dat_r)); if (basesoc_done) begin basesoc_shared_dat_r <= 32'd4294967295; basesoc_shared_ack <= 1'd1; basesoc_error <= 1'd1; end end assign basesoc_done = (basesoc_count == 1'd0); assign basesoc_csr_bankarray_csrbank0_sel = (basesoc_csr_bankarray_interface0_bank_bus_adr[13:9] == 1'd0); assign basesoc_csr_bankarray_csrbank0_reset0_r = basesoc_csr_bankarray_interface0_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank0_reset0_re = ((basesoc_csr_bankarray_csrbank0_sel & basesoc_csr_bankarray_interface0_bank_bus_we) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank0_reset0_we = ((basesoc_csr_bankarray_csrbank0_sel & (~basesoc_csr_bankarray_interface0_bank_bus_we)) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank0_scratch0_r = basesoc_csr_bankarray_interface0_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank0_scratch0_re = ((basesoc_csr_bankarray_csrbank0_sel & basesoc_csr_bankarray_interface0_bank_bus_we) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank0_scratch0_we = ((basesoc_csr_bankarray_csrbank0_sel & (~basesoc_csr_bankarray_interface0_bank_bus_we)) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank0_bus_errors_r = basesoc_csr_bankarray_interface0_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank0_bus_errors_re = ((basesoc_csr_bankarray_csrbank0_sel & basesoc_csr_bankarray_interface0_bank_bus_we) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank0_bus_errors_we = ((basesoc_csr_bankarray_csrbank0_sel & (~basesoc_csr_bankarray_interface0_bank_bus_we)) & (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank0_reset0_w = soccontroller_reset_storage; assign basesoc_csr_bankarray_csrbank0_scratch0_w = soccontroller_scratch_storage[31:0]; assign basesoc_csr_bankarray_csrbank0_bus_errors_w = soccontroller_bus_errors_status[31:0]; assign soccontroller_bus_errors_we = basesoc_csr_bankarray_csrbank0_bus_errors_we; assign basesoc_csr_bankarray_csrbank1_sel = (basesoc_csr_bankarray_interface1_bank_bus_adr[13:9] == 3'd6); assign basesoc_csr_bankarray_csrbank1_rst0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank1_rst0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank1_rst0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[4:0]; assign basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank1_wlevel_en0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank1_wlevel_en0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank1_wlevel_en0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd2)); assign a7ddrphy_wlevel_strobe_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; assign a7ddrphy_wlevel_strobe_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd3)); assign a7ddrphy_wlevel_strobe_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd3)); assign basesoc_csr_bankarray_csrbank1_dly_sel0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[1:0]; assign basesoc_csr_bankarray_csrbank1_dly_sel0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd4)); assign basesoc_csr_bankarray_csrbank1_dly_sel0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd4)); assign a7ddrphy_rdly_dq_rst_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; assign a7ddrphy_rdly_dq_rst_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd5)); assign a7ddrphy_rdly_dq_rst_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd5)); assign a7ddrphy_rdly_dq_inc_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; assign a7ddrphy_rdly_dq_inc_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd6)); assign a7ddrphy_rdly_dq_inc_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd6)); assign a7ddrphy_rdly_dq_bitslip_rst_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; assign a7ddrphy_rdly_dq_bitslip_rst_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; assign a7ddrphy_rdly_dq_bitslip_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd8)); assign a7ddrphy_wdly_dq_bitslip_rst_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; assign a7ddrphy_wdly_dq_bitslip_rst_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd9)); assign a7ddrphy_wdly_dq_bitslip_rst_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd9)); assign a7ddrphy_wdly_dq_bitslip_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[0]; assign a7ddrphy_wdly_dq_bitslip_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd10)); assign a7ddrphy_wdly_dq_bitslip_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd10)); assign basesoc_csr_bankarray_csrbank1_rdphase0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[1:0]; assign basesoc_csr_bankarray_csrbank1_rdphase0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd11)); assign basesoc_csr_bankarray_csrbank1_rdphase0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd11)); assign basesoc_csr_bankarray_csrbank1_wrphase0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[1:0]; assign basesoc_csr_bankarray_csrbank1_wrphase0_re = ((basesoc_csr_bankarray_csrbank1_sel & basesoc_csr_bankarray_interface1_bank_bus_we) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd12)); assign basesoc_csr_bankarray_csrbank1_wrphase0_we = ((basesoc_csr_bankarray_csrbank1_sel & (~basesoc_csr_bankarray_interface1_bank_bus_we)) & (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd12)); assign basesoc_csr_bankarray_csrbank1_rst0_w = a7ddrphy_rst_storage; assign basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign basesoc_csr_bankarray_csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign basesoc_csr_bankarray_csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; assign basesoc_csr_bankarray_csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0]; assign basesoc_csr_bankarray_csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; assign basesoc_csr_bankarray_sel = (basesoc_csr_bankarray_sram_bus_adr[13:9] == 2'd2); always @(*) begin basesoc_csr_bankarray_sram_bus_dat_r <= 32'd0; if (basesoc_csr_bankarray_sel_r) begin basesoc_csr_bankarray_sram_bus_dat_r <= basesoc_csr_bankarray_dat_r; end end assign basesoc_csr_bankarray_adr = basesoc_csr_bankarray_sram_bus_adr[5:0]; assign basesoc_csr_bankarray_csrbank2_sel = (basesoc_csr_bankarray_interface2_bank_bus_adr[13:9] == 4'd11); assign basesoc_csr_bankarray_csrbank2_out0_r = basesoc_csr_bankarray_interface2_bank_bus_dat_w[7:0]; assign basesoc_csr_bankarray_csrbank2_out0_re = ((basesoc_csr_bankarray_csrbank2_sel & basesoc_csr_bankarray_interface2_bank_bus_we) & (basesoc_csr_bankarray_interface2_bank_bus_adr[0] == 1'd0)); assign basesoc_csr_bankarray_csrbank2_out0_we = ((basesoc_csr_bankarray_csrbank2_sel & (~basesoc_csr_bankarray_interface2_bank_bus_we)) & (basesoc_csr_bankarray_interface2_bank_bus_adr[0] == 1'd0)); assign basesoc_csr_bankarray_csrbank2_out0_w = storage[7:0]; assign basesoc_csr_bankarray_csrbank3_sel = (basesoc_csr_bankarray_interface3_bank_bus_adr[13:9] == 4'd10); assign basesoc_csr_bankarray_csrbank3_sector1_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[15:0]; assign basesoc_csr_bankarray_csrbank3_sector1_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank3_sector1_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank3_sector0_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank3_sector0_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank3_sector0_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank3_base1_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank3_base1_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank3_base1_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank3_base0_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank3_base0_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 2'd3)); assign basesoc_csr_bankarray_csrbank3_base0_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 2'd3)); assign sata_mem2sector_start_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[0]; assign sata_mem2sector_start_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd4)); assign sata_mem2sector_start_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd4)); assign basesoc_csr_bankarray_csrbank3_done_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank3_done_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank3_done_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank3_error_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank3_error_re = ((basesoc_csr_bankarray_csrbank3_sel & basesoc_csr_bankarray_interface3_bank_bus_we) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank3_error_we = ((basesoc_csr_bankarray_csrbank3_sel & (~basesoc_csr_bankarray_interface3_bank_bus_we)) & (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank3_sector1_w = sata_mem2sector_sector_storage[47:32]; assign basesoc_csr_bankarray_csrbank3_sector0_w = sata_mem2sector_sector_storage[31:0]; assign basesoc_csr_bankarray_csrbank3_base1_w = sata_mem2sector_base_storage[63:32]; assign basesoc_csr_bankarray_csrbank3_base0_w = sata_mem2sector_base_storage[31:0]; assign basesoc_csr_bankarray_csrbank3_done_w = sata_mem2sector_done_status; assign sata_mem2sector_done_we = basesoc_csr_bankarray_csrbank3_done_we; assign basesoc_csr_bankarray_csrbank3_error_w = sata_mem2sector_error_status; assign sata_mem2sector_error_we = basesoc_csr_bankarray_csrbank3_error_we; assign basesoc_csr_bankarray_csrbank4_sel = (basesoc_csr_bankarray_interface4_bank_bus_adr[13:9] == 4'd8); assign basesoc_csr_bankarray_csrbank4_enable0_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank4_enable0_re = ((basesoc_csr_bankarray_csrbank4_sel & basesoc_csr_bankarray_interface4_bank_bus_we) & (basesoc_csr_bankarray_interface4_bank_bus_adr[0] == 1'd0)); assign basesoc_csr_bankarray_csrbank4_enable0_we = ((basesoc_csr_bankarray_csrbank4_sel & (~basesoc_csr_bankarray_interface4_bank_bus_we)) & (basesoc_csr_bankarray_interface4_bank_bus_adr[0] == 1'd0)); assign basesoc_csr_bankarray_csrbank4_status_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[3:0]; assign basesoc_csr_bankarray_csrbank4_status_re = ((basesoc_csr_bankarray_csrbank4_sel & basesoc_csr_bankarray_interface4_bank_bus_we) & (basesoc_csr_bankarray_interface4_bank_bus_adr[0] == 1'd1)); assign basesoc_csr_bankarray_csrbank4_status_we = ((basesoc_csr_bankarray_csrbank4_sel & (~basesoc_csr_bankarray_interface4_bank_bus_we)) & (basesoc_csr_bankarray_interface4_bank_bus_adr[0] == 1'd1)); assign basesoc_csr_bankarray_csrbank4_enable0_w = litesataphy_enable_storage; always @(*) begin litesataphy_status_status <= 4'd0; litesataphy_status_status[0] <= litesataphy_ready; litesataphy_status_status[1] <= litesataphy_tx_ready; litesataphy_status_status[2] <= litesataphy_rx_ready; litesataphy_status_status[3] <= litesataphy_ctrl_ready; end assign basesoc_csr_bankarray_csrbank4_status_w = litesataphy_status_status[3:0]; assign litesataphy_status_we = basesoc_csr_bankarray_csrbank4_status_we; assign basesoc_csr_bankarray_csrbank5_sel = (basesoc_csr_bankarray_interface5_bank_bus_adr[13:9] == 4'd9); assign basesoc_csr_bankarray_csrbank5_sector1_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[15:0]; assign basesoc_csr_bankarray_csrbank5_sector1_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank5_sector1_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank5_sector0_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank5_sector0_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank5_sector0_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank5_base1_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank5_base1_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank5_base1_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank5_base0_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank5_base0_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 2'd3)); assign basesoc_csr_bankarray_csrbank5_base0_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 2'd3)); assign sata_sector2mem_start_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[0]; assign sata_sector2mem_start_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd4)); assign sata_sector2mem_start_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd4)); assign basesoc_csr_bankarray_csrbank5_done_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank5_done_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank5_done_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank5_error_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank5_error_re = ((basesoc_csr_bankarray_csrbank5_sel & basesoc_csr_bankarray_interface5_bank_bus_we) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank5_error_we = ((basesoc_csr_bankarray_csrbank5_sel & (~basesoc_csr_bankarray_interface5_bank_bus_we)) & (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank5_sector1_w = sata_sector2mem_sector_storage[47:32]; assign basesoc_csr_bankarray_csrbank5_sector0_w = sata_sector2mem_sector_storage[31:0]; assign basesoc_csr_bankarray_csrbank5_base1_w = sata_sector2mem_base_storage[63:32]; assign basesoc_csr_bankarray_csrbank5_base0_w = sata_sector2mem_base_storage[31:0]; assign basesoc_csr_bankarray_csrbank5_done_w = sata_sector2mem_done_status; assign sata_sector2mem_done_we = basesoc_csr_bankarray_csrbank5_done_we; assign basesoc_csr_bankarray_csrbank5_error_w = sata_sector2mem_error_status; assign sata_sector2mem_error_we = basesoc_csr_bankarray_csrbank5_error_we; assign basesoc_csr_bankarray_csrbank6_sel = (basesoc_csr_bankarray_interface6_bank_bus_adr[13:9] == 3'd7); assign basesoc_csr_bankarray_csrbank6_dfii_control0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[3:0]; assign basesoc_csr_bankarray_csrbank6_dfii_control0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank6_dfii_control0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[5:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 1'd1)); assign sdram_phaseinjector0_command_issue_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; assign sdram_phaseinjector0_command_issue_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 2'd2)); assign sdram_phaseinjector0_command_issue_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[13:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 2'd3)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 2'd3)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[2:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd4)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd4)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[5:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd7)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 3'd7)); assign sdram_phaseinjector1_command_issue_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; assign sdram_phaseinjector1_command_issue_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd8)); assign sdram_phaseinjector1_command_issue_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd8)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[13:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd9)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd9)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[2:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd10)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd10)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd11)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd11)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd12)); assign basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd12)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[5:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd13)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd13)); assign sdram_phaseinjector2_command_issue_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; assign sdram_phaseinjector2_command_issue_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd14)); assign sdram_phaseinjector2_command_issue_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd14)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[13:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd15)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 4'd15)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[2:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd16)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd16)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd17)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd17)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd18)); assign basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd18)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[5:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd19)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd19)); assign sdram_phaseinjector3_command_issue_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; assign sdram_phaseinjector3_command_issue_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd20)); assign sdram_phaseinjector3_command_issue_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd20)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[13:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd21)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd21)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[2:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd22)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd22)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd23)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd23)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_re = ((basesoc_csr_bankarray_csrbank6_sel & basesoc_csr_bankarray_interface6_bank_bus_we) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd24)); assign basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_we = ((basesoc_csr_bankarray_csrbank6_sel & (~basesoc_csr_bankarray_interface6_bank_bus_we)) & (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0] == 5'd24)); assign sdram_sel = sdram_storage[0]; assign sdram_cke = sdram_storage[1]; assign sdram_odt = sdram_storage[2]; assign sdram_reset_n = sdram_storage[3]; assign basesoc_csr_bankarray_csrbank6_dfii_control0_w = sdram_storage[3:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_w = sdram_phaseinjector0_command_storage[5:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_w = sdram_phaseinjector0_address_storage[13:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_w = sdram_phaseinjector0_baddress_storage[2:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_w = sdram_phaseinjector0_wrdata_storage[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_w = sdram_phaseinjector0_rddata_status[31:0]; assign sdram_phaseinjector0_rddata_we = basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_we; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_w = sdram_phaseinjector1_command_storage[5:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_w = sdram_phaseinjector1_address_storage[13:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_w = sdram_phaseinjector1_baddress_storage[2:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_w = sdram_phaseinjector1_wrdata_storage[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_w = sdram_phaseinjector1_rddata_status[31:0]; assign sdram_phaseinjector1_rddata_we = basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_we; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_w = sdram_phaseinjector2_command_storage[5:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_w = sdram_phaseinjector2_address_storage[13:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_w = sdram_phaseinjector2_baddress_storage[2:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_w = sdram_phaseinjector2_wrdata_storage[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_w = sdram_phaseinjector2_rddata_status[31:0]; assign sdram_phaseinjector2_rddata_we = basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_we; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_w = sdram_phaseinjector3_command_storage[5:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_w = sdram_phaseinjector3_address_storage[13:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_w = sdram_phaseinjector3_baddress_storage[2:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_w = sdram_phaseinjector3_wrdata_storage[31:0]; assign basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_w = sdram_phaseinjector3_rddata_status[31:0]; assign sdram_phaseinjector3_rddata_we = basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_we; assign basesoc_csr_bankarray_csrbank7_sel = (basesoc_csr_bankarray_interface7_bank_bus_adr[13:9] == 3'd5); assign basesoc_csr_bankarray_csrbank7_load0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank7_load0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank7_load0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank7_reload0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank7_reload0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank7_reload0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank7_en0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank7_en0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank7_en0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank7_update_value0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank7_update_value0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 2'd3)); assign basesoc_csr_bankarray_csrbank7_update_value0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 2'd3)); assign basesoc_csr_bankarray_csrbank7_value_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank7_value_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd4)); assign basesoc_csr_bankarray_csrbank7_value_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd4)); assign basesoc_csr_bankarray_csrbank7_ev_status_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank7_ev_status_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank7_ev_status_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank7_ev_pending_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank7_ev_pending_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank7_ev_pending_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank7_ev_enable0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank7_ev_enable0_re = ((basesoc_csr_bankarray_csrbank7_sel & basesoc_csr_bankarray_interface7_bank_bus_we) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd7)); assign basesoc_csr_bankarray_csrbank7_ev_enable0_we = ((basesoc_csr_bankarray_csrbank7_sel & (~basesoc_csr_bankarray_interface7_bank_bus_we)) & (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0] == 3'd7)); assign basesoc_csr_bankarray_csrbank7_load0_w = timer_load_storage[31:0]; assign basesoc_csr_bankarray_csrbank7_reload0_w = timer_reload_storage[31:0]; assign basesoc_csr_bankarray_csrbank7_en0_w = timer_en_storage; assign basesoc_csr_bankarray_csrbank7_update_value0_w = timer_update_value_storage; assign basesoc_csr_bankarray_csrbank7_value_w = timer_value_status[31:0]; assign timer_value_we = basesoc_csr_bankarray_csrbank7_value_we; assign timer_status_status = timer_zero0; assign basesoc_csr_bankarray_csrbank7_ev_status_w = timer_status_status; assign timer_status_we = basesoc_csr_bankarray_csrbank7_ev_status_we; assign timer_pending_status = timer_zero1; assign basesoc_csr_bankarray_csrbank7_ev_pending_w = timer_pending_status; assign timer_pending_we = basesoc_csr_bankarray_csrbank7_ev_pending_we; assign timer_zero2 = timer_enable_storage; assign basesoc_csr_bankarray_csrbank7_ev_enable0_w = timer_enable_storage; assign basesoc_csr_bankarray_csrbank8_sel = (basesoc_csr_bankarray_interface8_bank_bus_adr[13:9] == 3'd4); assign uart_rxtx_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[7:0]; assign uart_rxtx_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 1'd0)); assign uart_rxtx_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 1'd0)); assign basesoc_csr_bankarray_csrbank8_txfull_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank8_txfull_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank8_txfull_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 1'd1)); assign basesoc_csr_bankarray_csrbank8_rxempty_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank8_rxempty_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank8_rxempty_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 2'd2)); assign basesoc_csr_bankarray_csrbank8_ev_status_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[1:0]; assign basesoc_csr_bankarray_csrbank8_ev_status_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 2'd3)); assign basesoc_csr_bankarray_csrbank8_ev_status_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 2'd3)); assign basesoc_csr_bankarray_csrbank8_ev_pending_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[1:0]; assign basesoc_csr_bankarray_csrbank8_ev_pending_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd4)); assign basesoc_csr_bankarray_csrbank8_ev_pending_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd4)); assign basesoc_csr_bankarray_csrbank8_ev_enable0_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[1:0]; assign basesoc_csr_bankarray_csrbank8_ev_enable0_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank8_ev_enable0_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd5)); assign basesoc_csr_bankarray_csrbank8_txempty_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank8_txempty_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank8_txempty_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd6)); assign basesoc_csr_bankarray_csrbank8_rxfull_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; assign basesoc_csr_bankarray_csrbank8_rxfull_re = ((basesoc_csr_bankarray_csrbank8_sel & basesoc_csr_bankarray_interface8_bank_bus_we) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd7)); assign basesoc_csr_bankarray_csrbank8_rxfull_we = ((basesoc_csr_bankarray_csrbank8_sel & (~basesoc_csr_bankarray_interface8_bank_bus_we)) & (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0] == 3'd7)); assign basesoc_csr_bankarray_csrbank8_txfull_w = uart_txfull_status; assign uart_txfull_we = basesoc_csr_bankarray_csrbank8_txfull_we; assign basesoc_csr_bankarray_csrbank8_rxempty_w = uart_rxempty_status; assign uart_rxempty_we = basesoc_csr_bankarray_csrbank8_rxempty_we; always @(*) begin uart_status_status <= 2'd0; uart_status_status[0] <= uart_tx0; uart_status_status[1] <= uart_rx0; end assign basesoc_csr_bankarray_csrbank8_ev_status_w = uart_status_status[1:0]; assign uart_status_we = basesoc_csr_bankarray_csrbank8_ev_status_we; always @(*) begin uart_pending_status <= 2'd0; uart_pending_status[0] <= uart_tx1; uart_pending_status[1] <= uart_rx1; end assign basesoc_csr_bankarray_csrbank8_ev_pending_w = uart_pending_status[1:0]; assign uart_pending_we = basesoc_csr_bankarray_csrbank8_ev_pending_we; assign uart_tx2 = uart_enable_storage[0]; assign uart_rx2 = uart_enable_storage[1]; assign basesoc_csr_bankarray_csrbank8_ev_enable0_w = uart_enable_storage[1:0]; assign basesoc_csr_bankarray_csrbank8_txempty_w = uart_txempty_status; assign uart_txempty_we = basesoc_csr_bankarray_csrbank8_txempty_we; assign basesoc_csr_bankarray_csrbank8_rxfull_w = uart_rxfull_status; assign uart_rxfull_we = basesoc_csr_bankarray_csrbank8_rxfull_we; assign basesoc_csr_bankarray_csrbank9_sel = (basesoc_csr_bankarray_interface9_bank_bus_adr[13:9] == 2'd3); assign basesoc_csr_bankarray_csrbank9_tuning_word0_r = basesoc_csr_bankarray_interface9_bank_bus_dat_w[31:0]; assign basesoc_csr_bankarray_csrbank9_tuning_word0_re = ((basesoc_csr_bankarray_csrbank9_sel & basesoc_csr_bankarray_interface9_bank_bus_we) & (basesoc_csr_bankarray_interface9_bank_bus_adr[0] == 1'd0)); assign basesoc_csr_bankarray_csrbank9_tuning_word0_we = ((basesoc_csr_bankarray_csrbank9_sel & (~basesoc_csr_bankarray_interface9_bank_bus_we)) & (basesoc_csr_bankarray_interface9_bank_bus_adr[0] == 1'd0)); assign basesoc_csr_bankarray_csrbank9_tuning_word0_w = uart_phy_storage[31:0]; assign basesoc_csr_interconnect_adr = basesoc_basesoc_adr; assign basesoc_csr_interconnect_we = basesoc_basesoc_we; assign basesoc_csr_interconnect_dat_w = basesoc_basesoc_dat_w; assign basesoc_basesoc_dat_r = basesoc_csr_interconnect_dat_r; assign basesoc_csr_bankarray_interface0_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface1_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface2_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface3_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface4_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface5_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface6_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface7_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface8_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface9_bank_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_sram_bus_adr = basesoc_csr_interconnect_adr; assign basesoc_csr_bankarray_interface0_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface1_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface2_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface3_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface4_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface5_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface6_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface7_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface8_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface9_bank_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_sram_bus_we = basesoc_csr_interconnect_we; assign basesoc_csr_bankarray_interface0_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_interface1_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_interface2_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_interface3_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_interface4_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_interface5_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_interface6_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_interface7_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_interface8_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_interface9_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_bankarray_sram_bus_dat_w = basesoc_csr_interconnect_dat_w; assign basesoc_csr_interconnect_dat_r = ((((((((((basesoc_csr_bankarray_interface0_bank_bus_dat_r | basesoc_csr_bankarray_interface1_bank_bus_dat_r) | basesoc_csr_bankarray_interface2_bank_bus_dat_r) | basesoc_csr_bankarray_interface3_bank_bus_dat_r) | basesoc_csr_bankarray_interface4_bank_bus_dat_r) | basesoc_csr_bankarray_interface5_bank_bus_dat_r) | basesoc_csr_bankarray_interface6_bank_bus_dat_r) | basesoc_csr_bankarray_interface7_bank_bus_dat_r) | basesoc_csr_bankarray_interface8_bank_bus_dat_r) | basesoc_csr_bankarray_interface9_bank_bus_dat_r) | basesoc_csr_bankarray_sram_bus_dat_r); always @(*) begin rhs_array_muxed0 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[0]; end 1'd1: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[1]; end 2'd2: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[2]; end 2'd3: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[3]; end 3'd4: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[4]; end 3'd5: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[5]; end 3'd6: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[6]; end default: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[7]; end endcase end always @(*) begin rhs_array_muxed1 <= 14'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed1 <= sdram_bankmachine0_cmd_payload_a; end 1'd1: begin rhs_array_muxed1 <= sdram_bankmachine1_cmd_payload_a; end 2'd2: begin rhs_array_muxed1 <= sdram_bankmachine2_cmd_payload_a; end 2'd3: begin rhs_array_muxed1 <= sdram_bankmachine3_cmd_payload_a; end 3'd4: begin rhs_array_muxed1 <= sdram_bankmachine4_cmd_payload_a; end 3'd5: begin rhs_array_muxed1 <= sdram_bankmachine5_cmd_payload_a; end 3'd6: begin rhs_array_muxed1 <= sdram_bankmachine6_cmd_payload_a; end default: begin rhs_array_muxed1 <= sdram_bankmachine7_cmd_payload_a; end endcase end always @(*) begin rhs_array_muxed2 <= 3'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed2 <= sdram_bankmachine0_cmd_payload_ba; end 1'd1: begin rhs_array_muxed2 <= sdram_bankmachine1_cmd_payload_ba; end 2'd2: begin rhs_array_muxed2 <= sdram_bankmachine2_cmd_payload_ba; end 2'd3: begin rhs_array_muxed2 <= sdram_bankmachine3_cmd_payload_ba; end 3'd4: begin rhs_array_muxed2 <= sdram_bankmachine4_cmd_payload_ba; end 3'd5: begin rhs_array_muxed2 <= sdram_bankmachine5_cmd_payload_ba; end 3'd6: begin rhs_array_muxed2 <= sdram_bankmachine6_cmd_payload_ba; end default: begin rhs_array_muxed2 <= sdram_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin rhs_array_muxed3 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed3 <= sdram_bankmachine0_cmd_payload_is_read; end 1'd1: begin rhs_array_muxed3 <= sdram_bankmachine1_cmd_payload_is_read; end 2'd2: begin rhs_array_muxed3 <= sdram_bankmachine2_cmd_payload_is_read; end 2'd3: begin rhs_array_muxed3 <= sdram_bankmachine3_cmd_payload_is_read; end 3'd4: begin rhs_array_muxed3 <= sdram_bankmachine4_cmd_payload_is_read; end 3'd5: begin rhs_array_muxed3 <= sdram_bankmachine5_cmd_payload_is_read; end 3'd6: begin rhs_array_muxed3 <= sdram_bankmachine6_cmd_payload_is_read; end default: begin rhs_array_muxed3 <= sdram_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin rhs_array_muxed4 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed4 <= sdram_bankmachine0_cmd_payload_is_write; end 1'd1: begin rhs_array_muxed4 <= sdram_bankmachine1_cmd_payload_is_write; end 2'd2: begin rhs_array_muxed4 <= sdram_bankmachine2_cmd_payload_is_write; end 2'd3: begin rhs_array_muxed4 <= sdram_bankmachine3_cmd_payload_is_write; end 3'd4: begin rhs_array_muxed4 <= sdram_bankmachine4_cmd_payload_is_write; end 3'd5: begin rhs_array_muxed4 <= sdram_bankmachine5_cmd_payload_is_write; end 3'd6: begin rhs_array_muxed4 <= sdram_bankmachine6_cmd_payload_is_write; end default: begin rhs_array_muxed4 <= sdram_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin rhs_array_muxed5 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed5 <= sdram_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin rhs_array_muxed5 <= sdram_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin rhs_array_muxed5 <= sdram_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin rhs_array_muxed5 <= sdram_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin rhs_array_muxed5 <= sdram_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin rhs_array_muxed5 <= sdram_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin rhs_array_muxed5 <= sdram_bankmachine6_cmd_payload_is_cmd; end default: begin rhs_array_muxed5 <= sdram_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin t_array_muxed0 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin t_array_muxed0 <= sdram_bankmachine0_cmd_payload_cas; end 1'd1: begin t_array_muxed0 <= sdram_bankmachine1_cmd_payload_cas; end 2'd2: begin t_array_muxed0 <= sdram_bankmachine2_cmd_payload_cas; end 2'd3: begin t_array_muxed0 <= sdram_bankmachine3_cmd_payload_cas; end 3'd4: begin t_array_muxed0 <= sdram_bankmachine4_cmd_payload_cas; end 3'd5: begin t_array_muxed0 <= sdram_bankmachine5_cmd_payload_cas; end 3'd6: begin t_array_muxed0 <= sdram_bankmachine6_cmd_payload_cas; end default: begin t_array_muxed0 <= sdram_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin t_array_muxed1 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin t_array_muxed1 <= sdram_bankmachine0_cmd_payload_ras; end 1'd1: begin t_array_muxed1 <= sdram_bankmachine1_cmd_payload_ras; end 2'd2: begin t_array_muxed1 <= sdram_bankmachine2_cmd_payload_ras; end 2'd3: begin t_array_muxed1 <= sdram_bankmachine3_cmd_payload_ras; end 3'd4: begin t_array_muxed1 <= sdram_bankmachine4_cmd_payload_ras; end 3'd5: begin t_array_muxed1 <= sdram_bankmachine5_cmd_payload_ras; end 3'd6: begin t_array_muxed1 <= sdram_bankmachine6_cmd_payload_ras; end default: begin t_array_muxed1 <= sdram_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin t_array_muxed2 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin t_array_muxed2 <= sdram_bankmachine0_cmd_payload_we; end 1'd1: begin t_array_muxed2 <= sdram_bankmachine1_cmd_payload_we; end 2'd2: begin t_array_muxed2 <= sdram_bankmachine2_cmd_payload_we; end 2'd3: begin t_array_muxed2 <= sdram_bankmachine3_cmd_payload_we; end 3'd4: begin t_array_muxed2 <= sdram_bankmachine4_cmd_payload_we; end 3'd5: begin t_array_muxed2 <= sdram_bankmachine5_cmd_payload_we; end 3'd6: begin t_array_muxed2 <= sdram_bankmachine6_cmd_payload_we; end default: begin t_array_muxed2 <= sdram_bankmachine7_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed6 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed6 <= sdram_choose_req_valids[0]; end 1'd1: begin rhs_array_muxed6 <= sdram_choose_req_valids[1]; end 2'd2: begin rhs_array_muxed6 <= sdram_choose_req_valids[2]; end 2'd3: begin rhs_array_muxed6 <= sdram_choose_req_valids[3]; end 3'd4: begin rhs_array_muxed6 <= sdram_choose_req_valids[4]; end 3'd5: begin rhs_array_muxed6 <= sdram_choose_req_valids[5]; end 3'd6: begin rhs_array_muxed6 <= sdram_choose_req_valids[6]; end default: begin rhs_array_muxed6 <= sdram_choose_req_valids[7]; end endcase end always @(*) begin rhs_array_muxed7 <= 14'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed7 <= sdram_bankmachine0_cmd_payload_a; end 1'd1: begin rhs_array_muxed7 <= sdram_bankmachine1_cmd_payload_a; end 2'd2: begin rhs_array_muxed7 <= sdram_bankmachine2_cmd_payload_a; end 2'd3: begin rhs_array_muxed7 <= sdram_bankmachine3_cmd_payload_a; end 3'd4: begin rhs_array_muxed7 <= sdram_bankmachine4_cmd_payload_a; end 3'd5: begin rhs_array_muxed7 <= sdram_bankmachine5_cmd_payload_a; end 3'd6: begin rhs_array_muxed7 <= sdram_bankmachine6_cmd_payload_a; end default: begin rhs_array_muxed7 <= sdram_bankmachine7_cmd_payload_a; end endcase end always @(*) begin rhs_array_muxed8 <= 3'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed8 <= sdram_bankmachine0_cmd_payload_ba; end 1'd1: begin rhs_array_muxed8 <= sdram_bankmachine1_cmd_payload_ba; end 2'd2: begin rhs_array_muxed8 <= sdram_bankmachine2_cmd_payload_ba; end 2'd3: begin rhs_array_muxed8 <= sdram_bankmachine3_cmd_payload_ba; end 3'd4: begin rhs_array_muxed8 <= sdram_bankmachine4_cmd_payload_ba; end 3'd5: begin rhs_array_muxed8 <= sdram_bankmachine5_cmd_payload_ba; end 3'd6: begin rhs_array_muxed8 <= sdram_bankmachine6_cmd_payload_ba; end default: begin rhs_array_muxed8 <= sdram_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin rhs_array_muxed9 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed9 <= sdram_bankmachine0_cmd_payload_is_read; end 1'd1: begin rhs_array_muxed9 <= sdram_bankmachine1_cmd_payload_is_read; end 2'd2: begin rhs_array_muxed9 <= sdram_bankmachine2_cmd_payload_is_read; end 2'd3: begin rhs_array_muxed9 <= sdram_bankmachine3_cmd_payload_is_read; end 3'd4: begin rhs_array_muxed9 <= sdram_bankmachine4_cmd_payload_is_read; end 3'd5: begin rhs_array_muxed9 <= sdram_bankmachine5_cmd_payload_is_read; end 3'd6: begin rhs_array_muxed9 <= sdram_bankmachine6_cmd_payload_is_read; end default: begin rhs_array_muxed9 <= sdram_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin rhs_array_muxed10 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed10 <= sdram_bankmachine0_cmd_payload_is_write; end 1'd1: begin rhs_array_muxed10 <= sdram_bankmachine1_cmd_payload_is_write; end 2'd2: begin rhs_array_muxed10 <= sdram_bankmachine2_cmd_payload_is_write; end 2'd3: begin rhs_array_muxed10 <= sdram_bankmachine3_cmd_payload_is_write; end 3'd4: begin rhs_array_muxed10 <= sdram_bankmachine4_cmd_payload_is_write; end 3'd5: begin rhs_array_muxed10 <= sdram_bankmachine5_cmd_payload_is_write; end 3'd6: begin rhs_array_muxed10 <= sdram_bankmachine6_cmd_payload_is_write; end default: begin rhs_array_muxed10 <= sdram_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin rhs_array_muxed11 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed11 <= sdram_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin rhs_array_muxed11 <= sdram_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin rhs_array_muxed11 <= sdram_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin rhs_array_muxed11 <= sdram_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin rhs_array_muxed11 <= sdram_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin rhs_array_muxed11 <= sdram_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin rhs_array_muxed11 <= sdram_bankmachine6_cmd_payload_is_cmd; end default: begin rhs_array_muxed11 <= sdram_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin t_array_muxed3 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin t_array_muxed3 <= sdram_bankmachine0_cmd_payload_cas; end 1'd1: begin t_array_muxed3 <= sdram_bankmachine1_cmd_payload_cas; end 2'd2: begin t_array_muxed3 <= sdram_bankmachine2_cmd_payload_cas; end 2'd3: begin t_array_muxed3 <= sdram_bankmachine3_cmd_payload_cas; end 3'd4: begin t_array_muxed3 <= sdram_bankmachine4_cmd_payload_cas; end 3'd5: begin t_array_muxed3 <= sdram_bankmachine5_cmd_payload_cas; end 3'd6: begin t_array_muxed3 <= sdram_bankmachine6_cmd_payload_cas; end default: begin t_array_muxed3 <= sdram_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin t_array_muxed4 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin t_array_muxed4 <= sdram_bankmachine0_cmd_payload_ras; end 1'd1: begin t_array_muxed4 <= sdram_bankmachine1_cmd_payload_ras; end 2'd2: begin t_array_muxed4 <= sdram_bankmachine2_cmd_payload_ras; end 2'd3: begin t_array_muxed4 <= sdram_bankmachine3_cmd_payload_ras; end 3'd4: begin t_array_muxed4 <= sdram_bankmachine4_cmd_payload_ras; end 3'd5: begin t_array_muxed4 <= sdram_bankmachine5_cmd_payload_ras; end 3'd6: begin t_array_muxed4 <= sdram_bankmachine6_cmd_payload_ras; end default: begin t_array_muxed4 <= sdram_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin t_array_muxed5 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin t_array_muxed5 <= sdram_bankmachine0_cmd_payload_we; end 1'd1: begin t_array_muxed5 <= sdram_bankmachine1_cmd_payload_we; end 2'd2: begin t_array_muxed5 <= sdram_bankmachine2_cmd_payload_we; end 2'd3: begin t_array_muxed5 <= sdram_bankmachine3_cmd_payload_we; end 3'd4: begin t_array_muxed5 <= sdram_bankmachine4_cmd_payload_we; end 3'd5: begin t_array_muxed5 <= sdram_bankmachine5_cmd_payload_we; end 3'd6: begin t_array_muxed5 <= sdram_bankmachine6_cmd_payload_we; end default: begin t_array_muxed5 <= sdram_bankmachine7_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed12 <= 21'd0; case (subfragments_roundrobin0_grant) default: begin rhs_array_muxed12 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed13 <= 1'd0; case (subfragments_roundrobin0_grant) default: begin rhs_array_muxed13 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed14 <= 1'd0; case (subfragments_roundrobin0_grant) default: begin rhs_array_muxed14 <= (((port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed15 <= 21'd0; case (subfragments_roundrobin1_grant) default: begin rhs_array_muxed15 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed16 <= 1'd0; case (subfragments_roundrobin1_grant) default: begin rhs_array_muxed16 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed17 <= 1'd0; case (subfragments_roundrobin1_grant) default: begin rhs_array_muxed17 <= (((port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed18 <= 21'd0; case (subfragments_roundrobin2_grant) default: begin rhs_array_muxed18 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed19 <= 1'd0; case (subfragments_roundrobin2_grant) default: begin rhs_array_muxed19 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed20 <= 1'd0; case (subfragments_roundrobin2_grant) default: begin rhs_array_muxed20 <= (((port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed21 <= 21'd0; case (subfragments_roundrobin3_grant) default: begin rhs_array_muxed21 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed22 <= 1'd0; case (subfragments_roundrobin3_grant) default: begin rhs_array_muxed22 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed23 <= 1'd0; case (subfragments_roundrobin3_grant) default: begin rhs_array_muxed23 <= (((port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed24 <= 21'd0; case (subfragments_roundrobin4_grant) default: begin rhs_array_muxed24 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed25 <= 1'd0; case (subfragments_roundrobin4_grant) default: begin rhs_array_muxed25 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed26 <= 1'd0; case (subfragments_roundrobin4_grant) default: begin rhs_array_muxed26 <= (((port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((subfragments_locked4 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed27 <= 21'd0; case (subfragments_roundrobin5_grant) default: begin rhs_array_muxed27 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed28 <= 1'd0; case (subfragments_roundrobin5_grant) default: begin rhs_array_muxed28 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed29 <= 1'd0; case (subfragments_roundrobin5_grant) default: begin rhs_array_muxed29 <= (((port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((subfragments_locked5 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed30 <= 21'd0; case (subfragments_roundrobin6_grant) default: begin rhs_array_muxed30 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed31 <= 1'd0; case (subfragments_roundrobin6_grant) default: begin rhs_array_muxed31 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed32 <= 1'd0; case (subfragments_roundrobin6_grant) default: begin rhs_array_muxed32 <= (((port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((subfragments_locked6 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank7_lock & (subfragments_roundrobin7_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed33 <= 21'd0; case (subfragments_roundrobin7_grant) default: begin rhs_array_muxed33 <= {port_cmd_payload_addr[23:10], port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed34 <= 1'd0; case (subfragments_roundrobin7_grant) default: begin rhs_array_muxed34 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed35 <= 1'd0; case (subfragments_roundrobin7_grant) default: begin rhs_array_muxed35 <= (((port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((subfragments_locked7 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))) | (sdram_interface_bank4_lock & (subfragments_roundrobin4_grant == 1'd0))) | (sdram_interface_bank5_lock & (subfragments_roundrobin5_grant == 1'd0))) | (sdram_interface_bank6_lock & (subfragments_roundrobin6_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed36 <= 32'd0; case (basesoc_grant) 1'd0: begin rhs_array_muxed36 <= cpu_ibus_adr; end 1'd1: begin rhs_array_muxed36 <= cpu_dbus_adr; end 2'd2: begin rhs_array_muxed36 <= interface0_bus_adr; end default: begin rhs_array_muxed36 <= interface1_bus_adr; end endcase end always @(*) begin rhs_array_muxed37 <= 32'd0; case (basesoc_grant) 1'd0: begin rhs_array_muxed37 <= cpu_ibus_dat_w; end 1'd1: begin rhs_array_muxed37 <= cpu_dbus_dat_w; end 2'd2: begin rhs_array_muxed37 <= interface0_bus_dat_w; end default: begin rhs_array_muxed37 <= interface1_bus_dat_w; end endcase end always @(*) begin rhs_array_muxed38 <= 4'd0; case (basesoc_grant) 1'd0: begin rhs_array_muxed38 <= cpu_ibus_sel; end 1'd1: begin rhs_array_muxed38 <= cpu_dbus_sel; end 2'd2: begin rhs_array_muxed38 <= interface0_bus_sel; end default: begin rhs_array_muxed38 <= interface1_bus_sel; end endcase end always @(*) begin rhs_array_muxed39 <= 1'd0; case (basesoc_grant) 1'd0: begin rhs_array_muxed39 <= cpu_ibus_cyc; end 1'd1: begin rhs_array_muxed39 <= cpu_dbus_cyc; end 2'd2: begin rhs_array_muxed39 <= interface0_bus_cyc; end default: begin rhs_array_muxed39 <= interface1_bus_cyc; end endcase end always @(*) begin rhs_array_muxed40 <= 1'd0; case (basesoc_grant) 1'd0: begin rhs_array_muxed40 <= cpu_ibus_stb; end 1'd1: begin rhs_array_muxed40 <= cpu_dbus_stb; end 2'd2: begin rhs_array_muxed40 <= interface0_bus_stb; end default: begin rhs_array_muxed40 <= interface1_bus_stb; end endcase end always @(*) begin rhs_array_muxed41 <= 1'd0; case (basesoc_grant) 1'd0: begin rhs_array_muxed41 <= cpu_ibus_we; end 1'd1: begin rhs_array_muxed41 <= cpu_dbus_we; end 2'd2: begin rhs_array_muxed41 <= interface0_bus_we; end default: begin rhs_array_muxed41 <= interface1_bus_we; end endcase end always @(*) begin rhs_array_muxed42 <= 3'd0; case (basesoc_grant) 1'd0: begin rhs_array_muxed42 <= cpu_ibus_cti; end 1'd1: begin rhs_array_muxed42 <= cpu_dbus_cti; end 2'd2: begin rhs_array_muxed42 <= interface0_bus_cti; end default: begin rhs_array_muxed42 <= interface1_bus_cti; end endcase end always @(*) begin rhs_array_muxed43 <= 2'd0; case (basesoc_grant) 1'd0: begin rhs_array_muxed43 <= cpu_ibus_bte; end 1'd1: begin rhs_array_muxed43 <= cpu_dbus_bte; end 2'd2: begin rhs_array_muxed43 <= interface0_bus_bte; end default: begin rhs_array_muxed43 <= interface1_bus_bte; end endcase end always @(*) begin array_muxed0 <= 3'd0; case (sdram_steerer_sel0) 1'd0: begin array_muxed0 <= sdram_nop_ba[2:0]; end 1'd1: begin array_muxed0 <= sdram_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin array_muxed0 <= sdram_choose_req_cmd_payload_ba[2:0]; end default: begin array_muxed0 <= sdram_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed1 <= 14'd0; case (sdram_steerer_sel0) 1'd0: begin array_muxed1 <= sdram_nop_a; end 1'd1: begin array_muxed1 <= sdram_choose_cmd_cmd_payload_a; end 2'd2: begin array_muxed1 <= sdram_choose_req_cmd_payload_a; end default: begin array_muxed1 <= sdram_cmd_payload_a; end endcase end always @(*) begin array_muxed2 <= 1'd0; case (sdram_steerer_sel0) 1'd0: begin array_muxed2 <= 1'd0; end 1'd1: begin array_muxed2 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_cas); end 2'd2: begin array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); end default: begin array_muxed2 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); end endcase end always @(*) begin array_muxed3 <= 1'd0; case (sdram_steerer_sel0) 1'd0: begin array_muxed3 <= 1'd0; end 1'd1: begin array_muxed3 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_ras); end 2'd2: begin array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); end default: begin array_muxed3 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); end endcase end always @(*) begin array_muxed4 <= 1'd0; case (sdram_steerer_sel0) 1'd0: begin array_muxed4 <= 1'd0; end 1'd1: begin array_muxed4 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_we); end 2'd2: begin array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); end default: begin array_muxed4 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); end endcase end always @(*) begin array_muxed5 <= 1'd0; case (sdram_steerer_sel0) 1'd0: begin array_muxed5 <= 1'd0; end 1'd1: begin array_muxed5 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_read); end 2'd2: begin array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); end default: begin array_muxed5 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); end endcase end always @(*) begin array_muxed6 <= 1'd0; case (sdram_steerer_sel0) 1'd0: begin array_muxed6 <= 1'd0; end 1'd1: begin array_muxed6 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_write); end 2'd2: begin array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); end default: begin array_muxed6 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); end endcase end always @(*) begin array_muxed7 <= 3'd0; case (sdram_steerer_sel1) 1'd0: begin array_muxed7 <= sdram_nop_ba[2:0]; end 1'd1: begin array_muxed7 <= sdram_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin array_muxed7 <= sdram_choose_req_cmd_payload_ba[2:0]; end default: begin array_muxed7 <= sdram_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed8 <= 14'd0; case (sdram_steerer_sel1) 1'd0: begin array_muxed8 <= sdram_nop_a; end 1'd1: begin array_muxed8 <= sdram_choose_cmd_cmd_payload_a; end 2'd2: begin array_muxed8 <= sdram_choose_req_cmd_payload_a; end default: begin array_muxed8 <= sdram_cmd_payload_a; end endcase end always @(*) begin array_muxed9 <= 1'd0; case (sdram_steerer_sel1) 1'd0: begin array_muxed9 <= 1'd0; end 1'd1: begin array_muxed9 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_cas); end 2'd2: begin array_muxed9 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); end default: begin array_muxed9 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); end endcase end always @(*) begin array_muxed10 <= 1'd0; case (sdram_steerer_sel1) 1'd0: begin array_muxed10 <= 1'd0; end 1'd1: begin array_muxed10 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_ras); end 2'd2: begin array_muxed10 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); end default: begin array_muxed10 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); end endcase end always @(*) begin array_muxed11 <= 1'd0; case (sdram_steerer_sel1) 1'd0: begin array_muxed11 <= 1'd0; end 1'd1: begin array_muxed11 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_we); end 2'd2: begin array_muxed11 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); end default: begin array_muxed11 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); end endcase end always @(*) begin array_muxed12 <= 1'd0; case (sdram_steerer_sel1) 1'd0: begin array_muxed12 <= 1'd0; end 1'd1: begin array_muxed12 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_read); end 2'd2: begin array_muxed12 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); end default: begin array_muxed12 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); end endcase end always @(*) begin array_muxed13 <= 1'd0; case (sdram_steerer_sel1) 1'd0: begin array_muxed13 <= 1'd0; end 1'd1: begin array_muxed13 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_write); end 2'd2: begin array_muxed13 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); end default: begin array_muxed13 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); end endcase end always @(*) begin array_muxed14 <= 3'd0; case (sdram_steerer_sel2) 1'd0: begin array_muxed14 <= sdram_nop_ba[2:0]; end 1'd1: begin array_muxed14 <= sdram_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin array_muxed14 <= sdram_choose_req_cmd_payload_ba[2:0]; end default: begin array_muxed14 <= sdram_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed15 <= 14'd0; case (sdram_steerer_sel2) 1'd0: begin array_muxed15 <= sdram_nop_a; end 1'd1: begin array_muxed15 <= sdram_choose_cmd_cmd_payload_a; end 2'd2: begin array_muxed15 <= sdram_choose_req_cmd_payload_a; end default: begin array_muxed15 <= sdram_cmd_payload_a; end endcase end always @(*) begin array_muxed16 <= 1'd0; case (sdram_steerer_sel2) 1'd0: begin array_muxed16 <= 1'd0; end 1'd1: begin array_muxed16 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_cas); end 2'd2: begin array_muxed16 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); end default: begin array_muxed16 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); end endcase end always @(*) begin array_muxed17 <= 1'd0; case (sdram_steerer_sel2) 1'd0: begin array_muxed17 <= 1'd0; end 1'd1: begin array_muxed17 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_ras); end 2'd2: begin array_muxed17 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); end default: begin array_muxed17 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); end endcase end always @(*) begin array_muxed18 <= 1'd0; case (sdram_steerer_sel2) 1'd0: begin array_muxed18 <= 1'd0; end 1'd1: begin array_muxed18 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_we); end 2'd2: begin array_muxed18 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); end default: begin array_muxed18 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); end endcase end always @(*) begin array_muxed19 <= 1'd0; case (sdram_steerer_sel2) 1'd0: begin array_muxed19 <= 1'd0; end 1'd1: begin array_muxed19 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_read); end 2'd2: begin array_muxed19 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); end default: begin array_muxed19 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); end endcase end always @(*) begin array_muxed20 <= 1'd0; case (sdram_steerer_sel2) 1'd0: begin array_muxed20 <= 1'd0; end 1'd1: begin array_muxed20 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_write); end 2'd2: begin array_muxed20 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); end default: begin array_muxed20 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); end endcase end always @(*) begin array_muxed21 <= 3'd0; case (sdram_steerer_sel3) 1'd0: begin array_muxed21 <= sdram_nop_ba[2:0]; end 1'd1: begin array_muxed21 <= sdram_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin array_muxed21 <= sdram_choose_req_cmd_payload_ba[2:0]; end default: begin array_muxed21 <= sdram_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed22 <= 14'd0; case (sdram_steerer_sel3) 1'd0: begin array_muxed22 <= sdram_nop_a; end 1'd1: begin array_muxed22 <= sdram_choose_cmd_cmd_payload_a; end 2'd2: begin array_muxed22 <= sdram_choose_req_cmd_payload_a; end default: begin array_muxed22 <= sdram_cmd_payload_a; end endcase end always @(*) begin array_muxed23 <= 1'd0; case (sdram_steerer_sel3) 1'd0: begin array_muxed23 <= 1'd0; end 1'd1: begin array_muxed23 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_cas); end 2'd2: begin array_muxed23 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); end default: begin array_muxed23 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); end endcase end always @(*) begin array_muxed24 <= 1'd0; case (sdram_steerer_sel3) 1'd0: begin array_muxed24 <= 1'd0; end 1'd1: begin array_muxed24 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_ras); end 2'd2: begin array_muxed24 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); end default: begin array_muxed24 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); end endcase end always @(*) begin array_muxed25 <= 1'd0; case (sdram_steerer_sel3) 1'd0: begin array_muxed25 <= 1'd0; end 1'd1: begin array_muxed25 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_we); end 2'd2: begin array_muxed25 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); end default: begin array_muxed25 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); end endcase end always @(*) begin array_muxed26 <= 1'd0; case (sdram_steerer_sel3) 1'd0: begin array_muxed26 <= 1'd0; end 1'd1: begin array_muxed26 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_read); end 2'd2: begin array_muxed26 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); end default: begin array_muxed26 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); end endcase end always @(*) begin array_muxed27 <= 1'd0; case (sdram_steerer_sel3) 1'd0: begin array_muxed27 <= 1'd0; end 1'd1: begin array_muxed27 <= ((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & sdram_choose_cmd_cmd_payload_is_write); end 2'd2: begin array_muxed27 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); end default: begin array_muxed27 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); end endcase end assign uart_phy_rx = xilinxmultiregimpl0_regs1; assign xilinxasyncresetsynchronizerimpl0 = (~crg_locked); assign xilinxasyncresetsynchronizerimpl1 = (~crg_locked); assign xilinxasyncresetsynchronizerimpl2 = (~crg_locked); assign xilinxasyncresetsynchronizerimpl3 = (~crg_locked); assign xilinxasyncresetsynchronizerimpl4 = (~crg_locked); assign a7litesataphy_tx_init_plllock1 = xilinxmultiregimpl1_regs1; assign a7litesataphy_tx_init_txresetdone1 = xilinxmultiregimpl2_regs1; assign a7litesataphy_tx_init_txdlysresetdone1 = xilinxmultiregimpl3_regs1; assign a7litesataphy_tx_init_txphinitdone1 = xilinxmultiregimpl4_regs1; assign a7litesataphy_tx_init_txphaligndone1 = xilinxmultiregimpl5_regs1; assign a7litesataphy_rx_init_rxpmaresetdone1 = xilinxmultiregimpl6_regs1; assign a7litesataphy_rx_init_plllock1 = xilinxmultiregimpl7_regs1; assign a7litesataphy_rx_init_rxresetdone1 = xilinxmultiregimpl8_regs1; assign a7litesataphy_rx_init_rxdlysresetdone1 = xilinxmultiregimpl9_regs1; assign a7litesataphy_rx_init_rxsyncdone1 = xilinxmultiregimpl10_regs1; assign a7litesataphy_txpd1 = xilinxmultiregimpl11_regs1; assign a7litesataphy_txelecidle1 = xilinxmultiregimpl12_regs1; assign a7litesataphy_pulsesynchronizer0_toggle_o = xilinxmultiregimpl13_regs1; assign a7litesataphy_pulsesynchronizer1_toggle_o = xilinxmultiregimpl14_regs1; assign a7litesataphy_pulsesynchronizer2_toggle_o = xilinxmultiregimpl15_regs1; assign a7litesataphy_rxcominitdet0 = xilinxmultiregimpl16_regs1; assign a7litesataphy_rxcomwakedet0 = xilinxmultiregimpl17_regs1; assign a7litesataphy_rxdisperr0 = xilinxmultiregimpl18_regs1; assign a7litesataphy_rxnotintable0 = xilinxmultiregimpl19_regs1; assign xilinxasyncresetsynchronizerimpl5 = ((~a7litesataphy_qplllock) | crg_tx_reset); assign xilinxasyncresetsynchronizerimpl6 = ((~a7litesataphy_qplllock) | crg_rx_reset); assign datapath_tx_fifo_produce_rdomain = xilinxmultiregimpl20_regs1; assign datapath_tx_fifo_consume_wdomain = xilinxmultiregimpl21_regs1; assign datapath_rx_fifo_produce_rdomain = xilinxmultiregimpl22_regs1; assign datapath_rx_fifo_consume_wdomain = xilinxmultiregimpl23_regs1; always @(posedge idelay_clk) begin if ((crg_reset_counter != 1'd0)) begin crg_reset_counter <= (crg_reset_counter - 1'd1); end else begin crg_ic_reset <= 1'd0; end if (idelay_rst) begin crg_reset_counter <= 4'd15; crg_ic_reset <= 1'd1; end end always @(posedge sata_rx_clk) begin a7litesataphy_source_valid <= 1'd1; a7litesataphy_source_payload_charisk <= a7litesataphy_rxcharisk; a7litesataphy_source_payload_data <= a7litesataphy_rxdata; if ((datapath_rx_sink_sink_valid & datapath_rx_sink_sink_ready)) begin if ((datapath_rx_sink_sink_payload_charisk != 1'd0)) begin datapath_rx_byte_alignment <= datapath_rx_sink_sink_payload_charisk; end datapath_rx_last_charisk <= datapath_rx_sink_sink_payload_charisk; datapath_rx_last_data <= datapath_rx_sink_sink_payload_data; end if (datapath_rx_converter_converter_source_ready) begin datapath_rx_converter_converter_strobe_all <= 1'd0; end if (datapath_rx_converter_converter_load_part) begin if (((datapath_rx_converter_converter_demux == 1'd1) | datapath_rx_converter_converter_sink_last)) begin datapath_rx_converter_converter_demux <= 1'd0; datapath_rx_converter_converter_strobe_all <= 1'd1; end else begin datapath_rx_converter_converter_demux <= (datapath_rx_converter_converter_demux + 1'd1); end end if ((datapath_rx_converter_converter_source_valid & datapath_rx_converter_converter_source_ready)) begin if ((datapath_rx_converter_converter_sink_valid & datapath_rx_converter_converter_sink_ready)) begin datapath_rx_converter_converter_source_first <= datapath_rx_converter_converter_sink_first; datapath_rx_converter_converter_source_last <= datapath_rx_converter_converter_sink_last; end else begin datapath_rx_converter_converter_source_first <= 1'd0; datapath_rx_converter_converter_source_last <= 1'd0; end end else begin if ((datapath_rx_converter_converter_sink_valid & datapath_rx_converter_converter_sink_ready)) begin datapath_rx_converter_converter_source_first <= (datapath_rx_converter_converter_sink_first | datapath_rx_converter_converter_source_first); datapath_rx_converter_converter_source_last <= (datapath_rx_converter_converter_sink_last | datapath_rx_converter_converter_source_last); end end if (datapath_rx_converter_converter_load_part) begin case (datapath_rx_converter_converter_demux) 1'd0: begin datapath_rx_converter_converter_source_payload_data[17:0] <= datapath_rx_converter_converter_sink_payload_data; end 1'd1: begin datapath_rx_converter_converter_source_payload_data[35:18] <= datapath_rx_converter_converter_sink_payload_data; end endcase end if (datapath_rx_converter_converter_load_part) begin datapath_rx_converter_converter_source_payload_valid_token_count <= (datapath_rx_converter_converter_demux + 1'd1); end if (datapath_rx_converter_reset) begin datapath_rx_converter_converter_source_payload_data <= 36'd0; datapath_rx_converter_converter_source_payload_valid_token_count <= 2'd0; datapath_rx_converter_converter_demux <= 1'd0; datapath_rx_converter_converter_strobe_all <= 1'd0; end datapath_rx_fifo_graycounter0_q_binary <= datapath_rx_fifo_graycounter0_q_next_binary; datapath_rx_fifo_graycounter0_q <= datapath_rx_fifo_graycounter0_q_next; if (sata_rx_rst) begin a7litesataphy_source_valid <= 1'd0; a7litesataphy_source_payload_data <= 16'd0; a7litesataphy_source_payload_charisk <= 2'd0; datapath_rx_byte_alignment <= 2'd0; datapath_rx_last_charisk <= 2'd0; datapath_rx_last_data <= 16'd0; datapath_rx_converter_converter_source_payload_data <= 36'd0; datapath_rx_converter_converter_source_payload_valid_token_count <= 2'd0; datapath_rx_converter_converter_demux <= 1'd0; datapath_rx_converter_converter_strobe_all <= 1'd0; datapath_rx_fifo_graycounter0_q <= 4'd0; datapath_rx_fifo_graycounter0_q_binary <= 4'd0; end xilinxmultiregimpl23_regs0 <= datapath_rx_fifo_graycounter1_q; xilinxmultiregimpl23_regs1 <= xilinxmultiregimpl23_regs0; end always @(posedge sata_tx_clk) begin a7litesataphy_txcharisk <= a7litesataphy_sink_payload_charisk; a7litesataphy_txdata <= a7litesataphy_sink_payload_data; a7litesataphy_sink_ready <= 1'd1; a7litesataphy_pulsesynchronizer0_toggle_o_r <= a7litesataphy_pulsesynchronizer0_toggle_o; a7litesataphy_pulsesynchronizer1_toggle_o_r <= a7litesataphy_pulsesynchronizer1_toggle_o; if (a7litesataphy_pulsesynchronizer2_i) begin a7litesataphy_pulsesynchronizer2_toggle_i <= (~a7litesataphy_pulsesynchronizer2_toggle_i); end datapath_tx_fifo_graycounter1_q_binary <= datapath_tx_fifo_graycounter1_q_next_binary; datapath_tx_fifo_graycounter1_q <= datapath_tx_fifo_graycounter1_q_next; if ((datapath_tx_converter_converter_source_valid & datapath_tx_converter_converter_source_ready)) begin if (datapath_tx_converter_converter_last) begin datapath_tx_converter_converter_mux <= 1'd0; end else begin datapath_tx_converter_converter_mux <= (datapath_tx_converter_converter_mux + 1'd1); end end if (sata_tx_rst) begin a7litesataphy_sink_ready <= 1'd0; a7litesataphy_txcharisk <= 2'd0; a7litesataphy_txdata <= 16'd0; datapath_tx_fifo_graycounter1_q <= 4'd0; datapath_tx_fifo_graycounter1_q_binary <= 4'd0; datapath_tx_converter_converter_mux <= 1'd0; end xilinxmultiregimpl11_regs0 <= a7litesataphy_txpd0; xilinxmultiregimpl11_regs1 <= xilinxmultiregimpl11_regs0; xilinxmultiregimpl12_regs0 <= a7litesataphy_txelecidle0; xilinxmultiregimpl12_regs1 <= xilinxmultiregimpl12_regs0; xilinxmultiregimpl13_regs0 <= a7litesataphy_pulsesynchronizer0_toggle_i; xilinxmultiregimpl13_regs1 <= xilinxmultiregimpl13_regs0; xilinxmultiregimpl14_regs0 <= a7litesataphy_pulsesynchronizer1_toggle_i; xilinxmultiregimpl14_regs1 <= xilinxmultiregimpl14_regs0; xilinxmultiregimpl20_regs0 <= datapath_tx_fifo_graycounter0_q; xilinxmultiregimpl20_regs1 <= xilinxmultiregimpl20_regs0; end always @(posedge sys_clk) begin if ((soccontroller_bus_errors != 32'd4294967295)) begin if (soccontroller_bus_error) begin soccontroller_bus_errors <= (soccontroller_bus_errors + 1'd1); end end basesoc_ram_bus_ack <= 1'd0; if (((basesoc_ram_bus_cyc & basesoc_ram_bus_stb) & (~basesoc_ram_bus_ack))) begin basesoc_ram_bus_ack <= 1'd1; end ram_bus_ram_bus_ack <= 1'd0; if (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & (~ram_bus_ram_bus_ack))) begin ram_bus_ram_bus_ack <= 1'd1; end uart_phy_sink_ready <= 1'd0; if (((uart_phy_sink_valid & (~uart_phy_tx_busy)) & (~uart_phy_sink_ready))) begin uart_phy_tx_reg <= uart_phy_sink_payload_data; uart_phy_tx_bitcount <= 1'd0; uart_phy_tx_busy <= 1'd1; serial_tx <= 1'd0; end else begin if ((uart_phy_tx_clken & uart_phy_tx_busy)) begin uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1); if ((uart_phy_tx_bitcount == 4'd8)) begin serial_tx <= 1'd1; end else begin if ((uart_phy_tx_bitcount == 4'd9)) begin serial_tx <= 1'd1; uart_phy_tx_busy <= 1'd0; uart_phy_sink_ready <= 1'd1; end else begin serial_tx <= uart_phy_tx_reg[0]; uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]}; end end end end if (uart_phy_tx_busy) begin {uart_phy_tx_clken, uart_phy_tx_clkphase} <= (uart_phy_tx_clkphase + uart_phy_storage); end else begin {uart_phy_tx_clken, uart_phy_tx_clkphase} <= uart_phy_storage; end uart_phy_source_valid <= 1'd0; uart_phy_rx_r <= uart_phy_rx; if ((~uart_phy_rx_busy)) begin if (((~uart_phy_rx) & uart_phy_rx_r)) begin uart_phy_rx_busy <= 1'd1; uart_phy_rx_bitcount <= 1'd0; end end else begin if (uart_phy_rx_clken) begin uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1); if ((uart_phy_rx_bitcount == 1'd0)) begin if (uart_phy_rx) begin uart_phy_rx_busy <= 1'd0; end end else begin if ((uart_phy_rx_bitcount == 4'd9)) begin uart_phy_rx_busy <= 1'd0; if (uart_phy_rx) begin uart_phy_source_payload_data <= uart_phy_rx_reg; uart_phy_source_valid <= 1'd1; end end else begin uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]}; end end end end if (uart_phy_rx_busy) begin {uart_phy_rx_clken, uart_phy_rx_clkphase} <= (uart_phy_rx_clkphase + uart_phy_storage); end else begin {uart_phy_rx_clken, uart_phy_rx_clkphase} <= 32'd2147483648; end if (uart_tx_clear) begin uart_tx_pending <= 1'd0; end uart_tx_old_trigger <= uart_tx_trigger; if (((~uart_tx_trigger) & uart_tx_old_trigger)) begin uart_tx_pending <= 1'd1; end if (uart_rx_clear) begin uart_rx_pending <= 1'd0; end uart_rx_old_trigger <= uart_rx_trigger; if (((~uart_rx_trigger) & uart_rx_old_trigger)) begin uart_rx_pending <= 1'd1; end if (uart_tx_fifo_syncfifo_re) begin uart_tx_fifo_readable <= 1'd1; end else begin if (uart_tx_fifo_re) begin uart_tx_fifo_readable <= 1'd0; end end if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1); end if (uart_tx_fifo_do_read) begin uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1); end if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin if ((~uart_tx_fifo_do_read)) begin uart_tx_fifo_level0 <= (uart_tx_fifo_level0 + 1'd1); end end else begin if (uart_tx_fifo_do_read) begin uart_tx_fifo_level0 <= (uart_tx_fifo_level0 - 1'd1); end end if (uart_rx_fifo_syncfifo_re) begin uart_rx_fifo_readable <= 1'd1; end else begin if (uart_rx_fifo_re) begin uart_rx_fifo_readable <= 1'd0; end end if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1); end if (uart_rx_fifo_do_read) begin uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1); end if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin if ((~uart_rx_fifo_do_read)) begin uart_rx_fifo_level0 <= (uart_rx_fifo_level0 + 1'd1); end end else begin if (uart_rx_fifo_do_read) begin uart_rx_fifo_level0 <= (uart_rx_fifo_level0 - 1'd1); end end if (timer_en_storage) begin if ((timer_value == 1'd0)) begin timer_value <= timer_reload_storage; end else begin timer_value <= (timer_value - 1'd1); end end else begin timer_value <= timer_load_storage; end if (timer_update_value_re) begin timer_value_status <= timer_value; end if (timer_zero_clear) begin timer_zero_pending <= 1'd0; end timer_zero_old_trigger <= timer_zero_trigger; if (((~timer_zero_trigger) & timer_zero_old_trigger)) begin timer_zero_pending <= 1'd1; end a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip0_value0 <= 3'd7; end a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip1_value0 <= 3'd7; end a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip0_value1 <= 3'd7; end a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip1_value1 <= 3'd7; end a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip0_value2 <= 3'd7; end a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip0_value3 <= 3'd7; end a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip1_value2 <= 3'd7; end a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip1_value3 <= 3'd7; end a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip2_value0 <= 3'd7; end a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip2_value1 <= 3'd7; end a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip3_value0 <= 3'd7; end a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip3_value1 <= 3'd7; end a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip4_value0 <= 3'd7; end a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip4_value1 <= 3'd7; end a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip5_value0 <= 3'd7; end a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip5_value1 <= 3'd7; end a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip6_value0 <= 3'd7; end a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip6_value1 <= 3'd7; end a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip7_value0 <= 3'd7; end a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip7_value1 <= 3'd7; end a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip8_value0 <= 3'd7; end a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip8_value1 <= 3'd7; end a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip9_value0 <= 3'd7; end a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip9_value1 <= 3'd7; end a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip10_value0 <= 3'd7; end a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip10_value1 <= 3'd7; end a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip11_value0 <= 3'd7; end a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip11_value1 <= 3'd7; end a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip12_value0 <= 3'd7; end a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip12_value1 <= 3'd7; end a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip13_value0 <= 3'd7; end a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip13_value1 <= 3'd7; end a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip14_value0 <= 3'd7; end a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip14_value1 <= 3'd7; end a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip15_value0 <= 3'd7; end a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip15_value1 <= 3'd7; end a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; if (sdram_inti_p0_rddata_valid) begin sdram_phaseinjector0_rddata_status <= sdram_inti_p0_rddata; end if (sdram_inti_p1_rddata_valid) begin sdram_phaseinjector1_rddata_status <= sdram_inti_p1_rddata; end if (sdram_inti_p2_rddata_valid) begin sdram_phaseinjector2_rddata_status <= sdram_inti_p2_rddata; end if (sdram_inti_p3_rddata_valid) begin sdram_phaseinjector3_rddata_status <= sdram_inti_p3_rddata; end if ((sdram_timer_wait & (~sdram_timer_done0))) begin sdram_timer_count1 <= (sdram_timer_count1 - 1'd1); end else begin sdram_timer_count1 <= 10'd624; end sdram_postponer_req_o <= 1'd0; if (sdram_postponer_req_i) begin sdram_postponer_count <= (sdram_postponer_count - 1'd1); if ((sdram_postponer_count == 1'd0)) begin sdram_postponer_count <= 1'd0; sdram_postponer_req_o <= 1'd1; end end if (sdram_sequencer_start0) begin sdram_sequencer_count <= 1'd0; end else begin if (sdram_sequencer_done1) begin if ((sdram_sequencer_count != 1'd0)) begin sdram_sequencer_count <= (sdram_sequencer_count - 1'd1); end end end sdram_cmd_payload_a <= 1'd0; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd0; sdram_cmd_payload_we <= 1'd0; sdram_sequencer_done1 <= 1'd0; if ((sdram_sequencer_start1 & (sdram_sequencer_counter == 1'd0))) begin sdram_cmd_payload_a <= 11'd1024; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd1; sdram_cmd_payload_we <= 1'd1; end if ((sdram_sequencer_counter == 2'd2)) begin sdram_cmd_payload_a <= 1'd0; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd1; sdram_cmd_payload_ras <= 1'd1; sdram_cmd_payload_we <= 1'd0; end if ((sdram_sequencer_counter == 6'd34)) begin sdram_cmd_payload_a <= 1'd0; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd0; sdram_cmd_payload_we <= 1'd0; sdram_sequencer_done1 <= 1'd1; end if ((sdram_sequencer_counter == 6'd34)) begin sdram_sequencer_counter <= 1'd0; end else begin if ((sdram_sequencer_counter != 1'd0)) begin sdram_sequencer_counter <= (sdram_sequencer_counter + 1'd1); end else begin if (sdram_sequencer_start1) begin sdram_sequencer_counter <= 1'd1; end end end if ((sdram_zqcs_timer_wait & (~sdram_zqcs_timer_done0))) begin sdram_zqcs_timer_count1 <= (sdram_zqcs_timer_count1 - 1'd1); end else begin sdram_zqcs_timer_count1 <= 27'd79999999; end sdram_zqcs_executer_done <= 1'd0; if ((sdram_zqcs_executer_start & (sdram_zqcs_executer_counter == 1'd0))) begin sdram_cmd_payload_a <= 11'd1024; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd1; sdram_cmd_payload_we <= 1'd1; end if ((sdram_zqcs_executer_counter == 2'd2)) begin sdram_cmd_payload_a <= 1'd0; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd0; sdram_cmd_payload_we <= 1'd1; end if ((sdram_zqcs_executer_counter == 5'd18)) begin sdram_cmd_payload_a <= 1'd0; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd0; sdram_cmd_payload_we <= 1'd0; sdram_zqcs_executer_done <= 1'd1; end if ((sdram_zqcs_executer_counter == 5'd18)) begin sdram_zqcs_executer_counter <= 1'd0; end else begin if ((sdram_zqcs_executer_counter != 1'd0)) begin sdram_zqcs_executer_counter <= (sdram_zqcs_executer_counter + 1'd1); end else begin if (sdram_zqcs_executer_start) begin sdram_zqcs_executer_counter <= 1'd1; end end end subfragments_refresher_state <= subfragments_refresher_next_state; if (sdram_bankmachine0_row_close) begin sdram_bankmachine0_row_opened <= 1'd0; end else begin if (sdram_bankmachine0_row_open) begin sdram_bankmachine0_row_opened <= 1'd1; sdram_bankmachine0_row <= sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; end end if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin sdram_bankmachine0_cmd_buffer_lookahead_produce <= (sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin sdram_bankmachine0_cmd_buffer_lookahead_consume <= (sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready)) begin sdram_bankmachine0_cmd_buffer_source_valid <= sdram_bankmachine0_cmd_buffer_sink_valid; sdram_bankmachine0_cmd_buffer_source_first <= sdram_bankmachine0_cmd_buffer_sink_first; sdram_bankmachine0_cmd_buffer_source_last <= sdram_bankmachine0_cmd_buffer_sink_last; sdram_bankmachine0_cmd_buffer_source_payload_we <= sdram_bankmachine0_cmd_buffer_sink_payload_we; sdram_bankmachine0_cmd_buffer_source_payload_addr <= sdram_bankmachine0_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine0_twtpcon_valid) begin sdram_bankmachine0_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine0_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine0_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine0_twtpcon_ready)) begin sdram_bankmachine0_twtpcon_count <= (sdram_bankmachine0_twtpcon_count - 1'd1); if ((sdram_bankmachine0_twtpcon_count == 1'd1)) begin sdram_bankmachine0_twtpcon_ready <= 1'd1; end end end if (sdram_bankmachine0_trccon_valid) begin sdram_bankmachine0_trccon_count <= 3'd4; if (1'd0) begin sdram_bankmachine0_trccon_ready <= 1'd1; end else begin sdram_bankmachine0_trccon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine0_trccon_ready)) begin sdram_bankmachine0_trccon_count <= (sdram_bankmachine0_trccon_count - 1'd1); if ((sdram_bankmachine0_trccon_count == 1'd1)) begin sdram_bankmachine0_trccon_ready <= 1'd1; end end end if (sdram_bankmachine0_trascon_valid) begin sdram_bankmachine0_trascon_count <= 2'd3; if (1'd0) begin sdram_bankmachine0_trascon_ready <= 1'd1; end else begin sdram_bankmachine0_trascon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine0_trascon_ready)) begin sdram_bankmachine0_trascon_count <= (sdram_bankmachine0_trascon_count - 1'd1); if ((sdram_bankmachine0_trascon_count == 1'd1)) begin sdram_bankmachine0_trascon_ready <= 1'd1; end end end subfragments_bankmachine0_state <= subfragments_bankmachine0_next_state; if (sdram_bankmachine1_row_close) begin sdram_bankmachine1_row_opened <= 1'd0; end else begin if (sdram_bankmachine1_row_open) begin sdram_bankmachine1_row_opened <= 1'd1; sdram_bankmachine1_row <= sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; end end if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin sdram_bankmachine1_cmd_buffer_lookahead_produce <= (sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin sdram_bankmachine1_cmd_buffer_lookahead_consume <= (sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready)) begin sdram_bankmachine1_cmd_buffer_source_valid <= sdram_bankmachine1_cmd_buffer_sink_valid; sdram_bankmachine1_cmd_buffer_source_first <= sdram_bankmachine1_cmd_buffer_sink_first; sdram_bankmachine1_cmd_buffer_source_last <= sdram_bankmachine1_cmd_buffer_sink_last; sdram_bankmachine1_cmd_buffer_source_payload_we <= sdram_bankmachine1_cmd_buffer_sink_payload_we; sdram_bankmachine1_cmd_buffer_source_payload_addr <= sdram_bankmachine1_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine1_twtpcon_valid) begin sdram_bankmachine1_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine1_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine1_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine1_twtpcon_ready)) begin sdram_bankmachine1_twtpcon_count <= (sdram_bankmachine1_twtpcon_count - 1'd1); if ((sdram_bankmachine1_twtpcon_count == 1'd1)) begin sdram_bankmachine1_twtpcon_ready <= 1'd1; end end end if (sdram_bankmachine1_trccon_valid) begin sdram_bankmachine1_trccon_count <= 3'd4; if (1'd0) begin sdram_bankmachine1_trccon_ready <= 1'd1; end else begin sdram_bankmachine1_trccon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine1_trccon_ready)) begin sdram_bankmachine1_trccon_count <= (sdram_bankmachine1_trccon_count - 1'd1); if ((sdram_bankmachine1_trccon_count == 1'd1)) begin sdram_bankmachine1_trccon_ready <= 1'd1; end end end if (sdram_bankmachine1_trascon_valid) begin sdram_bankmachine1_trascon_count <= 2'd3; if (1'd0) begin sdram_bankmachine1_trascon_ready <= 1'd1; end else begin sdram_bankmachine1_trascon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine1_trascon_ready)) begin sdram_bankmachine1_trascon_count <= (sdram_bankmachine1_trascon_count - 1'd1); if ((sdram_bankmachine1_trascon_count == 1'd1)) begin sdram_bankmachine1_trascon_ready <= 1'd1; end end end subfragments_bankmachine1_state <= subfragments_bankmachine1_next_state; if (sdram_bankmachine2_row_close) begin sdram_bankmachine2_row_opened <= 1'd0; end else begin if (sdram_bankmachine2_row_open) begin sdram_bankmachine2_row_opened <= 1'd1; sdram_bankmachine2_row <= sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; end end if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin sdram_bankmachine2_cmd_buffer_lookahead_produce <= (sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin sdram_bankmachine2_cmd_buffer_lookahead_consume <= (sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready)) begin sdram_bankmachine2_cmd_buffer_source_valid <= sdram_bankmachine2_cmd_buffer_sink_valid; sdram_bankmachine2_cmd_buffer_source_first <= sdram_bankmachine2_cmd_buffer_sink_first; sdram_bankmachine2_cmd_buffer_source_last <= sdram_bankmachine2_cmd_buffer_sink_last; sdram_bankmachine2_cmd_buffer_source_payload_we <= sdram_bankmachine2_cmd_buffer_sink_payload_we; sdram_bankmachine2_cmd_buffer_source_payload_addr <= sdram_bankmachine2_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine2_twtpcon_valid) begin sdram_bankmachine2_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine2_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine2_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine2_twtpcon_ready)) begin sdram_bankmachine2_twtpcon_count <= (sdram_bankmachine2_twtpcon_count - 1'd1); if ((sdram_bankmachine2_twtpcon_count == 1'd1)) begin sdram_bankmachine2_twtpcon_ready <= 1'd1; end end end if (sdram_bankmachine2_trccon_valid) begin sdram_bankmachine2_trccon_count <= 3'd4; if (1'd0) begin sdram_bankmachine2_trccon_ready <= 1'd1; end else begin sdram_bankmachine2_trccon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine2_trccon_ready)) begin sdram_bankmachine2_trccon_count <= (sdram_bankmachine2_trccon_count - 1'd1); if ((sdram_bankmachine2_trccon_count == 1'd1)) begin sdram_bankmachine2_trccon_ready <= 1'd1; end end end if (sdram_bankmachine2_trascon_valid) begin sdram_bankmachine2_trascon_count <= 2'd3; if (1'd0) begin sdram_bankmachine2_trascon_ready <= 1'd1; end else begin sdram_bankmachine2_trascon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine2_trascon_ready)) begin sdram_bankmachine2_trascon_count <= (sdram_bankmachine2_trascon_count - 1'd1); if ((sdram_bankmachine2_trascon_count == 1'd1)) begin sdram_bankmachine2_trascon_ready <= 1'd1; end end end subfragments_bankmachine2_state <= subfragments_bankmachine2_next_state; if (sdram_bankmachine3_row_close) begin sdram_bankmachine3_row_opened <= 1'd0; end else begin if (sdram_bankmachine3_row_open) begin sdram_bankmachine3_row_opened <= 1'd1; sdram_bankmachine3_row <= sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; end end if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin sdram_bankmachine3_cmd_buffer_lookahead_produce <= (sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin sdram_bankmachine3_cmd_buffer_lookahead_consume <= (sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready)) begin sdram_bankmachine3_cmd_buffer_source_valid <= sdram_bankmachine3_cmd_buffer_sink_valid; sdram_bankmachine3_cmd_buffer_source_first <= sdram_bankmachine3_cmd_buffer_sink_first; sdram_bankmachine3_cmd_buffer_source_last <= sdram_bankmachine3_cmd_buffer_sink_last; sdram_bankmachine3_cmd_buffer_source_payload_we <= sdram_bankmachine3_cmd_buffer_sink_payload_we; sdram_bankmachine3_cmd_buffer_source_payload_addr <= sdram_bankmachine3_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine3_twtpcon_valid) begin sdram_bankmachine3_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine3_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine3_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine3_twtpcon_ready)) begin sdram_bankmachine3_twtpcon_count <= (sdram_bankmachine3_twtpcon_count - 1'd1); if ((sdram_bankmachine3_twtpcon_count == 1'd1)) begin sdram_bankmachine3_twtpcon_ready <= 1'd1; end end end if (sdram_bankmachine3_trccon_valid) begin sdram_bankmachine3_trccon_count <= 3'd4; if (1'd0) begin sdram_bankmachine3_trccon_ready <= 1'd1; end else begin sdram_bankmachine3_trccon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine3_trccon_ready)) begin sdram_bankmachine3_trccon_count <= (sdram_bankmachine3_trccon_count - 1'd1); if ((sdram_bankmachine3_trccon_count == 1'd1)) begin sdram_bankmachine3_trccon_ready <= 1'd1; end end end if (sdram_bankmachine3_trascon_valid) begin sdram_bankmachine3_trascon_count <= 2'd3; if (1'd0) begin sdram_bankmachine3_trascon_ready <= 1'd1; end else begin sdram_bankmachine3_trascon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine3_trascon_ready)) begin sdram_bankmachine3_trascon_count <= (sdram_bankmachine3_trascon_count - 1'd1); if ((sdram_bankmachine3_trascon_count == 1'd1)) begin sdram_bankmachine3_trascon_ready <= 1'd1; end end end subfragments_bankmachine3_state <= subfragments_bankmachine3_next_state; if (sdram_bankmachine4_row_close) begin sdram_bankmachine4_row_opened <= 1'd0; end else begin if (sdram_bankmachine4_row_open) begin sdram_bankmachine4_row_opened <= 1'd1; sdram_bankmachine4_row <= sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; end end if (((sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin sdram_bankmachine4_cmd_buffer_lookahead_produce <= (sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin sdram_bankmachine4_cmd_buffer_lookahead_consume <= (sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine4_cmd_buffer_lookahead_level <= (sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin sdram_bankmachine4_cmd_buffer_lookahead_level <= (sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine4_cmd_buffer_source_valid) | sdram_bankmachine4_cmd_buffer_source_ready)) begin sdram_bankmachine4_cmd_buffer_source_valid <= sdram_bankmachine4_cmd_buffer_sink_valid; sdram_bankmachine4_cmd_buffer_source_first <= sdram_bankmachine4_cmd_buffer_sink_first; sdram_bankmachine4_cmd_buffer_source_last <= sdram_bankmachine4_cmd_buffer_sink_last; sdram_bankmachine4_cmd_buffer_source_payload_we <= sdram_bankmachine4_cmd_buffer_sink_payload_we; sdram_bankmachine4_cmd_buffer_source_payload_addr <= sdram_bankmachine4_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine4_twtpcon_valid) begin sdram_bankmachine4_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine4_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine4_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine4_twtpcon_ready)) begin sdram_bankmachine4_twtpcon_count <= (sdram_bankmachine4_twtpcon_count - 1'd1); if ((sdram_bankmachine4_twtpcon_count == 1'd1)) begin sdram_bankmachine4_twtpcon_ready <= 1'd1; end end end if (sdram_bankmachine4_trccon_valid) begin sdram_bankmachine4_trccon_count <= 3'd4; if (1'd0) begin sdram_bankmachine4_trccon_ready <= 1'd1; end else begin sdram_bankmachine4_trccon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine4_trccon_ready)) begin sdram_bankmachine4_trccon_count <= (sdram_bankmachine4_trccon_count - 1'd1); if ((sdram_bankmachine4_trccon_count == 1'd1)) begin sdram_bankmachine4_trccon_ready <= 1'd1; end end end if (sdram_bankmachine4_trascon_valid) begin sdram_bankmachine4_trascon_count <= 2'd3; if (1'd0) begin sdram_bankmachine4_trascon_ready <= 1'd1; end else begin sdram_bankmachine4_trascon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine4_trascon_ready)) begin sdram_bankmachine4_trascon_count <= (sdram_bankmachine4_trascon_count - 1'd1); if ((sdram_bankmachine4_trascon_count == 1'd1)) begin sdram_bankmachine4_trascon_ready <= 1'd1; end end end subfragments_bankmachine4_state <= subfragments_bankmachine4_next_state; if (sdram_bankmachine5_row_close) begin sdram_bankmachine5_row_opened <= 1'd0; end else begin if (sdram_bankmachine5_row_open) begin sdram_bankmachine5_row_opened <= 1'd1; sdram_bankmachine5_row <= sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; end end if (((sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin sdram_bankmachine5_cmd_buffer_lookahead_produce <= (sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin sdram_bankmachine5_cmd_buffer_lookahead_consume <= (sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine5_cmd_buffer_lookahead_level <= (sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin sdram_bankmachine5_cmd_buffer_lookahead_level <= (sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine5_cmd_buffer_source_valid) | sdram_bankmachine5_cmd_buffer_source_ready)) begin sdram_bankmachine5_cmd_buffer_source_valid <= sdram_bankmachine5_cmd_buffer_sink_valid; sdram_bankmachine5_cmd_buffer_source_first <= sdram_bankmachine5_cmd_buffer_sink_first; sdram_bankmachine5_cmd_buffer_source_last <= sdram_bankmachine5_cmd_buffer_sink_last; sdram_bankmachine5_cmd_buffer_source_payload_we <= sdram_bankmachine5_cmd_buffer_sink_payload_we; sdram_bankmachine5_cmd_buffer_source_payload_addr <= sdram_bankmachine5_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine5_twtpcon_valid) begin sdram_bankmachine5_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine5_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine5_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine5_twtpcon_ready)) begin sdram_bankmachine5_twtpcon_count <= (sdram_bankmachine5_twtpcon_count - 1'd1); if ((sdram_bankmachine5_twtpcon_count == 1'd1)) begin sdram_bankmachine5_twtpcon_ready <= 1'd1; end end end if (sdram_bankmachine5_trccon_valid) begin sdram_bankmachine5_trccon_count <= 3'd4; if (1'd0) begin sdram_bankmachine5_trccon_ready <= 1'd1; end else begin sdram_bankmachine5_trccon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine5_trccon_ready)) begin sdram_bankmachine5_trccon_count <= (sdram_bankmachine5_trccon_count - 1'd1); if ((sdram_bankmachine5_trccon_count == 1'd1)) begin sdram_bankmachine5_trccon_ready <= 1'd1; end end end if (sdram_bankmachine5_trascon_valid) begin sdram_bankmachine5_trascon_count <= 2'd3; if (1'd0) begin sdram_bankmachine5_trascon_ready <= 1'd1; end else begin sdram_bankmachine5_trascon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine5_trascon_ready)) begin sdram_bankmachine5_trascon_count <= (sdram_bankmachine5_trascon_count - 1'd1); if ((sdram_bankmachine5_trascon_count == 1'd1)) begin sdram_bankmachine5_trascon_ready <= 1'd1; end end end subfragments_bankmachine5_state <= subfragments_bankmachine5_next_state; if (sdram_bankmachine6_row_close) begin sdram_bankmachine6_row_opened <= 1'd0; end else begin if (sdram_bankmachine6_row_open) begin sdram_bankmachine6_row_opened <= 1'd1; sdram_bankmachine6_row <= sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; end end if (((sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin sdram_bankmachine6_cmd_buffer_lookahead_produce <= (sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin sdram_bankmachine6_cmd_buffer_lookahead_consume <= (sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine6_cmd_buffer_lookahead_level <= (sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin sdram_bankmachine6_cmd_buffer_lookahead_level <= (sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine6_cmd_buffer_source_valid) | sdram_bankmachine6_cmd_buffer_source_ready)) begin sdram_bankmachine6_cmd_buffer_source_valid <= sdram_bankmachine6_cmd_buffer_sink_valid; sdram_bankmachine6_cmd_buffer_source_first <= sdram_bankmachine6_cmd_buffer_sink_first; sdram_bankmachine6_cmd_buffer_source_last <= sdram_bankmachine6_cmd_buffer_sink_last; sdram_bankmachine6_cmd_buffer_source_payload_we <= sdram_bankmachine6_cmd_buffer_sink_payload_we; sdram_bankmachine6_cmd_buffer_source_payload_addr <= sdram_bankmachine6_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine6_twtpcon_valid) begin sdram_bankmachine6_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine6_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine6_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine6_twtpcon_ready)) begin sdram_bankmachine6_twtpcon_count <= (sdram_bankmachine6_twtpcon_count - 1'd1); if ((sdram_bankmachine6_twtpcon_count == 1'd1)) begin sdram_bankmachine6_twtpcon_ready <= 1'd1; end end end if (sdram_bankmachine6_trccon_valid) begin sdram_bankmachine6_trccon_count <= 3'd4; if (1'd0) begin sdram_bankmachine6_trccon_ready <= 1'd1; end else begin sdram_bankmachine6_trccon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine6_trccon_ready)) begin sdram_bankmachine6_trccon_count <= (sdram_bankmachine6_trccon_count - 1'd1); if ((sdram_bankmachine6_trccon_count == 1'd1)) begin sdram_bankmachine6_trccon_ready <= 1'd1; end end end if (sdram_bankmachine6_trascon_valid) begin sdram_bankmachine6_trascon_count <= 2'd3; if (1'd0) begin sdram_bankmachine6_trascon_ready <= 1'd1; end else begin sdram_bankmachine6_trascon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine6_trascon_ready)) begin sdram_bankmachine6_trascon_count <= (sdram_bankmachine6_trascon_count - 1'd1); if ((sdram_bankmachine6_trascon_count == 1'd1)) begin sdram_bankmachine6_trascon_ready <= 1'd1; end end end subfragments_bankmachine6_state <= subfragments_bankmachine6_next_state; if (sdram_bankmachine7_row_close) begin sdram_bankmachine7_row_opened <= 1'd0; end else begin if (sdram_bankmachine7_row_open) begin sdram_bankmachine7_row_opened <= 1'd1; sdram_bankmachine7_row <= sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; end end if (((sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin sdram_bankmachine7_cmd_buffer_lookahead_produce <= (sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin sdram_bankmachine7_cmd_buffer_lookahead_consume <= (sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine7_cmd_buffer_lookahead_level <= (sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin sdram_bankmachine7_cmd_buffer_lookahead_level <= (sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine7_cmd_buffer_source_valid) | sdram_bankmachine7_cmd_buffer_source_ready)) begin sdram_bankmachine7_cmd_buffer_source_valid <= sdram_bankmachine7_cmd_buffer_sink_valid; sdram_bankmachine7_cmd_buffer_source_first <= sdram_bankmachine7_cmd_buffer_sink_first; sdram_bankmachine7_cmd_buffer_source_last <= sdram_bankmachine7_cmd_buffer_sink_last; sdram_bankmachine7_cmd_buffer_source_payload_we <= sdram_bankmachine7_cmd_buffer_sink_payload_we; sdram_bankmachine7_cmd_buffer_source_payload_addr <= sdram_bankmachine7_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine7_twtpcon_valid) begin sdram_bankmachine7_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine7_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine7_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine7_twtpcon_ready)) begin sdram_bankmachine7_twtpcon_count <= (sdram_bankmachine7_twtpcon_count - 1'd1); if ((sdram_bankmachine7_twtpcon_count == 1'd1)) begin sdram_bankmachine7_twtpcon_ready <= 1'd1; end end end if (sdram_bankmachine7_trccon_valid) begin sdram_bankmachine7_trccon_count <= 3'd4; if (1'd0) begin sdram_bankmachine7_trccon_ready <= 1'd1; end else begin sdram_bankmachine7_trccon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine7_trccon_ready)) begin sdram_bankmachine7_trccon_count <= (sdram_bankmachine7_trccon_count - 1'd1); if ((sdram_bankmachine7_trccon_count == 1'd1)) begin sdram_bankmachine7_trccon_ready <= 1'd1; end end end if (sdram_bankmachine7_trascon_valid) begin sdram_bankmachine7_trascon_count <= 2'd3; if (1'd0) begin sdram_bankmachine7_trascon_ready <= 1'd1; end else begin sdram_bankmachine7_trascon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine7_trascon_ready)) begin sdram_bankmachine7_trascon_count <= (sdram_bankmachine7_trascon_count - 1'd1); if ((sdram_bankmachine7_trascon_count == 1'd1)) begin sdram_bankmachine7_trascon_ready <= 1'd1; end end end subfragments_bankmachine7_state <= subfragments_bankmachine7_next_state; if ((~sdram_en0)) begin sdram_time0 <= 5'd31; end else begin if ((~sdram_max_time0)) begin sdram_time0 <= (sdram_time0 - 1'd1); end end if ((~sdram_en1)) begin sdram_time1 <= 4'd15; end else begin if ((~sdram_max_time1)) begin sdram_time1 <= (sdram_time1 - 1'd1); end end if (sdram_choose_cmd_ce) begin case (sdram_choose_cmd_grant) 1'd0: begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end else begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end else begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end else begin if (sdram_choose_cmd_request[4]) begin sdram_choose_cmd_grant <= 3'd4; end else begin if (sdram_choose_cmd_request[5]) begin sdram_choose_cmd_grant <= 3'd5; end else begin if (sdram_choose_cmd_request[6]) begin sdram_choose_cmd_grant <= 3'd6; end else begin if (sdram_choose_cmd_request[7]) begin sdram_choose_cmd_grant <= 3'd7; end end end end end end end end 1'd1: begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end else begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end else begin if (sdram_choose_cmd_request[4]) begin sdram_choose_cmd_grant <= 3'd4; end else begin if (sdram_choose_cmd_request[5]) begin sdram_choose_cmd_grant <= 3'd5; end else begin if (sdram_choose_cmd_request[6]) begin sdram_choose_cmd_grant <= 3'd6; end else begin if (sdram_choose_cmd_request[7]) begin sdram_choose_cmd_grant <= 3'd7; end else begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end end end end end end end end 2'd2: begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end else begin if (sdram_choose_cmd_request[4]) begin sdram_choose_cmd_grant <= 3'd4; end else begin if (sdram_choose_cmd_request[5]) begin sdram_choose_cmd_grant <= 3'd5; end else begin if (sdram_choose_cmd_request[6]) begin sdram_choose_cmd_grant <= 3'd6; end else begin if (sdram_choose_cmd_request[7]) begin sdram_choose_cmd_grant <= 3'd7; end else begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end else begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end end end end end end end end 2'd3: begin if (sdram_choose_cmd_request[4]) begin sdram_choose_cmd_grant <= 3'd4; end else begin if (sdram_choose_cmd_request[5]) begin sdram_choose_cmd_grant <= 3'd5; end else begin if (sdram_choose_cmd_request[6]) begin sdram_choose_cmd_grant <= 3'd6; end else begin if (sdram_choose_cmd_request[7]) begin sdram_choose_cmd_grant <= 3'd7; end else begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end else begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end else begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end end end end end end end end 3'd4: begin if (sdram_choose_cmd_request[5]) begin sdram_choose_cmd_grant <= 3'd5; end else begin if (sdram_choose_cmd_request[6]) begin sdram_choose_cmd_grant <= 3'd6; end else begin if (sdram_choose_cmd_request[7]) begin sdram_choose_cmd_grant <= 3'd7; end else begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end else begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end else begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end else begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end end end end end end end end 3'd5: begin if (sdram_choose_cmd_request[6]) begin sdram_choose_cmd_grant <= 3'd6; end else begin if (sdram_choose_cmd_request[7]) begin sdram_choose_cmd_grant <= 3'd7; end else begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end else begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end else begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end else begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end else begin if (sdram_choose_cmd_request[4]) begin sdram_choose_cmd_grant <= 3'd4; end end end end end end end end 3'd6: begin if (sdram_choose_cmd_request[7]) begin sdram_choose_cmd_grant <= 3'd7; end else begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end else begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end else begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end else begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end else begin if (sdram_choose_cmd_request[4]) begin sdram_choose_cmd_grant <= 3'd4; end else begin if (sdram_choose_cmd_request[5]) begin sdram_choose_cmd_grant <= 3'd5; end end end end end end end end 3'd7: begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end else begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end else begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end else begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end else begin if (sdram_choose_cmd_request[4]) begin sdram_choose_cmd_grant <= 3'd4; end else begin if (sdram_choose_cmd_request[5]) begin sdram_choose_cmd_grant <= 3'd5; end else begin if (sdram_choose_cmd_request[6]) begin sdram_choose_cmd_grant <= 3'd6; end end end end end end end end endcase end if (sdram_choose_req_ce) begin case (sdram_choose_req_grant) 1'd0: begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end else begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end else begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end else begin if (sdram_choose_req_request[4]) begin sdram_choose_req_grant <= 3'd4; end else begin if (sdram_choose_req_request[5]) begin sdram_choose_req_grant <= 3'd5; end else begin if (sdram_choose_req_request[6]) begin sdram_choose_req_grant <= 3'd6; end else begin if (sdram_choose_req_request[7]) begin sdram_choose_req_grant <= 3'd7; end end end end end end end end 1'd1: begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end else begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end else begin if (sdram_choose_req_request[4]) begin sdram_choose_req_grant <= 3'd4; end else begin if (sdram_choose_req_request[5]) begin sdram_choose_req_grant <= 3'd5; end else begin if (sdram_choose_req_request[6]) begin sdram_choose_req_grant <= 3'd6; end else begin if (sdram_choose_req_request[7]) begin sdram_choose_req_grant <= 3'd7; end else begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end end end end end end end end 2'd2: begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end else begin if (sdram_choose_req_request[4]) begin sdram_choose_req_grant <= 3'd4; end else begin if (sdram_choose_req_request[5]) begin sdram_choose_req_grant <= 3'd5; end else begin if (sdram_choose_req_request[6]) begin sdram_choose_req_grant <= 3'd6; end else begin if (sdram_choose_req_request[7]) begin sdram_choose_req_grant <= 3'd7; end else begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end else begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end end end end end end end end 2'd3: begin if (sdram_choose_req_request[4]) begin sdram_choose_req_grant <= 3'd4; end else begin if (sdram_choose_req_request[5]) begin sdram_choose_req_grant <= 3'd5; end else begin if (sdram_choose_req_request[6]) begin sdram_choose_req_grant <= 3'd6; end else begin if (sdram_choose_req_request[7]) begin sdram_choose_req_grant <= 3'd7; end else begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end else begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end else begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end end end end end end end end 3'd4: begin if (sdram_choose_req_request[5]) begin sdram_choose_req_grant <= 3'd5; end else begin if (sdram_choose_req_request[6]) begin sdram_choose_req_grant <= 3'd6; end else begin if (sdram_choose_req_request[7]) begin sdram_choose_req_grant <= 3'd7; end else begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end else begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end else begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end else begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end end end end end end end end 3'd5: begin if (sdram_choose_req_request[6]) begin sdram_choose_req_grant <= 3'd6; end else begin if (sdram_choose_req_request[7]) begin sdram_choose_req_grant <= 3'd7; end else begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end else begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end else begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end else begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end else begin if (sdram_choose_req_request[4]) begin sdram_choose_req_grant <= 3'd4; end end end end end end end end 3'd6: begin if (sdram_choose_req_request[7]) begin sdram_choose_req_grant <= 3'd7; end else begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end else begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end else begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end else begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end else begin if (sdram_choose_req_request[4]) begin sdram_choose_req_grant <= 3'd4; end else begin if (sdram_choose_req_request[5]) begin sdram_choose_req_grant <= 3'd5; end end end end end end end end 3'd7: begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end else begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end else begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end else begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end else begin if (sdram_choose_req_request[4]) begin sdram_choose_req_grant <= 3'd4; end else begin if (sdram_choose_req_request[5]) begin sdram_choose_req_grant <= 3'd5; end else begin if (sdram_choose_req_request[6]) begin sdram_choose_req_grant <= 3'd6; end end end end end end end end endcase end sdram_dfi_p0_cs_n <= 1'd0; sdram_dfi_p0_bank <= array_muxed0; sdram_dfi_p0_address <= array_muxed1; sdram_dfi_p0_cas_n <= (~array_muxed2); sdram_dfi_p0_ras_n <= (~array_muxed3); sdram_dfi_p0_we_n <= (~array_muxed4); sdram_dfi_p0_rddata_en <= array_muxed5; sdram_dfi_p0_wrdata_en <= array_muxed6; sdram_dfi_p1_cs_n <= 1'd0; sdram_dfi_p1_bank <= array_muxed7; sdram_dfi_p1_address <= array_muxed8; sdram_dfi_p1_cas_n <= (~array_muxed9); sdram_dfi_p1_ras_n <= (~array_muxed10); sdram_dfi_p1_we_n <= (~array_muxed11); sdram_dfi_p1_rddata_en <= array_muxed12; sdram_dfi_p1_wrdata_en <= array_muxed13; sdram_dfi_p2_cs_n <= 1'd0; sdram_dfi_p2_bank <= array_muxed14; sdram_dfi_p2_address <= array_muxed15; sdram_dfi_p2_cas_n <= (~array_muxed16); sdram_dfi_p2_ras_n <= (~array_muxed17); sdram_dfi_p2_we_n <= (~array_muxed18); sdram_dfi_p2_rddata_en <= array_muxed19; sdram_dfi_p2_wrdata_en <= array_muxed20; sdram_dfi_p3_cs_n <= 1'd0; sdram_dfi_p3_bank <= array_muxed21; sdram_dfi_p3_address <= array_muxed22; sdram_dfi_p3_cas_n <= (~array_muxed23); sdram_dfi_p3_ras_n <= (~array_muxed24); sdram_dfi_p3_we_n <= (~array_muxed25); sdram_dfi_p3_rddata_en <= array_muxed26; sdram_dfi_p3_wrdata_en <= array_muxed27; if (sdram_trrdcon_valid) begin sdram_trrdcon_count <= 1'd1; if (1'd0) begin sdram_trrdcon_ready <= 1'd1; end else begin sdram_trrdcon_ready <= 1'd0; end end else begin if ((~sdram_trrdcon_ready)) begin sdram_trrdcon_count <= (sdram_trrdcon_count - 1'd1); if ((sdram_trrdcon_count == 1'd1)) begin sdram_trrdcon_ready <= 1'd1; end end end sdram_tfawcon_window <= {sdram_tfawcon_window, sdram_tfawcon_valid}; if ((sdram_tfawcon_count < 3'd4)) begin if ((sdram_tfawcon_count == 2'd3)) begin sdram_tfawcon_ready <= (~sdram_tfawcon_valid); end else begin sdram_tfawcon_ready <= 1'd1; end end if (sdram_tccdcon_valid) begin sdram_tccdcon_count <= 1'd0; if (1'd1) begin sdram_tccdcon_ready <= 1'd1; end else begin sdram_tccdcon_ready <= 1'd0; end end else begin if ((~sdram_tccdcon_ready)) begin sdram_tccdcon_count <= (sdram_tccdcon_count - 1'd1); if ((sdram_tccdcon_count == 1'd1)) begin sdram_tccdcon_ready <= 1'd1; end end end if (sdram_twtrcon_valid) begin sdram_twtrcon_count <= 3'd4; if (1'd0) begin sdram_twtrcon_ready <= 1'd1; end else begin sdram_twtrcon_ready <= 1'd0; end end else begin if ((~sdram_twtrcon_ready)) begin sdram_twtrcon_count <= (sdram_twtrcon_count - 1'd1); if ((sdram_twtrcon_count == 1'd1)) begin sdram_twtrcon_ready <= 1'd1; end end end subfragments_multiplexer_state <= subfragments_multiplexer_next_state; subfragments_new_master_wdata_ready0 <= ((((((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_wdata_ready)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_wdata_ready)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_wdata_ready)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_wdata_ready)) | ((subfragments_roundrobin4_grant == 1'd0) & sdram_interface_bank4_wdata_ready)) | ((subfragments_roundrobin5_grant == 1'd0) & sdram_interface_bank5_wdata_ready)) | ((subfragments_roundrobin6_grant == 1'd0) & sdram_interface_bank6_wdata_ready)) | ((subfragments_roundrobin7_grant == 1'd0) & sdram_interface_bank7_wdata_ready)); subfragments_new_master_wdata_ready1 <= subfragments_new_master_wdata_ready0; subfragments_new_master_rdata_valid0 <= ((((((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_rdata_valid)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_rdata_valid)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_rdata_valid)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_rdata_valid)) | ((subfragments_roundrobin4_grant == 1'd0) & sdram_interface_bank4_rdata_valid)) | ((subfragments_roundrobin5_grant == 1'd0) & sdram_interface_bank5_rdata_valid)) | ((subfragments_roundrobin6_grant == 1'd0) & sdram_interface_bank6_rdata_valid)) | ((subfragments_roundrobin7_grant == 1'd0) & sdram_interface_bank7_rdata_valid)); subfragments_new_master_rdata_valid1 <= subfragments_new_master_rdata_valid0; subfragments_new_master_rdata_valid2 <= subfragments_new_master_rdata_valid1; subfragments_new_master_rdata_valid3 <= subfragments_new_master_rdata_valid2; subfragments_new_master_rdata_valid4 <= subfragments_new_master_rdata_valid3; subfragments_new_master_rdata_valid5 <= subfragments_new_master_rdata_valid4; subfragments_new_master_rdata_valid6 <= subfragments_new_master_rdata_valid5; subfragments_new_master_rdata_valid7 <= subfragments_new_master_rdata_valid6; subfragments_new_master_rdata_valid8 <= subfragments_new_master_rdata_valid7; adr_offset_r <= wb_sdram_adr[1:0]; subfragments_fullmemorywe_state <= subfragments_fullmemorywe_next_state; if (interface_ack) begin cmd_consumed <= 1'd0; wdata_consumed <= 1'd0; end else begin if ((port_cmd_valid & port_cmd_ready)) begin cmd_consumed <= 1'd1; end if ((port_wdata_valid & port_wdata_ready)) begin wdata_consumed <= 1'd1; end end a7litesataphy_tx_init_gttxreset0 <= a7litesataphy_tx_init_gttxreset1; a7litesataphy_tx_init_gttxpd0 <= a7litesataphy_tx_init_gttxpd1; a7litesataphy_tx_init_txdlysreset0 <= a7litesataphy_tx_init_txdlysreset1; a7litesataphy_tx_init_txphinit0 <= a7litesataphy_tx_init_txphinit1; a7litesataphy_tx_init_txphalign0 <= a7litesataphy_tx_init_txphalign1; a7litesataphy_tx_init_txdlyen0 <= a7litesataphy_tx_init_txdlyen1; a7litesataphy_tx_init_txuserrdy0 <= a7litesataphy_tx_init_txuserrdy1; a7litesataphy_tx_init_txphaligndone_r <= a7litesataphy_tx_init_txphaligndone1; subfragments_litesataphy_gtptxinit_state <= subfragments_litesataphy_gtptxinit_next_state; if (a7litesataphy_tx_init_reset) begin subfragments_litesataphy_gtptxinit_state <= 4'd0; end if (a7litesataphy_tx_init_init_delay_wait) begin if ((~a7litesataphy_tx_init_init_delay_done)) begin a7litesataphy_tx_init_init_delay_count <= (a7litesataphy_tx_init_init_delay_count - 1'd1); end end else begin a7litesataphy_tx_init_init_delay_count <= 6'd40; end if (a7litesataphy_tx_init_watchdog_wait) begin if ((~a7litesataphy_tx_init_watchdog_done)) begin a7litesataphy_tx_init_watchdog_count <= (a7litesataphy_tx_init_watchdog_count - 1'd1); end end else begin a7litesataphy_tx_init_watchdog_count <= 17'd80000; end a7litesataphy_rx_init_rxpmaresetdone_r <= a7litesataphy_rx_init_rxpmaresetdone1; a7litesataphy_rx_init_gtrxreset0 <= a7litesataphy_rx_init_gtrxreset1; a7litesataphy_rx_init_gtrxpd0 <= a7litesataphy_rx_init_gtrxpd1; a7litesataphy_rx_init_rxdlysreset0 <= a7litesataphy_rx_init_rxdlysreset1; a7litesataphy_rx_init_rxphalign0 <= a7litesataphy_rx_init_rxphalign1; a7litesataphy_rx_init_rxuserrdy0 <= a7litesataphy_rx_init_rxuserrdy1; subfragments_litesataphy_gtprxinit_state <= subfragments_litesataphy_gtprxinit_next_state; if (a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value_ce) begin a7litesataphy_rx_init_drpvalue <= a7litesataphy_rx_init_drpvalue_subfragments_a7litesataphy_next_value; end if (a7litesataphy_rx_init_reset) begin a7litesataphy_rx_init_drpvalue <= 16'd0; subfragments_litesataphy_gtprxinit_state <= 4'd0; end if (a7litesataphy_rx_init_init_delay_wait) begin if ((~a7litesataphy_rx_init_init_delay_done)) begin a7litesataphy_rx_init_init_delay_count <= (a7litesataphy_rx_init_init_delay_count - 1'd1); end end else begin a7litesataphy_rx_init_init_delay_count <= 6'd40; end if (a7litesataphy_rx_init_watchdog_wait) begin if ((~a7litesataphy_rx_init_watchdog_done)) begin a7litesataphy_rx_init_watchdog_count <= (a7litesataphy_rx_init_watchdog_count - 1'd1); end end else begin a7litesataphy_rx_init_watchdog_count <= 19'd320000; end a7litesataphy_i_d0 <= a7litesataphy_tx_cominit_stb; a7litesataphy_i_d1 <= a7litesataphy_tx_comwake_stb; if (a7litesataphy_pulsesynchronizer0_i) begin a7litesataphy_pulsesynchronizer0_toggle_i <= (~a7litesataphy_pulsesynchronizer0_toggle_i); end if (a7litesataphy_pulsesynchronizer1_i) begin a7litesataphy_pulsesynchronizer1_toggle_i <= (~a7litesataphy_pulsesynchronizer1_toggle_i); end a7litesataphy_pulsesynchronizer2_toggle_o_r <= a7litesataphy_pulsesynchronizer2_toggle_o; a7litesataphy_tx_idle <= ctrl_tx_idle; crg_rx_reset <= ctrl_rx_reset; crg_tx_reset <= ctrl_tx_reset; if (ctrl_align_timer_wait) begin if ((~ctrl_align_timer_done)) begin ctrl_align_timer_count <= (ctrl_align_timer_count - 1'd1); end end else begin ctrl_align_timer_count <= 17'd69840; end if (ctrl_retry_timer_wait) begin if ((~ctrl_retry_timer_done)) begin ctrl_retry_timer_count <= (ctrl_retry_timer_count - 1'd1); end end else begin ctrl_retry_timer_count <= 20'd800000; end subfragments_litesataphy_state <= subfragments_litesataphy_next_state; if (ctrl_align_count_subfragments_litesataphyctrl_next_value_ce0) begin ctrl_align_count <= ctrl_align_count_subfragments_litesataphyctrl_next_value0; end if (a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value_ce1) begin a7litesataphy_rx_polarity <= a7litesataphy_rx_polarity_subfragments_litesataphyctrl_next_value1; end if (a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value_ce2) begin a7litesataphy_tx_polarity <= a7litesataphy_tx_polarity_subfragments_litesataphyctrl_next_value2; end if (ctrl_reset) begin a7litesataphy_tx_polarity <= 1'd0; a7litesataphy_rx_polarity <= 1'd0; ctrl_align_count <= 4'd0; subfragments_litesataphy_state <= 4'd0; end if (ctrl_stability_timer_wait) begin if ((~ctrl_stability_timer_done)) begin ctrl_stability_timer_count <= (ctrl_stability_timer_count - 1'd1); end end else begin ctrl_stability_timer_count <= 19'd400000; end datapath_tx_fifo_graycounter0_q_binary <= datapath_tx_fifo_graycounter0_q_next_binary; datapath_tx_fifo_graycounter0_q <= datapath_tx_fifo_graycounter0_q_next; datapath_rx_fifo_graycounter1_q_binary <= datapath_rx_fifo_graycounter1_q_next_binary; datapath_rx_fifo_graycounter1_q <= datapath_rx_fifo_graycounter1_q_next; if (datapath_align_timer_wait) begin if ((~datapath_align_timer_done)) begin datapath_align_timer_count <= (datapath_align_timer_count - 1'd1); end end else begin datapath_align_timer_count <= 13'd4096; end if ((~(link_litesatalinktx_fsm_is_ongoing0 | link_litesatalinktx_fsm_is_ongoing1))) begin link_litesatalinktx_error <= (link_litesatalinktx_from_rx_payload_primitive_valid & (link_litesatalinktx_from_rx_payload_primitive == 32'd3048576380)); end if (link_litesatalinktx_crc_ce) begin link_litesatalinktx_crc_reg_i <= link_litesatalinktx_crc_next; end if (link_litesatalinktx_crc_reset) begin link_litesatalinktx_crc_reg_i <= 32'd1379029042; end subfragments_litesatalinktx_litesatacrcinserter_state <= subfragments_litesatalinktx_litesatacrcinserter_next_state; if (link_litesatalinktx_scrambler_ce) begin link_litesatalinktx_scrambler_context <= link_litesatalinktx_scrambler_next_value[31:16]; end if (link_litesatalinktx_scrambler_reset) begin link_litesatalinktx_scrambler_context <= 16'd61686; end subfragments_litesatalinktx_fsm_state <= subfragments_litesatalinktx_fsm_next_state; if (((~link_tx_source_valid) | link_tx_source_ready)) begin link_tx_source_valid <= link_tx_sink_valid; link_tx_source_first <= link_tx_sink_first; link_tx_source_last <= link_tx_sink_last; link_tx_source_payload_data <= link_tx_sink_payload_data; link_tx_source_payload_charisk <= link_tx_sink_payload_charisk; end if ((link_tx_align_source_valid & link_tx_align_source_ready)) begin link_tx_align_cnt <= (link_tx_align_cnt + 1'd1); end if ((link_rx_cont_sink_valid & link_rx_cont_sink_ready)) begin if (link_rx_cont_is_cont) begin link_rx_cont_in_cont <= 1'd1; end else begin if ((~link_rx_cont_is_data)) begin link_rx_cont_in_cont <= 1'd0; end end end if ((link_rx_cont_sink_valid & link_rx_cont_sink_ready)) begin if (((~link_rx_cont_is_data) & (~link_rx_cont_is_cont))) begin link_rx_cont_last_primitive <= link_rx_cont_sink_payload_data; end end if (((link_litesatalinkrx_crc_source_source_valid & link_litesatalinkrx_crc_source_source_last) & link_litesatalinkrx_crc_source_source_ready)) begin link_litesatalinkrx_crc_error <= link_litesatalinkrx_crc_source_source_payload_error; end if (link_litesatalinkrx_data_valid) begin link_litesatalinkrx_descrambler_sink_payload_data <= link_litesatalinkrx_sink_sink_payload_data; end if (link_litesatalinkrx_descrambler_ce) begin link_litesatalinkrx_descrambler_context <= link_litesatalinkrx_descrambler_next_value[31:16]; end if (link_litesatalinkrx_descrambler_reset) begin link_litesatalinkrx_descrambler_context <= 16'd61686; end if (link_litesatalinkrx_crc_crc_ce) begin link_litesatalinkrx_crc_crc_reg_i <= link_litesatalinkrx_crc_crc_next; end if (link_litesatalinkrx_crc_crc_reset) begin link_litesatalinkrx_crc_crc_reg_i <= 32'd1379029042; end if (((link_litesatalinkrx_crc_syncfifo_syncfifo_we & link_litesatalinkrx_crc_syncfifo_syncfifo_writable) & (~link_litesatalinkrx_crc_syncfifo_replace))) begin link_litesatalinkrx_crc_syncfifo_produce <= (link_litesatalinkrx_crc_syncfifo_produce + 1'd1); end if (link_litesatalinkrx_crc_syncfifo_do_read) begin link_litesatalinkrx_crc_syncfifo_consume <= (link_litesatalinkrx_crc_syncfifo_consume + 1'd1); end if (((link_litesatalinkrx_crc_syncfifo_syncfifo_we & link_litesatalinkrx_crc_syncfifo_syncfifo_writable) & (~link_litesatalinkrx_crc_syncfifo_replace))) begin if ((~link_litesatalinkrx_crc_syncfifo_do_read)) begin link_litesatalinkrx_crc_syncfifo_level <= (link_litesatalinkrx_crc_syncfifo_level + 1'd1); end end else begin if (link_litesatalinkrx_crc_syncfifo_do_read) begin link_litesatalinkrx_crc_syncfifo_level <= (link_litesatalinkrx_crc_syncfifo_level - 1'd1); end end if (link_litesatalinkrx_crc_fifo_reset) begin link_litesatalinkrx_crc_syncfifo_level <= 2'd0; link_litesatalinkrx_crc_syncfifo_produce <= 1'd0; link_litesatalinkrx_crc_syncfifo_consume <= 1'd0; end subfragments_litesatalinkrx_litesatacrcchecker_state <= subfragments_litesatalinkrx_litesatacrcchecker_next_state; subfragments_litesatalinkrx_fsm_state <= subfragments_litesatalinkrx_fsm_next_state; if (((~link_rx_source_valid) | link_rx_source_ready)) begin link_rx_source_valid <= link_rx_sink_valid; link_rx_source_first <= link_rx_sink_first; link_rx_source_last <= link_rx_sink_last; link_rx_source_payload_data <= link_rx_sink_payload_data; link_rx_source_payload_charisk <= link_rx_sink_payload_charisk; end if (((link_rx_buffer_syncfifo_we & link_rx_buffer_syncfifo_writable) & (~link_rx_buffer_replace))) begin link_rx_buffer_produce <= (link_rx_buffer_produce + 1'd1); end if (link_rx_buffer_do_read) begin link_rx_buffer_consume <= (link_rx_buffer_consume + 1'd1); end if (((link_rx_buffer_syncfifo_we & link_rx_buffer_syncfifo_writable) & (~link_rx_buffer_replace))) begin if ((~link_rx_buffer_do_read)) begin link_rx_buffer_level <= (link_rx_buffer_level + 1'd1); end end else begin if (link_rx_buffer_do_read) begin link_rx_buffer_level <= (link_rx_buffer_level - 1'd1); end end if (transport_tx_counter_reset) begin transport_tx_counter <= 1'd0; end else begin if (transport_tx_counter_ce) begin transport_tx_counter <= (transport_tx_counter + 1'd1); end end if (transport_tx_update_fis_type) begin transport_tx_fis_type <= link_rx_buffer_source_payload_data[7:0]; end subfragments_litesatatransporttx_state <= subfragments_litesatatransporttx_next_state; if (transport_rx_counter_reset) begin transport_rx_counter <= 1'd0; end else begin if (transport_rx_counter_ce) begin transport_rx_counter <= (transport_rx_counter + 1'd1); end end if (transport_rx_update_fis_type) begin transport_rx_fis_type <= link_rx_buffer_source_payload_data[7:0]; end if (transport_rx_cmd_receive) begin case (transport_rx_counter) 1'd0: begin transport_rx_encoded_cmd[31:0] <= link_rx_buffer_source_payload_data; end 1'd1: begin transport_rx_encoded_cmd[63:32] <= link_rx_buffer_source_payload_data; end 2'd2: begin transport_rx_encoded_cmd[95:64] <= link_rx_buffer_source_payload_data; end 2'd3: begin transport_rx_encoded_cmd[127:96] <= link_rx_buffer_source_payload_data; end 3'd4: begin transport_rx_encoded_cmd[159:128] <= link_rx_buffer_source_payload_data; end endcase end subfragments_litesatatransportrx_state <= subfragments_litesatatransportrx_next_state; if (command_tx_is_ongoing0) begin command_tx_is_write <= command_tx_sink_param_write; command_tx_is_read <= command_tx_sink_param_read; command_tx_is_identify <= command_tx_sink_param_identify; end subfragments_litesatacommandtx_state <= subfragments_litesatacommandtx_next_state; if (command_tx_dwords_counter_subfragments_litesatacommandtx_next_value_ce) begin command_tx_dwords_counter <= command_tx_dwords_counter_subfragments_litesatacommandtx_next_value; end if (command_rx_from_tx_payload_read) begin command_rx_read_ndwords <= ((command_rx_from_tx_payload_count * 8'd128) - 1'd1); end if (command_rx_clr_d2h_error) begin command_rx_d2h_error <= 1'd0; end else begin if (command_rx_set_d2h_error) begin command_rx_d2h_error <= 1'd1; end end if (command_rx_clr_read_error) begin command_rx_read_error <= 1'd0; end else begin if (command_rx_set_read_error) begin command_rx_read_error <= 1'd1; end end if (command_rx_update_d2h) begin command_rx_d2h_status <= transport_rx_source_param_status; command_rx_d2h_errors <= transport_rx_source_param_errors; end if (command_rx_is_ongoing) begin command_rx_is_identify <= command_rx_from_tx_payload_identify; end subfragments_litesatacommandrx_state <= subfragments_litesatacommandrx_next_state; if (command_rx_dwords_counter_subfragments_litesatacommandrx_next_value_ce) begin command_rx_dwords_counter <= command_rx_dwords_counter_subfragments_litesatacommandrx_next_value; end if (subfragments_done0) begin subfragments_ongoing0 <= 1'd0; end else begin if (litesatauserport0_sink_valid) begin subfragments_ongoing0 <= 1'd1; end end if (subfragments_done1) begin subfragments_ongoing1 <= 1'd0; end else begin if (litesatauserport1_sink_valid) begin subfragments_ongoing1 <= 1'd1; end end case (subfragments_grant) 1'd0: begin if ((~subfragments_request[0])) begin if (subfragments_request[1]) begin subfragments_grant <= 1'd1; end end end 1'd1: begin if ((~subfragments_request[1])) begin if (subfragments_request[0]) begin subfragments_grant <= 1'd0; end end end endcase if (((sata_sector2mem_buf_syncfifo_we & sata_sector2mem_buf_syncfifo_writable) & (~sata_sector2mem_buf_replace))) begin sata_sector2mem_buf_produce <= (sata_sector2mem_buf_produce + 1'd1); end if (sata_sector2mem_buf_do_read) begin sata_sector2mem_buf_consume <= (sata_sector2mem_buf_consume + 1'd1); end if (((sata_sector2mem_buf_syncfifo_we & sata_sector2mem_buf_syncfifo_writable) & (~sata_sector2mem_buf_replace))) begin if ((~sata_sector2mem_buf_do_read)) begin sata_sector2mem_buf_level <= (sata_sector2mem_buf_level + 1'd1); end end else begin if (sata_sector2mem_buf_do_read) begin sata_sector2mem_buf_level <= (sata_sector2mem_buf_level - 1'd1); end end subfragments_litesatasector2memdma_state <= subfragments_litesatasector2memdma_next_state; if (sata_sector2mem_count_subfragments_next_value_ce0) begin sata_sector2mem_count <= sata_sector2mem_count_subfragments_next_value0; end if (sata_sector2mem_error_status_subfragments_next_value_ce1) begin sata_sector2mem_error_status <= sata_sector2mem_error_status_subfragments_next_value1; end subfragments_wishbonedmareader_state <= subfragments_wishbonedmareader_next_state; if (sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value_ce) begin sata_mem2sector_dma_data <= sata_mem2sector_dma_data_subfragments_wishbonedmareader_next_value; end if (((sata_mem2sector_buf_syncfifo_we & sata_mem2sector_buf_syncfifo_writable) & (~sata_mem2sector_buf_replace))) begin sata_mem2sector_buf_produce <= (sata_mem2sector_buf_produce + 1'd1); end if (sata_mem2sector_buf_do_read) begin sata_mem2sector_buf_consume <= (sata_mem2sector_buf_consume + 1'd1); end if (((sata_mem2sector_buf_syncfifo_we & sata_mem2sector_buf_syncfifo_writable) & (~sata_mem2sector_buf_replace))) begin if ((~sata_mem2sector_buf_do_read)) begin sata_mem2sector_buf_level <= (sata_mem2sector_buf_level + 1'd1); end end else begin if (sata_mem2sector_buf_do_read) begin sata_mem2sector_buf_level <= (sata_mem2sector_buf_level - 1'd1); end end subfragments_fsm_state <= subfragments_fsm_next_state; if (sata_mem2sector_count_subfragments_fsm_next_value_ce0) begin sata_mem2sector_count <= sata_mem2sector_count_subfragments_fsm_next_value0; end if (sata_mem2sector_error_status_subfragments_fsm_next_value_ce1) begin sata_mem2sector_error_status <= sata_mem2sector_error_status_subfragments_fsm_next_value1; end if (done) begin chaser <= {chaser, (~chaser[7])}; end if (re) begin mode <= 1'd1; end if (wait_1) begin if ((~done)) begin count <= (count - 1'd1); end end else begin count <= 23'd5000000; end basesoc_state <= basesoc_next_state; if (basesoc_basesoc_dat_w_basesoc_next_value_ce0) begin basesoc_basesoc_dat_w <= basesoc_basesoc_dat_w_basesoc_next_value0; end if (basesoc_basesoc_adr_basesoc_next_value_ce1) begin basesoc_basesoc_adr <= basesoc_basesoc_adr_basesoc_next_value1; end if (basesoc_basesoc_we_basesoc_next_value_ce2) begin basesoc_basesoc_we <= basesoc_basesoc_we_basesoc_next_value2; end case (basesoc_grant) 1'd0: begin if ((~basesoc_request[0])) begin if (basesoc_request[1]) begin basesoc_grant <= 1'd1; end else begin if (basesoc_request[2]) begin basesoc_grant <= 2'd2; end else begin if (basesoc_request[3]) begin basesoc_grant <= 2'd3; end end end end end 1'd1: begin if ((~basesoc_request[1])) begin if (basesoc_request[2]) begin basesoc_grant <= 2'd2; end else begin if (basesoc_request[3]) begin basesoc_grant <= 2'd3; end else begin if (basesoc_request[0]) begin basesoc_grant <= 1'd0; end end end end end 2'd2: begin if ((~basesoc_request[2])) begin if (basesoc_request[3]) begin basesoc_grant <= 2'd3; end else begin if (basesoc_request[0]) begin basesoc_grant <= 1'd0; end else begin if (basesoc_request[1]) begin basesoc_grant <= 1'd1; end end end end end 2'd3: begin if ((~basesoc_request[3])) begin if (basesoc_request[0]) begin basesoc_grant <= 1'd0; end else begin if (basesoc_request[1]) begin basesoc_grant <= 1'd1; end else begin if (basesoc_request[2]) begin basesoc_grant <= 2'd2; end end end end end endcase basesoc_slave_sel_r <= basesoc_slave_sel; if (basesoc_wait) begin if ((~basesoc_done)) begin basesoc_count <= (basesoc_count - 1'd1); end end else begin basesoc_count <= 20'd1000000; end basesoc_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank0_sel) begin case (basesoc_csr_bankarray_interface0_bank_bus_adr[1:0]) 1'd0: begin basesoc_csr_bankarray_interface0_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank0_reset0_w; end 1'd1: begin basesoc_csr_bankarray_interface0_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank0_scratch0_w; end 2'd2: begin basesoc_csr_bankarray_interface0_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank0_bus_errors_w; end endcase end if (basesoc_csr_bankarray_csrbank0_reset0_re) begin soccontroller_reset_storage <= basesoc_csr_bankarray_csrbank0_reset0_r; end soccontroller_reset_re <= basesoc_csr_bankarray_csrbank0_reset0_re; if (basesoc_csr_bankarray_csrbank0_scratch0_re) begin soccontroller_scratch_storage[31:0] <= basesoc_csr_bankarray_csrbank0_scratch0_r; end soccontroller_scratch_re <= basesoc_csr_bankarray_csrbank0_scratch0_re; soccontroller_bus_errors_re <= basesoc_csr_bankarray_csrbank0_bus_errors_re; basesoc_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank1_sel) begin case (basesoc_csr_bankarray_interface1_bank_bus_adr[3:0]) 1'd0: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_rst0_w; end 1'd1: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_w; end 2'd2: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_wlevel_en0_w; end 2'd3: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; end 3'd4: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_dly_sel0_w; end 3'd5: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; end 3'd6: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; end 3'd7: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd8: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; end 4'd9: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; end 4'd10: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; end 4'd11: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_rdphase0_w; end 4'd12: begin basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_wrphase0_w; end endcase end if (basesoc_csr_bankarray_csrbank1_rst0_re) begin a7ddrphy_rst_storage <= basesoc_csr_bankarray_csrbank1_rst0_r; end a7ddrphy_rst_re <= basesoc_csr_bankarray_csrbank1_rst0_re; if (basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_re) begin a7ddrphy_half_sys8x_taps_storage[4:0] <= basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_r; end a7ddrphy_half_sys8x_taps_re <= basesoc_csr_bankarray_csrbank1_half_sys8x_taps0_re; if (basesoc_csr_bankarray_csrbank1_wlevel_en0_re) begin a7ddrphy_wlevel_en_storage <= basesoc_csr_bankarray_csrbank1_wlevel_en0_r; end a7ddrphy_wlevel_en_re <= basesoc_csr_bankarray_csrbank1_wlevel_en0_re; if (basesoc_csr_bankarray_csrbank1_dly_sel0_re) begin a7ddrphy_dly_sel_storage[1:0] <= basesoc_csr_bankarray_csrbank1_dly_sel0_r; end a7ddrphy_dly_sel_re <= basesoc_csr_bankarray_csrbank1_dly_sel0_re; if (basesoc_csr_bankarray_csrbank1_rdphase0_re) begin a7ddrphy_rdphase_storage[1:0] <= basesoc_csr_bankarray_csrbank1_rdphase0_r; end a7ddrphy_rdphase_re <= basesoc_csr_bankarray_csrbank1_rdphase0_re; if (basesoc_csr_bankarray_csrbank1_wrphase0_re) begin a7ddrphy_wrphase_storage[1:0] <= basesoc_csr_bankarray_csrbank1_wrphase0_r; end a7ddrphy_wrphase_re <= basesoc_csr_bankarray_csrbank1_wrphase0_re; basesoc_csr_bankarray_sel_r <= basesoc_csr_bankarray_sel; basesoc_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank2_sel) begin case (basesoc_csr_bankarray_interface2_bank_bus_adr[0]) 1'd0: begin basesoc_csr_bankarray_interface2_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank2_out0_w; end endcase end if (basesoc_csr_bankarray_csrbank2_out0_re) begin storage[7:0] <= basesoc_csr_bankarray_csrbank2_out0_r; end re <= basesoc_csr_bankarray_csrbank2_out0_re; basesoc_csr_bankarray_interface3_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank3_sel) begin case (basesoc_csr_bankarray_interface3_bank_bus_adr[2:0]) 1'd0: begin basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_sector1_w; end 1'd1: begin basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_sector0_w; end 2'd2: begin basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_base1_w; end 2'd3: begin basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_base0_w; end 3'd4: begin basesoc_csr_bankarray_interface3_bank_bus_dat_r <= sata_mem2sector_start_w; end 3'd5: begin basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_done_w; end 3'd6: begin basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_error_w; end endcase end if (basesoc_csr_bankarray_csrbank3_sector1_re) begin sata_mem2sector_sector_storage[47:32] <= basesoc_csr_bankarray_csrbank3_sector1_r; end if (basesoc_csr_bankarray_csrbank3_sector0_re) begin sata_mem2sector_sector_storage[31:0] <= basesoc_csr_bankarray_csrbank3_sector0_r; end sata_mem2sector_sector_re <= basesoc_csr_bankarray_csrbank3_sector0_re; if (basesoc_csr_bankarray_csrbank3_base1_re) begin sata_mem2sector_base_storage[63:32] <= basesoc_csr_bankarray_csrbank3_base1_r; end if (basesoc_csr_bankarray_csrbank3_base0_re) begin sata_mem2sector_base_storage[31:0] <= basesoc_csr_bankarray_csrbank3_base0_r; end sata_mem2sector_base_re <= basesoc_csr_bankarray_csrbank3_base0_re; sata_mem2sector_done_re <= basesoc_csr_bankarray_csrbank3_done_re; sata_mem2sector_error_re <= basesoc_csr_bankarray_csrbank3_error_re; basesoc_csr_bankarray_interface4_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank4_sel) begin case (basesoc_csr_bankarray_interface4_bank_bus_adr[0]) 1'd0: begin basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_enable0_w; end 1'd1: begin basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_status_w; end endcase end if (basesoc_csr_bankarray_csrbank4_enable0_re) begin litesataphy_enable_storage <= basesoc_csr_bankarray_csrbank4_enable0_r; end litesataphy_enable_re <= basesoc_csr_bankarray_csrbank4_enable0_re; litesataphy_status_re <= basesoc_csr_bankarray_csrbank4_status_re; basesoc_csr_bankarray_interface5_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank5_sel) begin case (basesoc_csr_bankarray_interface5_bank_bus_adr[2:0]) 1'd0: begin basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_sector1_w; end 1'd1: begin basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_sector0_w; end 2'd2: begin basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_base1_w; end 2'd3: begin basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_base0_w; end 3'd4: begin basesoc_csr_bankarray_interface5_bank_bus_dat_r <= sata_sector2mem_start_w; end 3'd5: begin basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_done_w; end 3'd6: begin basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_error_w; end endcase end if (basesoc_csr_bankarray_csrbank5_sector1_re) begin sata_sector2mem_sector_storage[47:32] <= basesoc_csr_bankarray_csrbank5_sector1_r; end if (basesoc_csr_bankarray_csrbank5_sector0_re) begin sata_sector2mem_sector_storage[31:0] <= basesoc_csr_bankarray_csrbank5_sector0_r; end sata_sector2mem_sector_re <= basesoc_csr_bankarray_csrbank5_sector0_re; if (basesoc_csr_bankarray_csrbank5_base1_re) begin sata_sector2mem_base_storage[63:32] <= basesoc_csr_bankarray_csrbank5_base1_r; end if (basesoc_csr_bankarray_csrbank5_base0_re) begin sata_sector2mem_base_storage[31:0] <= basesoc_csr_bankarray_csrbank5_base0_r; end sata_sector2mem_base_re <= basesoc_csr_bankarray_csrbank5_base0_re; sata_sector2mem_done_re <= basesoc_csr_bankarray_csrbank5_done_re; sata_sector2mem_error_re <= basesoc_csr_bankarray_csrbank5_error_re; basesoc_csr_bankarray_interface6_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank6_sel) begin case (basesoc_csr_bankarray_interface6_bank_bus_adr[4:0]) 1'd0: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_control0_w; end 1'd1: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_w; end 2'd2: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= sdram_phaseinjector0_command_issue_w; end 2'd3: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_w; end 3'd4: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_w; end 3'd5: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_w; end 3'd6: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_w; end 3'd7: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_w; end 4'd8: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= sdram_phaseinjector1_command_issue_w; end 4'd9: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_w; end 4'd10: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_w; end 4'd11: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_w; end 4'd12: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_w; end 4'd13: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_w; end 4'd14: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= sdram_phaseinjector2_command_issue_w; end 4'd15: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_w; end 5'd16: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_w; end 5'd17: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_w; end 5'd18: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_w; end 5'd19: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_w; end 5'd20: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= sdram_phaseinjector3_command_issue_w; end 5'd21: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_w; end 5'd22: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_w; end 5'd23: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_w; end 5'd24: begin basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_w; end endcase end if (basesoc_csr_bankarray_csrbank6_dfii_control0_re) begin sdram_storage[3:0] <= basesoc_csr_bankarray_csrbank6_dfii_control0_r; end sdram_re <= basesoc_csr_bankarray_csrbank6_dfii_control0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_re) begin sdram_phaseinjector0_command_storage[5:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_r; end sdram_phaseinjector0_command_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_command0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_re) begin sdram_phaseinjector0_address_storage[13:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_r; end sdram_phaseinjector0_address_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_address0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_re) begin sdram_phaseinjector0_baddress_storage[2:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_r; end sdram_phaseinjector0_baddress_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_baddress0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_re) begin sdram_phaseinjector0_wrdata_storage[31:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_r; end sdram_phaseinjector0_wrdata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_wrdata0_re; sdram_phaseinjector0_rddata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi0_rddata_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_re) begin sdram_phaseinjector1_command_storage[5:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_r; end sdram_phaseinjector1_command_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_command0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_re) begin sdram_phaseinjector1_address_storage[13:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_r; end sdram_phaseinjector1_address_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_address0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_re) begin sdram_phaseinjector1_baddress_storage[2:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_r; end sdram_phaseinjector1_baddress_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_baddress0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_re) begin sdram_phaseinjector1_wrdata_storage[31:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_r; end sdram_phaseinjector1_wrdata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_wrdata0_re; sdram_phaseinjector1_rddata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi1_rddata_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_re) begin sdram_phaseinjector2_command_storage[5:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_r; end sdram_phaseinjector2_command_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_command0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_re) begin sdram_phaseinjector2_address_storage[13:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_r; end sdram_phaseinjector2_address_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_address0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_re) begin sdram_phaseinjector2_baddress_storage[2:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_r; end sdram_phaseinjector2_baddress_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_baddress0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_re) begin sdram_phaseinjector2_wrdata_storage[31:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_r; end sdram_phaseinjector2_wrdata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_wrdata0_re; sdram_phaseinjector2_rddata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi2_rddata_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_re) begin sdram_phaseinjector3_command_storage[5:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_r; end sdram_phaseinjector3_command_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_command0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_re) begin sdram_phaseinjector3_address_storage[13:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_r; end sdram_phaseinjector3_address_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_address0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_re) begin sdram_phaseinjector3_baddress_storage[2:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_r; end sdram_phaseinjector3_baddress_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_baddress0_re; if (basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_re) begin sdram_phaseinjector3_wrdata_storage[31:0] <= basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_r; end sdram_phaseinjector3_wrdata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_wrdata0_re; sdram_phaseinjector3_rddata_re <= basesoc_csr_bankarray_csrbank6_dfii_pi3_rddata_re; basesoc_csr_bankarray_interface7_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank7_sel) begin case (basesoc_csr_bankarray_interface7_bank_bus_adr[2:0]) 1'd0: begin basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_load0_w; end 1'd1: begin basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_reload0_w; end 2'd2: begin basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_en0_w; end 2'd3: begin basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_update_value0_w; end 3'd4: begin basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_value_w; end 3'd5: begin basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_status_w; end 3'd6: begin basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_pending_w; end 3'd7: begin basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_enable0_w; end endcase end if (basesoc_csr_bankarray_csrbank7_load0_re) begin timer_load_storage[31:0] <= basesoc_csr_bankarray_csrbank7_load0_r; end timer_load_re <= basesoc_csr_bankarray_csrbank7_load0_re; if (basesoc_csr_bankarray_csrbank7_reload0_re) begin timer_reload_storage[31:0] <= basesoc_csr_bankarray_csrbank7_reload0_r; end timer_reload_re <= basesoc_csr_bankarray_csrbank7_reload0_re; if (basesoc_csr_bankarray_csrbank7_en0_re) begin timer_en_storage <= basesoc_csr_bankarray_csrbank7_en0_r; end timer_en_re <= basesoc_csr_bankarray_csrbank7_en0_re; if (basesoc_csr_bankarray_csrbank7_update_value0_re) begin timer_update_value_storage <= basesoc_csr_bankarray_csrbank7_update_value0_r; end timer_update_value_re <= basesoc_csr_bankarray_csrbank7_update_value0_re; timer_value_re <= basesoc_csr_bankarray_csrbank7_value_re; timer_status_re <= basesoc_csr_bankarray_csrbank7_ev_status_re; if (basesoc_csr_bankarray_csrbank7_ev_pending_re) begin timer_pending_r <= basesoc_csr_bankarray_csrbank7_ev_pending_r; end timer_pending_re <= basesoc_csr_bankarray_csrbank7_ev_pending_re; if (basesoc_csr_bankarray_csrbank7_ev_enable0_re) begin timer_enable_storage <= basesoc_csr_bankarray_csrbank7_ev_enable0_r; end timer_enable_re <= basesoc_csr_bankarray_csrbank7_ev_enable0_re; basesoc_csr_bankarray_interface8_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank8_sel) begin case (basesoc_csr_bankarray_interface8_bank_bus_adr[2:0]) 1'd0: begin basesoc_csr_bankarray_interface8_bank_bus_dat_r <= uart_rxtx_w; end 1'd1: begin basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_txfull_w; end 2'd2: begin basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_rxempty_w; end 2'd3: begin basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_ev_status_w; end 3'd4: begin basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_ev_pending_w; end 3'd5: begin basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_ev_enable0_w; end 3'd6: begin basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_txempty_w; end 3'd7: begin basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_rxfull_w; end endcase end uart_txfull_re <= basesoc_csr_bankarray_csrbank8_txfull_re; uart_rxempty_re <= basesoc_csr_bankarray_csrbank8_rxempty_re; uart_status_re <= basesoc_csr_bankarray_csrbank8_ev_status_re; if (basesoc_csr_bankarray_csrbank8_ev_pending_re) begin uart_pending_r[1:0] <= basesoc_csr_bankarray_csrbank8_ev_pending_r; end uart_pending_re <= basesoc_csr_bankarray_csrbank8_ev_pending_re; if (basesoc_csr_bankarray_csrbank8_ev_enable0_re) begin uart_enable_storage[1:0] <= basesoc_csr_bankarray_csrbank8_ev_enable0_r; end uart_enable_re <= basesoc_csr_bankarray_csrbank8_ev_enable0_re; uart_txempty_re <= basesoc_csr_bankarray_csrbank8_txempty_re; uart_rxfull_re <= basesoc_csr_bankarray_csrbank8_rxfull_re; basesoc_csr_bankarray_interface9_bank_bus_dat_r <= 1'd0; if (basesoc_csr_bankarray_csrbank9_sel) begin case (basesoc_csr_bankarray_interface9_bank_bus_adr[0]) 1'd0: begin basesoc_csr_bankarray_interface9_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank9_tuning_word0_w; end endcase end if (basesoc_csr_bankarray_csrbank9_tuning_word0_re) begin uart_phy_storage[31:0] <= basesoc_csr_bankarray_csrbank9_tuning_word0_r; end uart_phy_re <= basesoc_csr_bankarray_csrbank9_tuning_word0_re; if (sys_rst) begin soccontroller_reset_storage <= 1'd0; soccontroller_reset_re <= 1'd0; soccontroller_scratch_storage <= 32'd305419896; soccontroller_scratch_re <= 1'd0; soccontroller_bus_errors_re <= 1'd0; soccontroller_bus_errors <= 32'd0; basesoc_ram_bus_ack <= 1'd0; ram_bus_ram_bus_ack <= 1'd0; serial_tx <= 1'd1; uart_phy_storage <= 32'd6184752; uart_phy_re <= 1'd0; uart_phy_sink_ready <= 1'd0; uart_phy_tx_clken <= 1'd0; uart_phy_tx_busy <= 1'd0; uart_phy_source_valid <= 1'd0; uart_phy_source_payload_data <= 8'd0; uart_phy_rx_clken <= 1'd0; uart_phy_rx_r <= 1'd0; uart_phy_rx_busy <= 1'd0; uart_txfull_re <= 1'd0; uart_rxempty_re <= 1'd0; uart_tx_pending <= 1'd0; uart_tx_old_trigger <= 1'd0; uart_rx_pending <= 1'd0; uart_rx_old_trigger <= 1'd0; uart_status_re <= 1'd0; uart_pending_re <= 1'd0; uart_pending_r <= 2'd0; uart_enable_storage <= 2'd0; uart_enable_re <= 1'd0; uart_txempty_re <= 1'd0; uart_rxfull_re <= 1'd0; uart_tx_fifo_readable <= 1'd0; uart_tx_fifo_level0 <= 5'd0; uart_tx_fifo_produce <= 4'd0; uart_tx_fifo_consume <= 4'd0; uart_rx_fifo_readable <= 1'd0; uart_rx_fifo_level0 <= 5'd0; uart_rx_fifo_produce <= 4'd0; uart_rx_fifo_consume <= 4'd0; timer_load_storage <= 32'd0; timer_load_re <= 1'd0; timer_reload_storage <= 32'd0; timer_reload_re <= 1'd0; timer_en_storage <= 1'd0; timer_en_re <= 1'd0; timer_update_value_storage <= 1'd0; timer_update_value_re <= 1'd0; timer_value_status <= 32'd0; timer_value_re <= 1'd0; timer_zero_pending <= 1'd0; timer_zero_old_trigger <= 1'd0; timer_status_re <= 1'd0; timer_pending_re <= 1'd0; timer_pending_r <= 1'd0; timer_enable_storage <= 1'd0; timer_enable_re <= 1'd0; timer_value <= 32'd0; a7ddrphy_rst_storage <= 1'd0; a7ddrphy_rst_re <= 1'd0; a7ddrphy_half_sys8x_taps_storage <= 5'd10; a7ddrphy_half_sys8x_taps_re <= 1'd0; a7ddrphy_wlevel_en_storage <= 1'd0; a7ddrphy_wlevel_en_re <= 1'd0; a7ddrphy_dly_sel_storage <= 2'd0; a7ddrphy_dly_sel_re <= 1'd0; a7ddrphy_rdphase_storage <= 2'd2; a7ddrphy_rdphase_re <= 1'd0; a7ddrphy_wrphase_storage <= 2'd3; a7ddrphy_wrphase_re <= 1'd0; a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; a7ddrphy_dqspattern_o1 <= 8'd0; a7ddrphy_bitslip0_value0 <= 3'd7; a7ddrphy_bitslip1_value0 <= 3'd7; a7ddrphy_bitslip0_value1 <= 3'd7; a7ddrphy_bitslip1_value1 <= 3'd7; a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; a7ddrphy_bitslip0_value2 <= 3'd7; a7ddrphy_bitslip0_value3 <= 3'd7; a7ddrphy_bitslip1_value2 <= 3'd7; a7ddrphy_bitslip1_value3 <= 3'd7; a7ddrphy_bitslip2_value0 <= 3'd7; a7ddrphy_bitslip2_value1 <= 3'd7; a7ddrphy_bitslip3_value0 <= 3'd7; a7ddrphy_bitslip3_value1 <= 3'd7; a7ddrphy_bitslip4_value0 <= 3'd7; a7ddrphy_bitslip4_value1 <= 3'd7; a7ddrphy_bitslip5_value0 <= 3'd7; a7ddrphy_bitslip5_value1 <= 3'd7; a7ddrphy_bitslip6_value0 <= 3'd7; a7ddrphy_bitslip6_value1 <= 3'd7; a7ddrphy_bitslip7_value0 <= 3'd7; a7ddrphy_bitslip7_value1 <= 3'd7; a7ddrphy_bitslip8_value0 <= 3'd7; a7ddrphy_bitslip8_value1 <= 3'd7; a7ddrphy_bitslip9_value0 <= 3'd7; a7ddrphy_bitslip9_value1 <= 3'd7; a7ddrphy_bitslip10_value0 <= 3'd7; a7ddrphy_bitslip10_value1 <= 3'd7; a7ddrphy_bitslip11_value0 <= 3'd7; a7ddrphy_bitslip11_value1 <= 3'd7; a7ddrphy_bitslip12_value0 <= 3'd7; a7ddrphy_bitslip12_value1 <= 3'd7; a7ddrphy_bitslip13_value0 <= 3'd7; a7ddrphy_bitslip13_value1 <= 3'd7; a7ddrphy_bitslip14_value0 <= 3'd7; a7ddrphy_bitslip14_value1 <= 3'd7; a7ddrphy_bitslip15_value0 <= 3'd7; a7ddrphy_bitslip15_value1 <= 3'd7; a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; sdram_storage <= 4'd1; sdram_re <= 1'd0; sdram_phaseinjector0_command_storage <= 6'd0; sdram_phaseinjector0_command_re <= 1'd0; sdram_phaseinjector0_address_re <= 1'd0; sdram_phaseinjector0_baddress_re <= 1'd0; sdram_phaseinjector0_wrdata_re <= 1'd0; sdram_phaseinjector0_rddata_status <= 32'd0; sdram_phaseinjector0_rddata_re <= 1'd0; sdram_phaseinjector1_command_storage <= 6'd0; sdram_phaseinjector1_command_re <= 1'd0; sdram_phaseinjector1_address_re <= 1'd0; sdram_phaseinjector1_baddress_re <= 1'd0; sdram_phaseinjector1_wrdata_re <= 1'd0; sdram_phaseinjector1_rddata_status <= 32'd0; sdram_phaseinjector1_rddata_re <= 1'd0; sdram_phaseinjector2_command_storage <= 6'd0; sdram_phaseinjector2_command_re <= 1'd0; sdram_phaseinjector2_address_re <= 1'd0; sdram_phaseinjector2_baddress_re <= 1'd0; sdram_phaseinjector2_wrdata_re <= 1'd0; sdram_phaseinjector2_rddata_status <= 32'd0; sdram_phaseinjector2_rddata_re <= 1'd0; sdram_phaseinjector3_command_storage <= 6'd0; sdram_phaseinjector3_command_re <= 1'd0; sdram_phaseinjector3_address_re <= 1'd0; sdram_phaseinjector3_baddress_re <= 1'd0; sdram_phaseinjector3_wrdata_re <= 1'd0; sdram_phaseinjector3_rddata_status <= 32'd0; sdram_phaseinjector3_rddata_re <= 1'd0; sdram_dfi_p0_address <= 14'd0; sdram_dfi_p0_bank <= 3'd0; sdram_dfi_p0_cas_n <= 1'd1; sdram_dfi_p0_cs_n <= 1'd1; sdram_dfi_p0_ras_n <= 1'd1; sdram_dfi_p0_we_n <= 1'd1; sdram_dfi_p0_wrdata_en <= 1'd0; sdram_dfi_p0_rddata_en <= 1'd0; sdram_dfi_p1_address <= 14'd0; sdram_dfi_p1_bank <= 3'd0; sdram_dfi_p1_cas_n <= 1'd1; sdram_dfi_p1_cs_n <= 1'd1; sdram_dfi_p1_ras_n <= 1'd1; sdram_dfi_p1_we_n <= 1'd1; sdram_dfi_p1_wrdata_en <= 1'd0; sdram_dfi_p1_rddata_en <= 1'd0; sdram_dfi_p2_address <= 14'd0; sdram_dfi_p2_bank <= 3'd0; sdram_dfi_p2_cas_n <= 1'd1; sdram_dfi_p2_cs_n <= 1'd1; sdram_dfi_p2_ras_n <= 1'd1; sdram_dfi_p2_we_n <= 1'd1; sdram_dfi_p2_wrdata_en <= 1'd0; sdram_dfi_p2_rddata_en <= 1'd0; sdram_dfi_p3_address <= 14'd0; sdram_dfi_p3_bank <= 3'd0; sdram_dfi_p3_cas_n <= 1'd1; sdram_dfi_p3_cs_n <= 1'd1; sdram_dfi_p3_ras_n <= 1'd1; sdram_dfi_p3_we_n <= 1'd1; sdram_dfi_p3_wrdata_en <= 1'd0; sdram_dfi_p3_rddata_en <= 1'd0; sdram_cmd_payload_a <= 14'd0; sdram_cmd_payload_ba <= 3'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd0; sdram_cmd_payload_we <= 1'd0; sdram_timer_count1 <= 10'd624; sdram_postponer_req_o <= 1'd0; sdram_postponer_count <= 1'd0; sdram_sequencer_done1 <= 1'd0; sdram_sequencer_counter <= 6'd0; sdram_sequencer_count <= 1'd0; sdram_zqcs_timer_count1 <= 27'd79999999; sdram_zqcs_executer_done <= 1'd0; sdram_zqcs_executer_counter <= 5'd0; sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; sdram_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0; sdram_bankmachine0_row <= 14'd0; sdram_bankmachine0_row_opened <= 1'd0; sdram_bankmachine0_twtpcon_ready <= 1'd0; sdram_bankmachine0_twtpcon_count <= 3'd0; sdram_bankmachine0_trccon_ready <= 1'd0; sdram_bankmachine0_trccon_count <= 3'd0; sdram_bankmachine0_trascon_ready <= 1'd0; sdram_bankmachine0_trascon_count <= 2'd0; sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; sdram_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0; sdram_bankmachine1_row <= 14'd0; sdram_bankmachine1_row_opened <= 1'd0; sdram_bankmachine1_twtpcon_ready <= 1'd0; sdram_bankmachine1_twtpcon_count <= 3'd0; sdram_bankmachine1_trccon_ready <= 1'd0; sdram_bankmachine1_trccon_count <= 3'd0; sdram_bankmachine1_trascon_ready <= 1'd0; sdram_bankmachine1_trascon_count <= 2'd0; sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; sdram_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0; sdram_bankmachine2_row <= 14'd0; sdram_bankmachine2_row_opened <= 1'd0; sdram_bankmachine2_twtpcon_ready <= 1'd0; sdram_bankmachine2_twtpcon_count <= 3'd0; sdram_bankmachine2_trccon_ready <= 1'd0; sdram_bankmachine2_trccon_count <= 3'd0; sdram_bankmachine2_trascon_ready <= 1'd0; sdram_bankmachine2_trascon_count <= 2'd0; sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; sdram_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0; sdram_bankmachine3_row <= 14'd0; sdram_bankmachine3_row_opened <= 1'd0; sdram_bankmachine3_twtpcon_ready <= 1'd0; sdram_bankmachine3_twtpcon_count <= 3'd0; sdram_bankmachine3_trccon_ready <= 1'd0; sdram_bankmachine3_trccon_count <= 3'd0; sdram_bankmachine3_trascon_ready <= 1'd0; sdram_bankmachine3_trascon_count <= 2'd0; sdram_bankmachine4_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine4_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine4_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; sdram_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0; sdram_bankmachine4_row <= 14'd0; sdram_bankmachine4_row_opened <= 1'd0; sdram_bankmachine4_twtpcon_ready <= 1'd0; sdram_bankmachine4_twtpcon_count <= 3'd0; sdram_bankmachine4_trccon_ready <= 1'd0; sdram_bankmachine4_trccon_count <= 3'd0; sdram_bankmachine4_trascon_ready <= 1'd0; sdram_bankmachine4_trascon_count <= 2'd0; sdram_bankmachine5_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine5_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine5_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; sdram_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0; sdram_bankmachine5_row <= 14'd0; sdram_bankmachine5_row_opened <= 1'd0; sdram_bankmachine5_twtpcon_ready <= 1'd0; sdram_bankmachine5_twtpcon_count <= 3'd0; sdram_bankmachine5_trccon_ready <= 1'd0; sdram_bankmachine5_trccon_count <= 3'd0; sdram_bankmachine5_trascon_ready <= 1'd0; sdram_bankmachine5_trascon_count <= 2'd0; sdram_bankmachine6_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine6_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine6_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; sdram_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0; sdram_bankmachine6_row <= 14'd0; sdram_bankmachine6_row_opened <= 1'd0; sdram_bankmachine6_twtpcon_ready <= 1'd0; sdram_bankmachine6_twtpcon_count <= 3'd0; sdram_bankmachine6_trccon_ready <= 1'd0; sdram_bankmachine6_trccon_count <= 3'd0; sdram_bankmachine6_trascon_ready <= 1'd0; sdram_bankmachine6_trascon_count <= 2'd0; sdram_bankmachine7_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine7_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine7_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; sdram_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0; sdram_bankmachine7_row <= 14'd0; sdram_bankmachine7_row_opened <= 1'd0; sdram_bankmachine7_twtpcon_ready <= 1'd0; sdram_bankmachine7_twtpcon_count <= 3'd0; sdram_bankmachine7_trccon_ready <= 1'd0; sdram_bankmachine7_trccon_count <= 3'd0; sdram_bankmachine7_trascon_ready <= 1'd0; sdram_bankmachine7_trascon_count <= 2'd0; sdram_choose_cmd_grant <= 3'd0; sdram_choose_req_grant <= 3'd0; sdram_trrdcon_ready <= 1'd0; sdram_trrdcon_count <= 1'd0; sdram_tfawcon_ready <= 1'd1; sdram_tfawcon_window <= 4'd0; sdram_tccdcon_ready <= 1'd0; sdram_tccdcon_count <= 1'd0; sdram_twtrcon_ready <= 1'd0; sdram_twtrcon_count <= 3'd0; sdram_time0 <= 5'd0; sdram_time1 <= 4'd0; cmd_consumed <= 1'd0; wdata_consumed <= 1'd0; a7litesataphy_tx_idle <= 1'd0; a7litesataphy_tx_polarity <= 1'd0; a7litesataphy_rx_polarity <= 1'd0; a7litesataphy_tx_init_gttxreset0 <= 1'd0; a7litesataphy_tx_init_gttxpd0 <= 1'd0; a7litesataphy_tx_init_txdlysreset0 <= 1'd0; a7litesataphy_tx_init_txphinit0 <= 1'd0; a7litesataphy_tx_init_txphalign0 <= 1'd0; a7litesataphy_tx_init_txdlyen0 <= 1'd0; a7litesataphy_tx_init_txuserrdy0 <= 1'd0; a7litesataphy_tx_init_txphaligndone_r <= 1'd1; a7litesataphy_tx_init_init_delay_count <= 6'd40; a7litesataphy_tx_init_watchdog_count <= 17'd80000; a7litesataphy_rx_init_gtrxreset0 <= 1'd0; a7litesataphy_rx_init_gtrxpd0 <= 1'd0; a7litesataphy_rx_init_rxdlysreset0 <= 1'd0; a7litesataphy_rx_init_rxphalign0 <= 1'd0; a7litesataphy_rx_init_rxuserrdy0 <= 1'd0; a7litesataphy_rx_init_drpvalue <= 16'd0; a7litesataphy_rx_init_rxpmaresetdone_r <= 1'd0; a7litesataphy_rx_init_init_delay_count <= 6'd40; a7litesataphy_rx_init_watchdog_count <= 19'd320000; a7litesataphy_i_d0 <= 1'd0; a7litesataphy_i_d1 <= 1'd0; crg_tx_reset <= 1'd0; crg_rx_reset <= 1'd0; ctrl_retry_timer_count <= 20'd800000; ctrl_align_timer_count <= 17'd69840; ctrl_align_count <= 4'd0; ctrl_stability_timer_count <= 19'd400000; datapath_tx_fifo_graycounter0_q <= 4'd0; datapath_tx_fifo_graycounter0_q_binary <= 4'd0; datapath_rx_fifo_graycounter1_q <= 4'd0; datapath_rx_fifo_graycounter1_q_binary <= 4'd0; datapath_align_timer_count <= 13'd4096; litesataphy_enable_storage <= 1'd1; litesataphy_enable_re <= 1'd0; litesataphy_status_re <= 1'd0; link_litesatalinktx_error <= 1'd0; link_litesatalinktx_crc_reg_i <= 32'd1379029042; link_litesatalinktx_scrambler_context <= 16'd61686; link_tx_source_valid <= 1'd0; link_tx_source_payload_data <= 32'd0; link_tx_source_payload_charisk <= 4'd0; link_tx_align_cnt <= 8'd0; link_rx_cont_in_cont <= 1'd0; link_rx_cont_last_primitive <= 32'd0; link_litesatalinkrx_descrambler_sink_payload_data <= 32'd0; link_litesatalinkrx_descrambler_context <= 16'd61686; link_litesatalinkrx_crc_crc_reg_i <= 32'd1379029042; link_litesatalinkrx_crc_syncfifo_level <= 2'd0; link_litesatalinkrx_crc_syncfifo_produce <= 1'd0; link_litesatalinkrx_crc_syncfifo_consume <= 1'd0; link_litesatalinkrx_crc_error <= 1'd0; link_rx_source_valid <= 1'd0; link_rx_source_payload_data <= 32'd0; link_rx_source_payload_charisk <= 4'd0; link_rx_buffer_level <= 8'd0; link_rx_buffer_produce <= 7'd0; link_rx_buffer_consume <= 7'd0; transport_tx_counter <= 3'd0; transport_tx_fis_type <= 8'd0; transport_rx_encoded_cmd <= 160'd0; transport_rx_counter <= 3'd0; transport_rx_fis_type <= 8'd0; command_tx_is_write <= 1'd0; command_tx_is_read <= 1'd0; command_tx_is_identify <= 1'd0; command_tx_dwords_counter <= 11'd0; command_rx_d2h_status <= 8'd0; command_rx_d2h_errors <= 8'd0; command_rx_is_identify <= 1'd0; command_rx_read_ndwords <= 23'd0; command_rx_dwords_counter <= 23'd0; command_rx_d2h_error <= 1'd0; command_rx_read_error <= 1'd0; sata_sector2mem_sector_storage <= 48'd0; sata_sector2mem_sector_re <= 1'd0; sata_sector2mem_base_storage <= 64'd0; sata_sector2mem_base_re <= 1'd0; sata_sector2mem_done_re <= 1'd0; sata_sector2mem_error_status <= 1'd0; sata_sector2mem_error_re <= 1'd0; sata_sector2mem_count <= 7'd0; sata_sector2mem_buf_level <= 8'd0; sata_sector2mem_buf_produce <= 7'd0; sata_sector2mem_buf_consume <= 7'd0; sata_mem2sector_sector_storage <= 48'd0; sata_mem2sector_sector_re <= 1'd0; sata_mem2sector_base_storage <= 64'd0; sata_mem2sector_base_re <= 1'd0; sata_mem2sector_done_re <= 1'd0; sata_mem2sector_error_status <= 1'd0; sata_mem2sector_error_re <= 1'd0; sata_mem2sector_count <= 7'd0; sata_mem2sector_dma_data <= 32'd0; sata_mem2sector_buf_level <= 8'd0; sata_mem2sector_buf_produce <= 7'd0; sata_mem2sector_buf_consume <= 7'd0; storage <= 8'd0; re <= 1'd0; chaser <= 8'd0; mode <= 1'd0; count <= 23'd5000000; subfragments_refresher_state <= 2'd0; subfragments_bankmachine0_state <= 3'd0; subfragments_bankmachine1_state <= 3'd0; subfragments_bankmachine2_state <= 3'd0; subfragments_bankmachine3_state <= 3'd0; subfragments_bankmachine4_state <= 3'd0; subfragments_bankmachine5_state <= 3'd0; subfragments_bankmachine6_state <= 3'd0; subfragments_bankmachine7_state <= 3'd0; subfragments_multiplexer_state <= 4'd0; subfragments_new_master_wdata_ready0 <= 1'd0; subfragments_new_master_wdata_ready1 <= 1'd0; subfragments_new_master_rdata_valid0 <= 1'd0; subfragments_new_master_rdata_valid1 <= 1'd0; subfragments_new_master_rdata_valid2 <= 1'd0; subfragments_new_master_rdata_valid3 <= 1'd0; subfragments_new_master_rdata_valid4 <= 1'd0; subfragments_new_master_rdata_valid5 <= 1'd0; subfragments_new_master_rdata_valid6 <= 1'd0; subfragments_new_master_rdata_valid7 <= 1'd0; subfragments_new_master_rdata_valid8 <= 1'd0; subfragments_fullmemorywe_state <= 2'd0; subfragments_litesataphy_gtptxinit_state <= 4'd0; subfragments_litesataphy_gtprxinit_state <= 4'd0; subfragments_litesataphy_state <= 4'd0; subfragments_litesatalinktx_litesatacrcinserter_state <= 2'd0; subfragments_litesatalinktx_fsm_state <= 3'd0; subfragments_litesatalinkrx_litesatacrcchecker_state <= 2'd0; subfragments_litesatalinkrx_fsm_state <= 3'd0; subfragments_litesatatransporttx_state <= 2'd0; subfragments_litesatatransportrx_state <= 3'd0; subfragments_litesatacommandtx_state <= 2'd0; subfragments_litesatacommandrx_state <= 4'd0; subfragments_grant <= 1'd0; subfragments_ongoing0 <= 1'd0; subfragments_ongoing1 <= 1'd0; subfragments_litesatasector2memdma_state <= 2'd0; subfragments_wishbonedmareader_state <= 1'd0; subfragments_fsm_state <= 2'd0; basesoc_basesoc_we <= 1'd0; basesoc_grant <= 2'd0; basesoc_slave_sel_r <= 4'd0; basesoc_count <= 20'd1000000; basesoc_csr_bankarray_sel_r <= 1'd0; basesoc_state <= 2'd0; end xilinxmultiregimpl0_regs0 <= serial_rx; xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0; xilinxmultiregimpl1_regs0 <= a7litesataphy_tx_init_plllock0; xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0; xilinxmultiregimpl2_regs0 <= a7litesataphy_tx_init_txresetdone0; xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0; xilinxmultiregimpl3_regs0 <= a7litesataphy_tx_init_txdlysresetdone0; xilinxmultiregimpl3_regs1 <= xilinxmultiregimpl3_regs0; xilinxmultiregimpl4_regs0 <= a7litesataphy_tx_init_txphinitdone0; xilinxmultiregimpl4_regs1 <= xilinxmultiregimpl4_regs0; xilinxmultiregimpl5_regs0 <= a7litesataphy_tx_init_txphaligndone0; xilinxmultiregimpl5_regs1 <= xilinxmultiregimpl5_regs0; xilinxmultiregimpl6_regs0 <= a7litesataphy_rx_init_rxpmaresetdone0; xilinxmultiregimpl6_regs1 <= xilinxmultiregimpl6_regs0; xilinxmultiregimpl7_regs0 <= a7litesataphy_rx_init_plllock0; xilinxmultiregimpl7_regs1 <= xilinxmultiregimpl7_regs0; xilinxmultiregimpl8_regs0 <= a7litesataphy_rx_init_rxresetdone0; xilinxmultiregimpl8_regs1 <= xilinxmultiregimpl8_regs0; xilinxmultiregimpl9_regs0 <= a7litesataphy_rx_init_rxdlysresetdone0; xilinxmultiregimpl9_regs1 <= xilinxmultiregimpl9_regs0; xilinxmultiregimpl10_regs0 <= a7litesataphy_rx_init_rxsyncdone0; xilinxmultiregimpl10_regs1 <= xilinxmultiregimpl10_regs0; xilinxmultiregimpl15_regs0 <= a7litesataphy_pulsesynchronizer2_toggle_i; xilinxmultiregimpl15_regs1 <= xilinxmultiregimpl15_regs0; xilinxmultiregimpl16_regs0 <= a7litesataphy_rxcominitdet1; xilinxmultiregimpl16_regs1 <= xilinxmultiregimpl16_regs0; xilinxmultiregimpl17_regs0 <= a7litesataphy_rxcomwakedet1; xilinxmultiregimpl17_regs1 <= xilinxmultiregimpl17_regs0; xilinxmultiregimpl18_regs0 <= a7litesataphy_rxdisperr1; xilinxmultiregimpl18_regs1 <= xilinxmultiregimpl18_regs0; xilinxmultiregimpl19_regs0 <= a7litesataphy_rxnotintable1; xilinxmultiregimpl19_regs1 <= xilinxmultiregimpl19_regs0; xilinxmultiregimpl21_regs0 <= datapath_tx_fifo_graycounter1_q; xilinxmultiregimpl21_regs1 <= xilinxmultiregimpl21_regs0; xilinxmultiregimpl22_regs0 <= datapath_rx_fifo_graycounter0_q; xilinxmultiregimpl22_regs1 <= xilinxmultiregimpl22_regs0; end reg [31:0] mem[0:16383]; reg [31:0] memdat; always @(posedge sys_clk) begin memdat <= mem[basesoc_adr]; end assign basesoc_dat_r = memdat; initial begin $readmemh("mem.init", mem); end reg [31:0] mem_1[0:2047]; reg [10:0] memadr; always @(posedge sys_clk) begin if (ram_we[0]) mem_1[ram_adr][7:0] <= ram_dat_w[7:0]; if (ram_we[1]) mem_1[ram_adr][15:8] <= ram_dat_w[15:8]; if (ram_we[2]) mem_1[ram_adr][23:16] <= ram_dat_w[23:16]; if (ram_we[3]) mem_1[ram_adr][31:24] <= ram_dat_w[31:24]; memadr <= ram_adr; end assign ram_dat_r = mem_1[memadr]; initial begin $readmemh("mem_1.init", mem_1); end reg [7:0] mem_2[0:44]; reg [5:0] memadr_1; always @(posedge sys_clk) begin memadr_1 <= basesoc_csr_bankarray_adr; end assign basesoc_csr_bankarray_dat_r = mem_2[memadr_1]; initial begin $readmemh("mem_2.init", mem_2); end reg [9:0] storage_1[0:15]; reg [9:0] memdat_1; reg [9:0] memdat_2; always @(posedge sys_clk) begin if (uart_tx_fifo_wrport_we) storage_1[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w; memdat_1 <= storage_1[uart_tx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (uart_tx_fifo_rdport_re) memdat_2 <= storage_1[uart_tx_fifo_rdport_adr]; end assign uart_tx_fifo_wrport_dat_r = memdat_1; assign uart_tx_fifo_rdport_dat_r = memdat_2; reg [9:0] storage_2[0:15]; reg [9:0] memdat_3; reg [9:0] memdat_4; always @(posedge sys_clk) begin if (uart_rx_fifo_wrport_we) storage_2[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w; memdat_3 <= storage_2[uart_rx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (uart_rx_fifo_rdport_re) memdat_4 <= storage_2[uart_rx_fifo_rdport_adr]; end assign uart_rx_fifo_wrport_dat_r = memdat_3; assign uart_rx_fifo_rdport_dat_r = memdat_4; BUFG BUFG( .I(crg_clkout0), .O(crg_clkout_buf0) ); BUFG BUFG_1( .I(crg_clkout1), .O(crg_clkout_buf1) ); BUFG BUFG_2( .I(crg_clkout2), .O(crg_clkout_buf2) ); BUFG BUFG_3( .I(crg_clkout3), .O(crg_clkout_buf3) ); BUFG BUFG_4( .I(crg_clkout4), .O(crg_clkout_buf4) ); IDELAYCTRL IDELAYCTRL( .REFCLK(idelay_clk), .RST(crg_ic_reset) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(1'd0), .D2(1'd1), .D3(1'd0), .D4(1'd1), .D5(1'd0), .D6(1'd1), .D7(1'd0), .D8(1'd1), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(a7ddrphy_sd_clk_se_nodelay) ); OBUFDS OBUFDS( .I(a7ddrphy_sd_clk_se_nodelay), .O(ddram_clk_p), .OB(ddram_clk_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_1 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_reset_n), .D2(a7ddrphy_dfi_p0_reset_n), .D3(a7ddrphy_dfi_p1_reset_n), .D4(a7ddrphy_dfi_p1_reset_n), .D5(a7ddrphy_dfi_p2_reset_n), .D6(a7ddrphy_dfi_p2_reset_n), .D7(a7ddrphy_dfi_p3_reset_n), .D8(a7ddrphy_dfi_p3_reset_n), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_reset_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[0]), .D2(a7ddrphy_dfi_p0_address[0]), .D3(a7ddrphy_dfi_p1_address[0]), .D4(a7ddrphy_dfi_p1_address[0]), .D5(a7ddrphy_dfi_p2_address[0]), .D6(a7ddrphy_dfi_p2_address[0]), .D7(a7ddrphy_dfi_p3_address[0]), .D8(a7ddrphy_dfi_p3_address[0]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[0]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_3 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[1]), .D2(a7ddrphy_dfi_p0_address[1]), .D3(a7ddrphy_dfi_p1_address[1]), .D4(a7ddrphy_dfi_p1_address[1]), .D5(a7ddrphy_dfi_p2_address[1]), .D6(a7ddrphy_dfi_p2_address[1]), .D7(a7ddrphy_dfi_p3_address[1]), .D8(a7ddrphy_dfi_p3_address[1]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[1]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_4 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[2]), .D2(a7ddrphy_dfi_p0_address[2]), .D3(a7ddrphy_dfi_p1_address[2]), .D4(a7ddrphy_dfi_p1_address[2]), .D5(a7ddrphy_dfi_p2_address[2]), .D6(a7ddrphy_dfi_p2_address[2]), .D7(a7ddrphy_dfi_p3_address[2]), .D8(a7ddrphy_dfi_p3_address[2]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[2]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_5 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[3]), .D2(a7ddrphy_dfi_p0_address[3]), .D3(a7ddrphy_dfi_p1_address[3]), .D4(a7ddrphy_dfi_p1_address[3]), .D5(a7ddrphy_dfi_p2_address[3]), .D6(a7ddrphy_dfi_p2_address[3]), .D7(a7ddrphy_dfi_p3_address[3]), .D8(a7ddrphy_dfi_p3_address[3]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[3]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_6 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[4]), .D2(a7ddrphy_dfi_p0_address[4]), .D3(a7ddrphy_dfi_p1_address[4]), .D4(a7ddrphy_dfi_p1_address[4]), .D5(a7ddrphy_dfi_p2_address[4]), .D6(a7ddrphy_dfi_p2_address[4]), .D7(a7ddrphy_dfi_p3_address[4]), .D8(a7ddrphy_dfi_p3_address[4]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[4]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_7 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[5]), .D2(a7ddrphy_dfi_p0_address[5]), .D3(a7ddrphy_dfi_p1_address[5]), .D4(a7ddrphy_dfi_p1_address[5]), .D5(a7ddrphy_dfi_p2_address[5]), .D6(a7ddrphy_dfi_p2_address[5]), .D7(a7ddrphy_dfi_p3_address[5]), .D8(a7ddrphy_dfi_p3_address[5]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[5]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_8 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[6]), .D2(a7ddrphy_dfi_p0_address[6]), .D3(a7ddrphy_dfi_p1_address[6]), .D4(a7ddrphy_dfi_p1_address[6]), .D5(a7ddrphy_dfi_p2_address[6]), .D6(a7ddrphy_dfi_p2_address[6]), .D7(a7ddrphy_dfi_p3_address[6]), .D8(a7ddrphy_dfi_p3_address[6]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[6]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_9 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[7]), .D2(a7ddrphy_dfi_p0_address[7]), .D3(a7ddrphy_dfi_p1_address[7]), .D4(a7ddrphy_dfi_p1_address[7]), .D5(a7ddrphy_dfi_p2_address[7]), .D6(a7ddrphy_dfi_p2_address[7]), .D7(a7ddrphy_dfi_p3_address[7]), .D8(a7ddrphy_dfi_p3_address[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[7]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_10 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[8]), .D2(a7ddrphy_dfi_p0_address[8]), .D3(a7ddrphy_dfi_p1_address[8]), .D4(a7ddrphy_dfi_p1_address[8]), .D5(a7ddrphy_dfi_p2_address[8]), .D6(a7ddrphy_dfi_p2_address[8]), .D7(a7ddrphy_dfi_p3_address[8]), .D8(a7ddrphy_dfi_p3_address[8]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[8]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_11 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[9]), .D2(a7ddrphy_dfi_p0_address[9]), .D3(a7ddrphy_dfi_p1_address[9]), .D4(a7ddrphy_dfi_p1_address[9]), .D5(a7ddrphy_dfi_p2_address[9]), .D6(a7ddrphy_dfi_p2_address[9]), .D7(a7ddrphy_dfi_p3_address[9]), .D8(a7ddrphy_dfi_p3_address[9]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[9]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_12 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[10]), .D2(a7ddrphy_dfi_p0_address[10]), .D3(a7ddrphy_dfi_p1_address[10]), .D4(a7ddrphy_dfi_p1_address[10]), .D5(a7ddrphy_dfi_p2_address[10]), .D6(a7ddrphy_dfi_p2_address[10]), .D7(a7ddrphy_dfi_p3_address[10]), .D8(a7ddrphy_dfi_p3_address[10]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[10]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_13 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[11]), .D2(a7ddrphy_dfi_p0_address[11]), .D3(a7ddrphy_dfi_p1_address[11]), .D4(a7ddrphy_dfi_p1_address[11]), .D5(a7ddrphy_dfi_p2_address[11]), .D6(a7ddrphy_dfi_p2_address[11]), .D7(a7ddrphy_dfi_p3_address[11]), .D8(a7ddrphy_dfi_p3_address[11]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[11]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_14 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[12]), .D2(a7ddrphy_dfi_p0_address[12]), .D3(a7ddrphy_dfi_p1_address[12]), .D4(a7ddrphy_dfi_p1_address[12]), .D5(a7ddrphy_dfi_p2_address[12]), .D6(a7ddrphy_dfi_p2_address[12]), .D7(a7ddrphy_dfi_p3_address[12]), .D8(a7ddrphy_dfi_p3_address[12]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[12]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_15 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[13]), .D2(a7ddrphy_dfi_p0_address[13]), .D3(a7ddrphy_dfi_p1_address[13]), .D4(a7ddrphy_dfi_p1_address[13]), .D5(a7ddrphy_dfi_p2_address[13]), .D6(a7ddrphy_dfi_p2_address[13]), .D7(a7ddrphy_dfi_p3_address[13]), .D8(a7ddrphy_dfi_p3_address[13]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[13]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_16 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[14]), .D2(a7ddrphy_dfi_p0_address[14]), .D3(a7ddrphy_dfi_p1_address[14]), .D4(a7ddrphy_dfi_p1_address[14]), .D5(a7ddrphy_dfi_p2_address[14]), .D6(a7ddrphy_dfi_p2_address[14]), .D7(a7ddrphy_dfi_p3_address[14]), .D8(a7ddrphy_dfi_p3_address[14]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[14]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_17 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_bank[0]), .D2(a7ddrphy_dfi_p0_bank[0]), .D3(a7ddrphy_dfi_p1_bank[0]), .D4(a7ddrphy_dfi_p1_bank[0]), .D5(a7ddrphy_dfi_p2_bank[0]), .D6(a7ddrphy_dfi_p2_bank[0]), .D7(a7ddrphy_dfi_p3_bank[0]), .D8(a7ddrphy_dfi_p3_bank[0]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_ba[0]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_18 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_bank[1]), .D2(a7ddrphy_dfi_p0_bank[1]), .D3(a7ddrphy_dfi_p1_bank[1]), .D4(a7ddrphy_dfi_p1_bank[1]), .D5(a7ddrphy_dfi_p2_bank[1]), .D6(a7ddrphy_dfi_p2_bank[1]), .D7(a7ddrphy_dfi_p3_bank[1]), .D8(a7ddrphy_dfi_p3_bank[1]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_ba[1]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_19 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_bank[2]), .D2(a7ddrphy_dfi_p0_bank[2]), .D3(a7ddrphy_dfi_p1_bank[2]), .D4(a7ddrphy_dfi_p1_bank[2]), .D5(a7ddrphy_dfi_p2_bank[2]), .D6(a7ddrphy_dfi_p2_bank[2]), .D7(a7ddrphy_dfi_p3_bank[2]), .D8(a7ddrphy_dfi_p3_bank[2]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_ba[2]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_20 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_ras_n), .D2(a7ddrphy_dfi_p0_ras_n), .D3(a7ddrphy_dfi_p1_ras_n), .D4(a7ddrphy_dfi_p1_ras_n), .D5(a7ddrphy_dfi_p2_ras_n), .D6(a7ddrphy_dfi_p2_ras_n), .D7(a7ddrphy_dfi_p3_ras_n), .D8(a7ddrphy_dfi_p3_ras_n), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_ras_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_21 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_cas_n), .D2(a7ddrphy_dfi_p0_cas_n), .D3(a7ddrphy_dfi_p1_cas_n), .D4(a7ddrphy_dfi_p1_cas_n), .D5(a7ddrphy_dfi_p2_cas_n), .D6(a7ddrphy_dfi_p2_cas_n), .D7(a7ddrphy_dfi_p3_cas_n), .D8(a7ddrphy_dfi_p3_cas_n), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_cas_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_22 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_we_n), .D2(a7ddrphy_dfi_p0_we_n), .D3(a7ddrphy_dfi_p1_we_n), .D4(a7ddrphy_dfi_p1_we_n), .D5(a7ddrphy_dfi_p2_we_n), .D6(a7ddrphy_dfi_p2_we_n), .D7(a7ddrphy_dfi_p3_we_n), .D8(a7ddrphy_dfi_p3_we_n), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_we_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_23 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_cke), .D2(a7ddrphy_dfi_p0_cke), .D3(a7ddrphy_dfi_p1_cke), .D4(a7ddrphy_dfi_p1_cke), .D5(a7ddrphy_dfi_p2_cke), .D6(a7ddrphy_dfi_p2_cke), .D7(a7ddrphy_dfi_p3_cke), .D8(a7ddrphy_dfi_p3_cke), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_cke) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_24 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_odt), .D2(a7ddrphy_dfi_p0_odt), .D3(a7ddrphy_dfi_p1_odt), .D4(a7ddrphy_dfi_p1_odt), .D5(a7ddrphy_dfi_p2_odt), .D6(a7ddrphy_dfi_p2_odt), .D7(a7ddrphy_dfi_p3_odt), .D8(a7ddrphy_dfi_p3_odt), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_odt) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_25 ( .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip00[0]), .D2(a7ddrphy_bitslip00[1]), .D3(a7ddrphy_bitslip00[2]), .D4(a7ddrphy_bitslip00[3]), .D5(a7ddrphy_bitslip00[4]), .D6(a7ddrphy_bitslip00[5]), .D7(a7ddrphy_bitslip00[6]), .D8(a7ddrphy_bitslip00[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OFB(a7ddrphy0), .OQ(a7ddrphy_dqs_o_no_delay0), .TQ(a7ddrphy_dqs_t0) ); IOBUFDS IOBUFDS( .I(a7ddrphy_dqs_o_no_delay0), .T(a7ddrphy_dqs_t0), .IO(ddram_dqs_p[0]), .IOB(ddram_dqs_n[0]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_26 ( .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip10[0]), .D2(a7ddrphy_bitslip10[1]), .D3(a7ddrphy_bitslip10[2]), .D4(a7ddrphy_bitslip10[3]), .D5(a7ddrphy_bitslip10[4]), .D6(a7ddrphy_bitslip10[5]), .D7(a7ddrphy_bitslip10[6]), .D8(a7ddrphy_bitslip10[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OFB(a7ddrphy1), .OQ(a7ddrphy_dqs_o_no_delay1), .TQ(a7ddrphy_dqs_t1) ); IOBUFDS IOBUFDS_1( .I(a7ddrphy_dqs_o_no_delay1), .T(a7ddrphy_dqs_t1), .IO(ddram_dqs_p[1]), .IOB(ddram_dqs_n[1]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_27 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip01[0]), .D2(a7ddrphy_bitslip01[1]), .D3(a7ddrphy_bitslip01[2]), .D4(a7ddrphy_bitslip01[3]), .D5(a7ddrphy_bitslip01[4]), .D6(a7ddrphy_bitslip01[5]), .D7(a7ddrphy_bitslip01[6]), .D8(a7ddrphy_bitslip01[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_dm[0]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_28 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip11[0]), .D2(a7ddrphy_bitslip11[1]), .D3(a7ddrphy_bitslip11[2]), .D4(a7ddrphy_bitslip11[3]), .D5(a7ddrphy_bitslip11[4]), .D6(a7ddrphy_bitslip11[5]), .D7(a7ddrphy_bitslip11[6]), .D8(a7ddrphy_bitslip11[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_dm[1]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_29 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip02[0]), .D2(a7ddrphy_bitslip02[1]), .D3(a7ddrphy_bitslip02[2]), .D4(a7ddrphy_bitslip02[3]), .D5(a7ddrphy_bitslip02[4]), .D6(a7ddrphy_bitslip02[5]), .D7(a7ddrphy_bitslip02[6]), .D8(a7ddrphy_bitslip02[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay0), .TQ(a7ddrphy_dq_t0) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed0), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip03[7]), .Q2(a7ddrphy_bitslip03[6]), .Q3(a7ddrphy_bitslip03[5]), .Q4(a7ddrphy_bitslip03[4]), .Q5(a7ddrphy_bitslip03[3]), .Q6(a7ddrphy_bitslip03[2]), .Q7(a7ddrphy_bitslip03[1]), .Q8(a7ddrphy_bitslip03[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay0), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed0) ); IOBUF IOBUF( .I(a7ddrphy_dq_o_nodelay0), .T(a7ddrphy_dq_t0), .IO(ddram_dq[0]), .O(a7ddrphy_dq_i_nodelay0) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_30 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip12[0]), .D2(a7ddrphy_bitslip12[1]), .D3(a7ddrphy_bitslip12[2]), .D4(a7ddrphy_bitslip12[3]), .D5(a7ddrphy_bitslip12[4]), .D6(a7ddrphy_bitslip12[5]), .D7(a7ddrphy_bitslip12[6]), .D8(a7ddrphy_bitslip12[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay1), .TQ(a7ddrphy_dq_t1) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_1 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed1), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip13[7]), .Q2(a7ddrphy_bitslip13[6]), .Q3(a7ddrphy_bitslip13[5]), .Q4(a7ddrphy_bitslip13[4]), .Q5(a7ddrphy_bitslip13[3]), .Q6(a7ddrphy_bitslip13[2]), .Q7(a7ddrphy_bitslip13[1]), .Q8(a7ddrphy_bitslip13[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_1 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay1), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed1) ); IOBUF IOBUF_1( .I(a7ddrphy_dq_o_nodelay1), .T(a7ddrphy_dq_t1), .IO(ddram_dq[1]), .O(a7ddrphy_dq_i_nodelay1) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_31 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip20[0]), .D2(a7ddrphy_bitslip20[1]), .D3(a7ddrphy_bitslip20[2]), .D4(a7ddrphy_bitslip20[3]), .D5(a7ddrphy_bitslip20[4]), .D6(a7ddrphy_bitslip20[5]), .D7(a7ddrphy_bitslip20[6]), .D8(a7ddrphy_bitslip20[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay2), .TQ(a7ddrphy_dq_t2) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_2 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed2), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip21[7]), .Q2(a7ddrphy_bitslip21[6]), .Q3(a7ddrphy_bitslip21[5]), .Q4(a7ddrphy_bitslip21[4]), .Q5(a7ddrphy_bitslip21[3]), .Q6(a7ddrphy_bitslip21[2]), .Q7(a7ddrphy_bitslip21[1]), .Q8(a7ddrphy_bitslip21[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_2 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay2), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed2) ); IOBUF IOBUF_2( .I(a7ddrphy_dq_o_nodelay2), .T(a7ddrphy_dq_t2), .IO(ddram_dq[2]), .O(a7ddrphy_dq_i_nodelay2) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_32 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip30[0]), .D2(a7ddrphy_bitslip30[1]), .D3(a7ddrphy_bitslip30[2]), .D4(a7ddrphy_bitslip30[3]), .D5(a7ddrphy_bitslip30[4]), .D6(a7ddrphy_bitslip30[5]), .D7(a7ddrphy_bitslip30[6]), .D8(a7ddrphy_bitslip30[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay3), .TQ(a7ddrphy_dq_t3) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_3 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed3), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip31[7]), .Q2(a7ddrphy_bitslip31[6]), .Q3(a7ddrphy_bitslip31[5]), .Q4(a7ddrphy_bitslip31[4]), .Q5(a7ddrphy_bitslip31[3]), .Q6(a7ddrphy_bitslip31[2]), .Q7(a7ddrphy_bitslip31[1]), .Q8(a7ddrphy_bitslip31[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_3 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay3), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed3) ); IOBUF IOBUF_3( .I(a7ddrphy_dq_o_nodelay3), .T(a7ddrphy_dq_t3), .IO(ddram_dq[3]), .O(a7ddrphy_dq_i_nodelay3) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_33 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip40[0]), .D2(a7ddrphy_bitslip40[1]), .D3(a7ddrphy_bitslip40[2]), .D4(a7ddrphy_bitslip40[3]), .D5(a7ddrphy_bitslip40[4]), .D6(a7ddrphy_bitslip40[5]), .D7(a7ddrphy_bitslip40[6]), .D8(a7ddrphy_bitslip40[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay4), .TQ(a7ddrphy_dq_t4) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_4 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed4), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip41[7]), .Q2(a7ddrphy_bitslip41[6]), .Q3(a7ddrphy_bitslip41[5]), .Q4(a7ddrphy_bitslip41[4]), .Q5(a7ddrphy_bitslip41[3]), .Q6(a7ddrphy_bitslip41[2]), .Q7(a7ddrphy_bitslip41[1]), .Q8(a7ddrphy_bitslip41[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_4 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay4), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed4) ); IOBUF IOBUF_4( .I(a7ddrphy_dq_o_nodelay4), .T(a7ddrphy_dq_t4), .IO(ddram_dq[4]), .O(a7ddrphy_dq_i_nodelay4) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_34 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip50[0]), .D2(a7ddrphy_bitslip50[1]), .D3(a7ddrphy_bitslip50[2]), .D4(a7ddrphy_bitslip50[3]), .D5(a7ddrphy_bitslip50[4]), .D6(a7ddrphy_bitslip50[5]), .D7(a7ddrphy_bitslip50[6]), .D8(a7ddrphy_bitslip50[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay5), .TQ(a7ddrphy_dq_t5) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_5 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed5), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip51[7]), .Q2(a7ddrphy_bitslip51[6]), .Q3(a7ddrphy_bitslip51[5]), .Q4(a7ddrphy_bitslip51[4]), .Q5(a7ddrphy_bitslip51[3]), .Q6(a7ddrphy_bitslip51[2]), .Q7(a7ddrphy_bitslip51[1]), .Q8(a7ddrphy_bitslip51[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_5 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay5), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed5) ); IOBUF IOBUF_5( .I(a7ddrphy_dq_o_nodelay5), .T(a7ddrphy_dq_t5), .IO(ddram_dq[5]), .O(a7ddrphy_dq_i_nodelay5) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_35 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip60[0]), .D2(a7ddrphy_bitslip60[1]), .D3(a7ddrphy_bitslip60[2]), .D4(a7ddrphy_bitslip60[3]), .D5(a7ddrphy_bitslip60[4]), .D6(a7ddrphy_bitslip60[5]), .D7(a7ddrphy_bitslip60[6]), .D8(a7ddrphy_bitslip60[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay6), .TQ(a7ddrphy_dq_t6) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_6 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed6), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip61[7]), .Q2(a7ddrphy_bitslip61[6]), .Q3(a7ddrphy_bitslip61[5]), .Q4(a7ddrphy_bitslip61[4]), .Q5(a7ddrphy_bitslip61[3]), .Q6(a7ddrphy_bitslip61[2]), .Q7(a7ddrphy_bitslip61[1]), .Q8(a7ddrphy_bitslip61[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_6 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay6), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed6) ); IOBUF IOBUF_6( .I(a7ddrphy_dq_o_nodelay6), .T(a7ddrphy_dq_t6), .IO(ddram_dq[6]), .O(a7ddrphy_dq_i_nodelay6) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_36 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip70[0]), .D2(a7ddrphy_bitslip70[1]), .D3(a7ddrphy_bitslip70[2]), .D4(a7ddrphy_bitslip70[3]), .D5(a7ddrphy_bitslip70[4]), .D6(a7ddrphy_bitslip70[5]), .D7(a7ddrphy_bitslip70[6]), .D8(a7ddrphy_bitslip70[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay7), .TQ(a7ddrphy_dq_t7) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_7 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed7), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip71[7]), .Q2(a7ddrphy_bitslip71[6]), .Q3(a7ddrphy_bitslip71[5]), .Q4(a7ddrphy_bitslip71[4]), .Q5(a7ddrphy_bitslip71[3]), .Q6(a7ddrphy_bitslip71[2]), .Q7(a7ddrphy_bitslip71[1]), .Q8(a7ddrphy_bitslip71[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_7 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay7), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed7) ); IOBUF IOBUF_7( .I(a7ddrphy_dq_o_nodelay7), .T(a7ddrphy_dq_t7), .IO(ddram_dq[7]), .O(a7ddrphy_dq_i_nodelay7) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_37 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip80[0]), .D2(a7ddrphy_bitslip80[1]), .D3(a7ddrphy_bitslip80[2]), .D4(a7ddrphy_bitslip80[3]), .D5(a7ddrphy_bitslip80[4]), .D6(a7ddrphy_bitslip80[5]), .D7(a7ddrphy_bitslip80[6]), .D8(a7ddrphy_bitslip80[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay8), .TQ(a7ddrphy_dq_t8) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_8 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed8), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip81[7]), .Q2(a7ddrphy_bitslip81[6]), .Q3(a7ddrphy_bitslip81[5]), .Q4(a7ddrphy_bitslip81[4]), .Q5(a7ddrphy_bitslip81[3]), .Q6(a7ddrphy_bitslip81[2]), .Q7(a7ddrphy_bitslip81[1]), .Q8(a7ddrphy_bitslip81[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_8 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay8), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed8) ); IOBUF IOBUF_8( .I(a7ddrphy_dq_o_nodelay8), .T(a7ddrphy_dq_t8), .IO(ddram_dq[8]), .O(a7ddrphy_dq_i_nodelay8) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_38 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip90[0]), .D2(a7ddrphy_bitslip90[1]), .D3(a7ddrphy_bitslip90[2]), .D4(a7ddrphy_bitslip90[3]), .D5(a7ddrphy_bitslip90[4]), .D6(a7ddrphy_bitslip90[5]), .D7(a7ddrphy_bitslip90[6]), .D8(a7ddrphy_bitslip90[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay9), .TQ(a7ddrphy_dq_t9) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_9 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed9), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip91[7]), .Q2(a7ddrphy_bitslip91[6]), .Q3(a7ddrphy_bitslip91[5]), .Q4(a7ddrphy_bitslip91[4]), .Q5(a7ddrphy_bitslip91[3]), .Q6(a7ddrphy_bitslip91[2]), .Q7(a7ddrphy_bitslip91[1]), .Q8(a7ddrphy_bitslip91[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_9 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay9), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed9) ); IOBUF IOBUF_9( .I(a7ddrphy_dq_o_nodelay9), .T(a7ddrphy_dq_t9), .IO(ddram_dq[9]), .O(a7ddrphy_dq_i_nodelay9) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_39 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip100[0]), .D2(a7ddrphy_bitslip100[1]), .D3(a7ddrphy_bitslip100[2]), .D4(a7ddrphy_bitslip100[3]), .D5(a7ddrphy_bitslip100[4]), .D6(a7ddrphy_bitslip100[5]), .D7(a7ddrphy_bitslip100[6]), .D8(a7ddrphy_bitslip100[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay10), .TQ(a7ddrphy_dq_t10) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_10 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed10), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip101[7]), .Q2(a7ddrphy_bitslip101[6]), .Q3(a7ddrphy_bitslip101[5]), .Q4(a7ddrphy_bitslip101[4]), .Q5(a7ddrphy_bitslip101[3]), .Q6(a7ddrphy_bitslip101[2]), .Q7(a7ddrphy_bitslip101[1]), .Q8(a7ddrphy_bitslip101[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_10 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay10), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed10) ); IOBUF IOBUF_10( .I(a7ddrphy_dq_o_nodelay10), .T(a7ddrphy_dq_t10), .IO(ddram_dq[10]), .O(a7ddrphy_dq_i_nodelay10) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_40 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip110[0]), .D2(a7ddrphy_bitslip110[1]), .D3(a7ddrphy_bitslip110[2]), .D4(a7ddrphy_bitslip110[3]), .D5(a7ddrphy_bitslip110[4]), .D6(a7ddrphy_bitslip110[5]), .D7(a7ddrphy_bitslip110[6]), .D8(a7ddrphy_bitslip110[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay11), .TQ(a7ddrphy_dq_t11) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_11 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed11), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip111[7]), .Q2(a7ddrphy_bitslip111[6]), .Q3(a7ddrphy_bitslip111[5]), .Q4(a7ddrphy_bitslip111[4]), .Q5(a7ddrphy_bitslip111[3]), .Q6(a7ddrphy_bitslip111[2]), .Q7(a7ddrphy_bitslip111[1]), .Q8(a7ddrphy_bitslip111[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_11 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay11), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed11) ); IOBUF IOBUF_11( .I(a7ddrphy_dq_o_nodelay11), .T(a7ddrphy_dq_t11), .IO(ddram_dq[11]), .O(a7ddrphy_dq_i_nodelay11) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_41 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip120[0]), .D2(a7ddrphy_bitslip120[1]), .D3(a7ddrphy_bitslip120[2]), .D4(a7ddrphy_bitslip120[3]), .D5(a7ddrphy_bitslip120[4]), .D6(a7ddrphy_bitslip120[5]), .D7(a7ddrphy_bitslip120[6]), .D8(a7ddrphy_bitslip120[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay12), .TQ(a7ddrphy_dq_t12) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_12 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed12), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip121[7]), .Q2(a7ddrphy_bitslip121[6]), .Q3(a7ddrphy_bitslip121[5]), .Q4(a7ddrphy_bitslip121[4]), .Q5(a7ddrphy_bitslip121[3]), .Q6(a7ddrphy_bitslip121[2]), .Q7(a7ddrphy_bitslip121[1]), .Q8(a7ddrphy_bitslip121[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_12 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay12), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed12) ); IOBUF IOBUF_12( .I(a7ddrphy_dq_o_nodelay12), .T(a7ddrphy_dq_t12), .IO(ddram_dq[12]), .O(a7ddrphy_dq_i_nodelay12) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_42 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip130[0]), .D2(a7ddrphy_bitslip130[1]), .D3(a7ddrphy_bitslip130[2]), .D4(a7ddrphy_bitslip130[3]), .D5(a7ddrphy_bitslip130[4]), .D6(a7ddrphy_bitslip130[5]), .D7(a7ddrphy_bitslip130[6]), .D8(a7ddrphy_bitslip130[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay13), .TQ(a7ddrphy_dq_t13) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_13 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed13), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip131[7]), .Q2(a7ddrphy_bitslip131[6]), .Q3(a7ddrphy_bitslip131[5]), .Q4(a7ddrphy_bitslip131[4]), .Q5(a7ddrphy_bitslip131[3]), .Q6(a7ddrphy_bitslip131[2]), .Q7(a7ddrphy_bitslip131[1]), .Q8(a7ddrphy_bitslip131[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_13 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay13), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed13) ); IOBUF IOBUF_13( .I(a7ddrphy_dq_o_nodelay13), .T(a7ddrphy_dq_t13), .IO(ddram_dq[13]), .O(a7ddrphy_dq_i_nodelay13) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_43 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip140[0]), .D2(a7ddrphy_bitslip140[1]), .D3(a7ddrphy_bitslip140[2]), .D4(a7ddrphy_bitslip140[3]), .D5(a7ddrphy_bitslip140[4]), .D6(a7ddrphy_bitslip140[5]), .D7(a7ddrphy_bitslip140[6]), .D8(a7ddrphy_bitslip140[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay14), .TQ(a7ddrphy_dq_t14) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_14 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed14), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip141[7]), .Q2(a7ddrphy_bitslip141[6]), .Q3(a7ddrphy_bitslip141[5]), .Q4(a7ddrphy_bitslip141[4]), .Q5(a7ddrphy_bitslip141[3]), .Q6(a7ddrphy_bitslip141[2]), .Q7(a7ddrphy_bitslip141[1]), .Q8(a7ddrphy_bitslip141[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_14 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay14), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed14) ); IOBUF IOBUF_14( .I(a7ddrphy_dq_o_nodelay14), .T(a7ddrphy_dq_t14), .IO(ddram_dq[14]), .O(a7ddrphy_dq_i_nodelay14) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_44 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip150[0]), .D2(a7ddrphy_bitslip150[1]), .D3(a7ddrphy_bitslip150[2]), .D4(a7ddrphy_bitslip150[3]), .D5(a7ddrphy_bitslip150[4]), .D6(a7ddrphy_bitslip150[5]), .D7(a7ddrphy_bitslip150[6]), .D8(a7ddrphy_bitslip150[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay15), .TQ(a7ddrphy_dq_t15) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_15 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed15), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip151[7]), .Q2(a7ddrphy_bitslip151[6]), .Q3(a7ddrphy_bitslip151[5]), .Q4(a7ddrphy_bitslip151[4]), .Q5(a7ddrphy_bitslip151[3]), .Q6(a7ddrphy_bitslip151[2]), .Q7(a7ddrphy_bitslip151[1]), .Q8(a7ddrphy_bitslip151[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_15 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay15), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed15) ); IOBUF IOBUF_15( .I(a7ddrphy_dq_o_nodelay15), .T(a7ddrphy_dq_t15), .IO(ddram_dq[15]), .O(a7ddrphy_dq_i_nodelay15) ); reg [23:0] storage_3[0:7]; reg [23:0] memdat_5; always @(posedge sys_clk) begin if (sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) storage_3[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; memdat_5 <= storage_3[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5; assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_3[sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_4[0:7]; reg [23:0] memdat_6; always @(posedge sys_clk) begin if (sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) storage_4[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; memdat_6 <= storage_4[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6; assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_4[sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_5[0:7]; reg [23:0] memdat_7; always @(posedge sys_clk) begin if (sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) storage_5[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; memdat_7 <= storage_5[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7; assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_5[sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_6[0:7]; reg [23:0] memdat_8; always @(posedge sys_clk) begin if (sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) storage_6[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; memdat_8 <= storage_6[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8; assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_6[sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_7[0:7]; reg [23:0] memdat_9; always @(posedge sys_clk) begin if (sdram_bankmachine4_cmd_buffer_lookahead_wrport_we) storage_7[sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; memdat_9 <= storage_7[sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end assign sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9; assign sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_7[sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_8[0:7]; reg [23:0] memdat_10; always @(posedge sys_clk) begin if (sdram_bankmachine5_cmd_buffer_lookahead_wrport_we) storage_8[sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; memdat_10 <= storage_8[sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end assign sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10; assign sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_8[sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_9[0:7]; reg [23:0] memdat_11; always @(posedge sys_clk) begin if (sdram_bankmachine6_cmd_buffer_lookahead_wrport_we) storage_9[sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; memdat_11 <= storage_9[sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end assign sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11; assign sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_9[sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr]; reg [23:0] storage_10[0:7]; reg [23:0] memdat_12; always @(posedge sys_clk) begin if (sdram_bankmachine7_cmd_buffer_lookahead_wrport_we) storage_10[sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; memdat_12 <= storage_10[sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end assign sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12; assign sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_10[sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr]; reg [23:0] tag_mem[0:511]; reg [8:0] memadr_2; always @(posedge sys_clk) begin if (tag_port_we) tag_mem[tag_port_adr] <= tag_port_dat_w; memadr_2 <= tag_port_adr; end assign tag_port_dat_r = tag_mem[memadr_2]; GTPE2_COMMON #( .PLL0_FBDIV(3'd5), .PLL0_FBDIV_45(3'd4), .PLL0_REFCLK_DIV(1'd1) ) GTPE2_COMMON ( .BGBYPASSB(1'd1), .BGMONITORENB(1'd1), .BGPDB(1'd1), .BGRCALOVRD(5'd31), .DRPADDR(a7litesataphy_qpll_drp_addr), .DRPCLK(a7litesataphy_qpll_drp_clk), .DRPDI(a7litesataphy_qpll_drp_di), .DRPEN(a7litesataphy_qpll_drp_en), .DRPWE(a7litesataphy_qpll_drp_we), // FIXME: The GTREFCLK1 needs to be used for this design. // Vivado automatically swaps the input accordingly to the IBUFDS placement location // and this is currently not doable in VPR. For the time being, we can just manually adjust it. // https://github.com/SymbiFlow/symbiflow-arch-defs/issues/2328 .GTREFCLK1(a7litesataphy_gtrefclk0), .PLL0LOCKEN(1'd1), .PLL0PD(1'd0), .PLL0REFCLKSEL(1'd1), .PLL0RESET(a7litesataphy_qpll_reset), .PLL1PD(1'd1), .RCALENB(1'd1), .DRPDO(a7litesataphy_qpll_drp_do), .DRPRDY(a7litesataphy_qpll_drp_rdy), .PLL0LOCK(a7litesataphy_qpll_lock), .PLL0OUTCLK(a7litesataphy_qpll_clk), .PLL0OUTREFCLK(a7litesataphy_qpll_refclk) ); // FIXME: FDPE connected to the IBUFDS clk output need to be in the same clock region, otherwise resulting // in an unroutable situation. // https://github.com/SymbiFlow/symbiflow-arch-defs/issues/2327 (* LOC="SLICE_X51Y227" *) FDPE #( .INIT(1'd1) ) FDPE ( .C(a7litesataphy_gtrefclk0), .CE(1'd1), .D((~a7litesataphy_oobclk)), .PRE(1'd0), .Q(a7litesataphy_oobclk) ); GTPE2_CHANNEL #( .ACJTAG_DEBUG_MODE(1'd0), .ACJTAG_MODE(1'd0), .ACJTAG_RESET(1'd0), .ADAPT_CFG0(1'd0), .ALIGN_COMMA_DOUBLE("FALSE"), .ALIGN_COMMA_ENABLE(10'd1023), .ALIGN_COMMA_WORD(2'd2), .ALIGN_MCOMMA_DET("TRUE"), .ALIGN_MCOMMA_VALUE(10'd643), .ALIGN_PCOMMA_DET("TRUE"), .ALIGN_PCOMMA_VALUE(9'd380), .CBCC_DATA_SOURCE_SEL("DECODED"), .CFOK_CFG(43'd5016522067584), .CFOK_CFG2(6'd32), .CFOK_CFG3(6'd32), .CFOK_CFG4(1'd0), .CFOK_CFG5(1'd0), .CFOK_CFG6(1'd0), .CHAN_BOND_KEEP_ALIGN("FALSE"), .CHAN_BOND_MAX_SKEW(1'd1), .CHAN_BOND_SEQ_1_1(1'd0), .CHAN_BOND_SEQ_1_2(1'd0), .CHAN_BOND_SEQ_1_3(1'd0), .CHAN_BOND_SEQ_1_4(1'd0), .CHAN_BOND_SEQ_1_ENABLE(4'd15), .CHAN_BOND_SEQ_2_1(1'd0), .CHAN_BOND_SEQ_2_2(1'd0), .CHAN_BOND_SEQ_2_3(1'd0), .CHAN_BOND_SEQ_2_4(1'd0), .CHAN_BOND_SEQ_2_ENABLE(4'd15), .CHAN_BOND_SEQ_2_USE("FALSE"), .CHAN_BOND_SEQ_LEN(1'd1), .CLK_COMMON_SWING(1'd0), .CLK_CORRECT_USE("FALSE"), .CLK_COR_KEEP_IDLE("FALSE"), .CLK_COR_MAX_LAT(4'd9), .CLK_COR_MIN_LAT(3'd7), .CLK_COR_PRECEDENCE("TRUE"), .CLK_COR_REPEAT_WAIT(1'd0), .CLK_COR_SEQ_1_1(9'd256), .CLK_COR_SEQ_1_2(1'd0), .CLK_COR_SEQ_1_3(1'd0), .CLK_COR_SEQ_1_4(1'd0), .CLK_COR_SEQ_1_ENABLE(4'd15), .CLK_COR_SEQ_2_1(9'd256), .CLK_COR_SEQ_2_2(1'd0), .CLK_COR_SEQ_2_3(1'd0), .CLK_COR_SEQ_2_4(1'd0), .CLK_COR_SEQ_2_ENABLE(4'd15), .CLK_COR_SEQ_2_USE("FALSE"), .CLK_COR_SEQ_LEN(1'd1), .DEC_MCOMMA_DETECT("TRUE"), .DEC_PCOMMA_DETECT("TRUE"), .DEC_VALID_COMMA_ONLY("TRUE"), .DMONITOR_CFG(12'd2560), .ES_CLK_PHASE_SEL(1'd0), .ES_CONTROL(1'd0), .ES_ERRDET_EN("FALSE"), .ES_EYE_SCAN_EN("TRUE"), .ES_HORZ_OFFSET(5'd16), .ES_PMA_CFG(1'd0), .ES_PRESCALE(1'd0), .ES_QUALIFIER(1'd0), .ES_QUAL_MASK(1'd0), .ES_SDATA_MASK(1'd0), .ES_VERT_OFFSET(1'd0), .FTS_DESKEW_SEQ_ENABLE(4'd15), .FTS_LANE_DESKEW_CFG(4'd15), .FTS_LANE_DESKEW_EN("FALSE"), .GEARBOX_MODE(1'd0), .LOOPBACK_CFG(1'd0), .OUTREFCLK_SEL_INV(2'd3), .PCS_PCIE_EN("FALSE"), .PCS_RSVD_ATTR(9'd256), .PD_TRANS_TIME_FROM_P2(6'd60), .PD_TRANS_TIME_NONE_P2(6'd60), .PD_TRANS_TIME_TO_P2(7'd100), .PMA_LOOPBACK_CFG(1'd0), .PMA_RSV(10'd819), .PMA_RSV2(14'd8256), .PMA_RSV3(1'd0), .PMA_RSV4(1'd0), .PMA_RSV5(1'd0), .PMA_RSV6(1'd0), .PMA_RSV7(1'd0), .RXBUFRESET_TIME(1'd1), .RXBUF_ADDR_MODE("FAST"), .RXBUF_EIDLE_HI_CNT(4'd8), .RXBUF_EIDLE_LO_CNT(1'd0), .RXBUF_EN("FALSE"), .RXBUF_RESET_ON_CB_CHANGE("TRUE"), .RXBUF_RESET_ON_COMMAALIGN("FALSE"), .RXBUF_RESET_ON_EIDLE("FALSE"), .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), .RXBUF_THRESH_OVFLW(6'd61), .RXBUF_THRESH_OVRD("FALSE"), .RXBUF_THRESH_UNDFLW(3'd4), .RXCDRFREQRESET_TIME(1'd1), .RXCDRPHRESET_TIME(1'd1), .RXCDR_CFG(63'd5187619418075041808), .RXCDR_FR_RESET_ON_EIDLE(1'd0), .RXCDR_HOLD_DURING_EIDLE(1'd0), .RXCDR_LOCK_CFG(4'd9), .RXCDR_PH_RESET_ON_EIDLE(1'd0), .RXDLY_CFG(5'd31), .RXDLY_LCFG(6'd48), .RXDLY_TAP_CFG(1'd0), .RXGEARBOX_EN("FALSE"), .RXISCANRESET_TIME(1'd1), .RXLPMRESET_TIME(4'd15), .RXLPM_BIAS_STARTUP_DISABLE(1'd0), .RXLPM_CFG(3'd6), .RXLPM_CFG1(1'd0), .RXLPM_CM_CFG(1'd0), .RXLPM_GC_CFG(9'd482), .RXLPM_GC_CFG2(1'd1), .RXLPM_HF_CFG(10'd1008), .RXLPM_HF_CFG2(4'd10), .RXLPM_HF_CFG3(1'd0), .RXLPM_HOLD_DURING_EIDLE(1'd0), .RXLPM_INCM_CFG(1'd1), .RXLPM_IPCM_CFG(1'd0), .RXLPM_LF_CFG(10'd1008), .RXLPM_LF_CFG2(4'd10), .RXLPM_OSINT_CFG(3'd4), .RXOOB_CFG(3'd6), .RXOOB_CLK_CFG("PMA"), .RXOSCALRESET_TIME(2'd3), .RXOSCALRESET_TIMEOUT(1'd0), .RXOUT_DIV(2'd2), .RXPCSRESET_TIME(1'd1), .RXPHDLY_CFG(20'd540704), .RXPH_CFG(24'd12582914), .RXPH_MONITOR_SEL(1'd0), .RXPI_CFG0(1'd0), .RXPI_CFG1(1'd1), .RXPI_CFG2(1'd1), .RXPMARESET_TIME(2'd3), .RXPRBS_ERR_LOOPBACK(1'd0), .RXSLIDE_AUTO_WAIT(3'd7), .RXSLIDE_MODE("PCS"), .RXSYNC_MULTILANE(1'd0), .RXSYNC_OVRD(1'd0), .RXSYNC_SKIP_DA(1'd0), .RX_BIAS_CFG(12'd3891), .RX_BUFFER_CFG(1'd0), .RX_CLK25_DIV(3'd6), .RX_CLKMUX_EN(1'd1), .RX_CM_SEL(2'd3), .RX_CM_TRIM(4'd10), .RX_DATA_WIDTH(5'd20), .RX_DDI_SEL(1'd0), .RX_DEBUG_CFG(1'd0), .RX_DEFER_RESET_BUF_EN("TRUE"), .RX_DISPERR_SEQ_MATCH("TRUE"), .RX_OS_CFG(8'd128), .RX_SIG_VALID_DLY(4'd10), .RX_XCLK_SEL("RXUSR"), .SAS_MAX_COM(7'd64), .SAS_MIN_COM(6'd36), .SATA_BURST_SEQ_LEN(3'd5), .SATA_BURST_VAL(3'd4), .SATA_EIDLE_VAL(3'd4), .SATA_MAX_BURST(4'd8), .SATA_MAX_INIT(5'd21), .SATA_MAX_WAKE(3'd7), .SATA_MIN_BURST(3'd4), .SATA_MIN_INIT(4'd12), .SATA_MIN_WAKE(3'd4), .SATA_PLL_CFG("VCO_3000MHZ"), .SHOW_REALIGN_COMMA("TRUE"), .SIM_RECEIVER_DETECT_PASS("TRUE"), .SIM_RESET_SPEEDUP("FALSE"), .SIM_TX_EIDLE_DRIVE_LEVEL("X"), .SIM_VERSION("2.0"), .TERM_RCAL_CFG(15'd16912), .TERM_RCAL_OVRD(1'd0), .TRANS_TIME_RATE(4'd14), .TST_RSV(1'd0), .TXBUF_EN("TRUE"), .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), .TXDLY_CFG(5'd31), .TXDLY_LCFG(6'd48), .TXDLY_TAP_CFG(1'd0), .TXGEARBOX_EN("FALSE"), .TXOOB_CFG(1'd0), .TXOUT_DIV(2'd2), .TXPCSRESET_TIME(1'd1), .TXPHDLY_CFG(20'd540704), .TXPH_CFG(11'd1920), .TXPH_MONITOR_SEL(1'd0), .TXPI_CFG0(1'd0), .TXPI_CFG1(1'd0), .TXPI_CFG2(1'd0), .TXPI_CFG3(1'd0), .TXPI_CFG4(1'd0), .TXPI_CFG5(1'd0), .TXPI_GREY_SEL(1'd0), .TXPI_INVSTROBE_SEL(1'd0), .TXPI_PPMCLK_SEL("TXUSRCLK2"), .TXPI_PPM_CFG(1'd0), .TXPI_SYNFREQ_PPM(1'd1), .TXPMARESET_TIME(1'd1), .TXSYNC_MULTILANE(1'd0), .TXSYNC_OVRD(1'd0), .TXSYNC_SKIP_DA(1'd0), .TX_CLK25_DIV(3'd6), .TX_CLKMUX_EN(1'd1), .TX_DATA_WIDTH(5'd20), .TX_DEEMPH0(1'd0), .TX_DEEMPH1(1'd0), .TX_DRIVE_MODE("DIRECT"), .TX_EIDLE_ASSERT_DELAY(3'd6), .TX_EIDLE_DEASSERT_DELAY(3'd4), .TX_LOOPBACK_DRIVE_HIZ("FALSE"), .TX_MAINCURSOR_SEL(1'd0), .TX_MARGIN_FULL_0(7'd78), .TX_MARGIN_FULL_1(7'd73), .TX_MARGIN_FULL_2(7'd69), .TX_MARGIN_FULL_3(7'd66), .TX_MARGIN_FULL_4(7'd64), .TX_MARGIN_LOW_0(7'd70), .TX_MARGIN_LOW_1(7'd68), .TX_MARGIN_LOW_2(7'd66), .TX_MARGIN_LOW_3(7'd64), .TX_MARGIN_LOW_4(7'd64), .TX_PREDRIVER_MODE(1'd0), .TX_RXDETECT_CFG(13'd6194), .TX_RXDETECT_REF(3'd4), .TX_XCLK_SEL("TXOUT"), .UCODEER_CLR(1'd0), .USE_PCS_CLK_PHASE_SEL(1'd0) ) GTPE2_CHANNEL ( .CFGRESET(1'd0), .CLKRSVD0(1'd0), .CLKRSVD1(1'd0), .DMONFIFORESET(1'd0), .DMONITORCLK(1'd0), .DRPADDR(a7litesataphy_rx_init_drp_addr), .DRPCLK(a7litesataphy_rx_init_drp_clk), .DRPDI(a7litesataphy_rx_init_drp_di), .DRPEN(a7litesataphy_rx_init_drp_en), .DRPWE(a7litesataphy_rx_init_drp_we), .EYESCANMODE(1'd0), .EYESCANRESET(1'd0), .EYESCANTRIGGER(1'd0), .GTPRXN(fmc2sata_rx_n), .GTPRXP(fmc2sata_rx_p), .GTRESETSEL(1'd0), .GTRSVD(1'd0), .GTRXRESET(a7litesataphy_rx_init_gtrxreset0), .GTTXRESET(a7litesataphy_tx_init_gttxreset0), .LOOPBACK(1'd0), .PCSRSVDIN(1'd0), .PLL0CLK(a7litesataphy_qpll_clk), .PLL0REFCLK(a7litesataphy_qpll_refclk), .PLL1CLK(1'd0), .PLL1REFCLK(1'd0), .PMARSVDIN0(1'd0), .PMARSVDIN1(1'd0), .PMARSVDIN2(1'd0), .PMARSVDIN3(1'd0), .PMARSVDIN4(1'd0), .RESETOVRD(1'd0), .RX8B10BEN(1'd1), .RXADAPTSELTEST(1'd0), .RXBUFRESET(1'd0), .RXCDRFREQRESET(1'd0), .RXCDRHOLD(a7litesataphy_rx_cdrhold), .RXCDROVRDEN(1'd0), .RXCDRRESET(1'd0), .RXCDRRESETRSV(1'd0), .RXCHBONDEN(1'd0), .RXCHBONDI(1'd0), .RXCHBONDLEVEL(1'd0), .RXCHBONDMASTER(1'd0), .RXCHBONDSLAVE(1'd0), .RXCOMMADETEN(1'd1), .RXDDIEN(1'd1), .RXDFEXYDEN(1'd0), .RXDLYBYPASS(1'd0), .RXDLYEN(1'd0), .RXDLYOVRDEN(1'd0), .RXDLYSRESET(a7litesataphy_rx_init_rxdlysreset0), .RXELECIDLEMODE(1'd0), .RXGEARBOXSLIP(1'd0), .RXLPMHFHOLD(1'd0), .RXLPMHFOVRDEN(1'd0), .RXLPMLFHOLD(1'd0), .RXLPMLFOVRDEN(1'd0), .RXLPMOSINTNTRLEN(1'd0), .RXLPMRESET(1'd0), .RXMCOMMAALIGNEN(1'd1), .RXOOBRESET(1'd0), .RXOSCALRESET(1'd0), .RXOSHOLD(1'd0), .RXOSINTCFG(2'd2), .RXOSINTEN(1'd1), .RXOSINTHOLD(1'd0), .RXOSINTID0(1'd0), .RXOSINTNTRLEN(1'd0), .RXOSINTOVRDEN(1'd0), .RXOSINTPD(1'd0), .RXOSINTSTROBE(1'd0), .RXOSINTTESTOVRDEN(1'd0), .RXOSOVRDEN(1'd0), .RXOUTCLKSEL(2'd2), .RXPCOMMAALIGNEN(1'd1), .RXPCSRESET(1'd0), .RXPD({2{a7litesataphy_rxpd}}), .RXPHALIGN(1'd0), .RXPHALIGNEN(1'd0), .RXPHDLYPD(1'd0), .RXPHDLYRESET(1'd0), .RXPHOVRDEN(1'd0), .RXPMARESET(1'd0), .RXPOLARITY(a7litesataphy_rx_polarity), .RXPRBSCNTRESET(1'd0), .RXPRBSSEL(1'd0), .RXRATE(1'd0), .RXRATEMODE(1'd0), .RXSLIDE(1'd0), .RXSYNCALLIN(a7litesataphy_rxphaligndone), .RXSYNCIN(1'd0), .RXSYNCMODE(1'd1), .RXSYSCLKSEL(1'd0), .RXUSERRDY(a7litesataphy_rx_init_rxuserrdy0), .RXUSRCLK(a7litesataphy_rxusrclk), .RXUSRCLK2(a7litesataphy_rxusrclk2), .SETERRSTATUS(1'd0), .SIGVALIDCLK(a7litesataphy_oobclk), .TSTIN(20'd1048575), .TX8B10BBYPASS(1'd0), .TX8B10BEN(1'd1), .TXBUFDIFFCTRL(3'd4), .TXCHARDISPMODE(1'd0), .TXCHARDISPVAL(1'd0), .TXCHARISK(a7litesataphy_txcharisk), .TXCOMINIT(a7litesataphy_txcominit1), .TXCOMSAS(1'd0), .TXCOMWAKE(a7litesataphy_txcomwake1), .TXDATA(a7litesataphy_txdata), .TXDEEMPH(1'd0), .TXDETECTRX(1'd0), .TXDIFFCTRL(4'd8), .TXDIFFPD(1'd0), .TXDLYBYPASS(1'd1), .TXDLYEN(1'd0), .TXDLYHOLD(1'd0), .TXDLYOVRDEN(1'd0), .TXDLYSRESET(a7litesataphy_tx_init_txdlysreset0), .TXDLYUPDOWN(1'd0), .TXELECIDLE(a7litesataphy_txelecidle1), .TXHEADER(1'd0), .TXINHIBIT(1'd0), .TXMAINCURSOR(1'd0), .TXMARGIN(1'd0), .TXOUTCLKSEL(2'd2), .TXPCSRESET(1'd0), .TXPD({2{a7litesataphy_txpd1}}), .TXPDELECIDLEMODE(1'd0), .TXPHALIGN(a7litesataphy_tx_init_txphalign0), .TXPHALIGNEN(1'd0), .TXPHDLYPD(1'd0), .TXPHDLYRESET(1'd0), .TXPHDLYTSTCLK(1'd0), .TXPHINIT(a7litesataphy_tx_init_txphinit0), .TXPHOVRDEN(1'd0), .TXPIPPMEN(1'd0), .TXPIPPMOVRDEN(1'd0), .TXPIPPMPD(1'd0), .TXPIPPMSEL(1'd1), .TXPIPPMSTEPSIZE(1'd0), .TXPISOPD(1'd0), .TXPMARESET(1'd0), .TXPOLARITY(a7litesataphy_tx_polarity), .TXPOSTCURSOR(1'd0), .TXPOSTCURSORINV(1'd0), .TXPRBSFORCEERR(1'd0), .TXPRBSSEL(1'd0), .TXPRECURSOR(1'd0), .TXPRECURSORINV(1'd0), .TXRATE(1'd0), .TXRATEMODE(1'd0), .TXSEQUENCE(1'd0), .TXSTARTSEQ(1'd0), .TXSWING(1'd0), .TXSYNCALLIN(1'd0), .TXSYNCIN(1'd0), .TXSYNCMODE(1'd0), .TXSYSCLKSEL(1'd0), .TXUSERRDY(a7litesataphy_tx_init_txuserrdy0), .TXUSRCLK(a7litesataphy_txusrclk), .TXUSRCLK2(a7litesataphy_txusrclk2), .DMONITOROUT(a7litesataphy23), .DRPDO(a7litesataphy_rx_init_drp_do), .DRPRDY(a7litesataphy_rx_init_drp_rdy), .EYESCANDATAERROR(a7litesataphy2), .GTPTXN(fmc2sata_tx_n), .GTPTXP(fmc2sata_tx_p), .PCSRSVDOUT(a7litesataphy34), .PHYSTATUS(a7litesataphy0), .PMARSVDOUT0(a7litesataphy9), .PMARSVDOUT1(a7litesataphy10), .RXBUFSTATUS(a7litesataphy11), .RXBYTEISALIGNED(a7litesataphy16), .RXBYTEREALIGN(a7litesataphy17), .RXCDRLOCK(a7litesataphy3), .RXCHANBONDSEQ(a7litesataphy19), .RXCHANISALIGNED(a7litesataphy21), .RXCHANREALIGN(a7litesataphy22), .RXCHARISCOMMA(a7litesataphy8), .RXCHARISK(a7litesataphy_rxcharisk), .RXCHBONDO(a7litesataphy20), .RXCLKCORCNT(a7litesataphy6), .RXCOMINITDET(a7litesataphy_rxcominitdet1), .RXCOMMADET(a7litesataphy18), .RXCOMSASDET(a7litesataphy32), .RXCOMWAKEDET(a7litesataphy_rxcomwakedet1), .RXDATA(a7litesataphy_rxdata), .RXDATAVALID(a7litesataphy28), .RXDISPERR(a7litesataphy_rxdisperr1), .RXDLYSRESETDONE(a7litesataphy_rx_init_rxdlysresetdone0), .RXELECIDLE(a7litesataphy33), .RXHEADER(a7litesataphy29), .RXHEADERVALID(a7litesataphy30), .RXNOTINTABLE(a7litesataphy_rxnotintable1), .RXOSINTDONE(a7litesataphy4), .RXOSINTSTROBEDONE(a7litesataphy24), .RXOSINTSTROBESTARTED(a7litesataphy5), .RXOUTCLK(a7litesataphy_rxoutclk), .RXOUTCLKFABRIC(a7litesataphy26), .RXOUTCLKPCS(a7litesataphy27), .RXPHALIGNDONE(a7litesataphy_rxphaligndone), .RXPHMONITOR(a7litesataphy12), .RXPHSLIPMONITOR(a7litesataphy13), .RXPMARESETDONE(a7litesataphy_rx_init_rxpmaresetdone0), .RXPRBSERR(a7litesataphy7), .RXRATEDONE(a7litesataphy25), .RXRESETDONE(a7litesataphy_rx_init_rxresetdone0), .RXSTARTOFSEQ(a7litesataphy31), .RXSTATUS(a7litesataphy14), .RXSYNCDONE(a7litesataphy_rx_init_rxsyncdone0), .RXSYNCOUT(a7litesataphy15), .RXVALID(a7litesataphy1), .TXBUFSTATUS(a7litesataphy36), .TXCOMFINISH(a7litesataphy_txcomfinish1), .TXDLYSRESETDONE(a7litesataphy_tx_init_txdlysresetdone0), .TXGEARBOXREADY(a7litesataphy42), .TXOUTCLK(a7litesataphy_txoutclk), .TXOUTCLKFABRIC(a7litesataphy39), .TXOUTCLKPCS(a7litesataphy40), .TXPHALIGNDONE(a7litesataphy_tx_init_txphaligndone0), .TXPHINITDONE(a7litesataphy_tx_init_txphinitdone0), .TXPMARESETDONE(a7litesataphy35), .TXRATEDONE(a7litesataphy41), .TXRESETDONE(a7litesataphy_tx_init_txresetdone0), .TXSYNCDONE(a7litesataphy37), .TXSYNCOUT(a7litesataphy38) ); IBUFDS_GTE2 IBUFDS_GTE2( .CEB(1'd0), .I(fmc2sata_clk_p), .IB(fmc2sata_clk_n), .O(crg_refclk) ); BUFG BUFG_5( .I(a7litesataphy_txoutclk), .O(sata_tx_clk) ); BUFG BUFG_6( .I(a7litesataphy_rxoutclk), .O(sata_rx_clk) ); reg [37:0] storage_11[0:7]; reg [2:0] memadr_3; reg [2:0] memadr_4; always @(posedge sys_clk) begin if (datapath_tx_fifo_wrport_we) storage_11[datapath_tx_fifo_wrport_adr] <= datapath_tx_fifo_wrport_dat_w; memadr_3 <= datapath_tx_fifo_wrport_adr; end always @(posedge sata_tx_clk) begin memadr_4 <= datapath_tx_fifo_rdport_adr; end assign datapath_tx_fifo_wrport_dat_r = storage_11[memadr_3]; assign datapath_tx_fifo_rdport_dat_r = storage_11[memadr_4]; reg [37:0] storage_12[0:7]; reg [2:0] memadr_5; reg [2:0] memadr_6; always @(posedge sata_rx_clk) begin if (datapath_rx_fifo_wrport_we) storage_12[datapath_rx_fifo_wrport_adr] <= datapath_rx_fifo_wrport_dat_w; memadr_5 <= datapath_rx_fifo_wrport_adr; end always @(posedge sys_clk) begin memadr_6 <= datapath_rx_fifo_rdport_adr; end assign datapath_rx_fifo_wrport_dat_r = storage_12[memadr_5]; assign datapath_rx_fifo_rdport_dat_r = storage_12[memadr_6]; reg [34:0] storage_13[0:1]; reg [34:0] memdat_13; always @(posedge sys_clk) begin if (link_litesatalinkrx_crc_syncfifo_wrport_we) storage_13[link_litesatalinkrx_crc_syncfifo_wrport_adr] <= link_litesatalinkrx_crc_syncfifo_wrport_dat_w; memdat_13 <= storage_13[link_litesatalinkrx_crc_syncfifo_wrport_adr]; end always @(posedge sys_clk) begin end assign link_litesatalinkrx_crc_syncfifo_wrport_dat_r = memdat_13; assign link_litesatalinkrx_crc_syncfifo_rdport_dat_r = storage_13[link_litesatalinkrx_crc_syncfifo_rdport_adr]; reg [34:0] storage_14[0:127]; reg [34:0] memdat_14; always @(posedge sys_clk) begin if (link_rx_buffer_wrport_we) storage_14[link_rx_buffer_wrport_adr] <= link_rx_buffer_wrport_dat_w; memdat_14 <= storage_14[link_rx_buffer_wrport_adr]; end always @(posedge sys_clk) begin end assign link_rx_buffer_wrport_dat_r = memdat_14; assign link_rx_buffer_rdport_dat_r = storage_14[link_rx_buffer_rdport_adr]; reg [33:0] storage_15[0:127]; reg [33:0] memdat_15; always @(posedge sys_clk) begin if (sata_sector2mem_buf_wrport_we) storage_15[sata_sector2mem_buf_wrport_adr] <= sata_sector2mem_buf_wrport_dat_w; memdat_15 <= storage_15[sata_sector2mem_buf_wrport_adr]; end always @(posedge sys_clk) begin end assign sata_sector2mem_buf_wrport_dat_r = memdat_15; assign sata_sector2mem_buf_rdport_dat_r = storage_15[sata_sector2mem_buf_rdport_adr]; reg [33:0] storage_16[0:127]; reg [33:0] memdat_16; always @(posedge sys_clk) begin if (sata_mem2sector_buf_wrport_we) storage_16[sata_mem2sector_buf_wrport_adr] <= sata_mem2sector_buf_wrport_dat_w; memdat_16 <= storage_16[sata_mem2sector_buf_wrport_adr]; end always @(posedge sys_clk) begin end assign sata_mem2sector_buf_wrport_dat_r = memdat_16; assign sata_mem2sector_buf_rdport_dat_r = storage_16[sata_mem2sector_buf_rdport_adr]; VexRiscv VexRiscv( .clk(sys_clk), .dBusWishbone_ACK(cpu_dbus_ack), .dBusWishbone_DAT_MISO(cpu_dbus_dat_r), .dBusWishbone_ERR(cpu_dbus_err), .externalInterruptArray(cpu_interrupt), .externalResetVector(vexriscv), .iBusWishbone_ACK(cpu_ibus_ack), .iBusWishbone_DAT_MISO(cpu_ibus_dat_r), .iBusWishbone_ERR(cpu_ibus_err), .reset((sys_rst | cpu_reset_1)), .softwareInterrupt(1'd0), .timerInterrupt(1'd0), .dBusWishbone_ADR(cpu_dbus_adr), .dBusWishbone_BTE(cpu_dbus_bte), .dBusWishbone_CTI(cpu_dbus_cti), .dBusWishbone_CYC(cpu_dbus_cyc), .dBusWishbone_DAT_MOSI(cpu_dbus_dat_w), .dBusWishbone_SEL(cpu_dbus_sel), .dBusWishbone_STB(cpu_dbus_stb), .dBusWishbone_WE(cpu_dbus_we), .iBusWishbone_ADR(cpu_ibus_adr), .iBusWishbone_BTE(cpu_ibus_bte), .iBusWishbone_CTI(cpu_ibus_cti), .iBusWishbone_CYC(cpu_ibus_cyc), .iBusWishbone_DAT_MOSI(cpu_ibus_dat_w), .iBusWishbone_SEL(cpu_ibus_sel), .iBusWishbone_STB(cpu_ibus_stb), .iBusWishbone_WE(cpu_ibus_we) ); FD FD( .C(crg_clkin), .D(crg_reset), .Q(subfragments_reset0) ); FD FD_1( .C(crg_clkin), .D(subfragments_reset0), .Q(subfragments_reset1) ); FD FD_2( .C(crg_clkin), .D(subfragments_reset1), .Q(subfragments_reset2) ); FD FD_3( .C(crg_clkin), .D(subfragments_reset2), .Q(subfragments_reset3) ); FD FD_4( .C(crg_clkin), .D(subfragments_reset3), .Q(subfragments_reset4) ); FD FD_5( .C(crg_clkin), .D(subfragments_reset4), .Q(subfragments_reset5) ); FD FD_6( .C(crg_clkin), .D(subfragments_reset5), .Q(subfragments_reset6) ); FD FD_7( .C(crg_clkin), .D(subfragments_reset6), .Q(subfragments_reset7) ); PLLE2_ADV #( .CLKFBOUT_MULT(5'd16), .CLKIN1_PERIOD(10.0), .CLKOUT0_DIVIDE(5'd20), .CLKOUT0_PHASE(1'd0), .CLKOUT1_DIVIDE(3'd5), .CLKOUT1_PHASE(1'd0), .CLKOUT2_DIVIDE(3'd5), .CLKOUT2_PHASE(7'd90), .CLKOUT3_DIVIDE(4'd8), .CLKOUT3_PHASE(1'd0), .CLKOUT4_DIVIDE(5'd16), .CLKOUT4_PHASE(1'd0), .DIVCLK_DIVIDE(1'd1), .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV ( .CLKFBIN(subfragments_pll_fb), .CLKIN1(crg_clkin), .RST(subfragments_reset7), .CLKFBOUT(subfragments_pll_fb), .CLKOUT0(crg_clkout0), .CLKOUT1(crg_clkout1), .CLKOUT2(crg_clkout2), .CLKOUT3(crg_clkout3), .CLKOUT4(crg_clkout4), .LOCKED(crg_locked) ); reg [7:0] data_mem_grain0[0:511]; reg [8:0] memadr_7; always @(posedge sys_clk) begin if (data_port_we[0]) data_mem_grain0[data_port_adr] <= data_port_dat_w[7:0]; memadr_7 <= data_port_adr; end assign data_port_dat_r[7:0] = data_mem_grain0[memadr_7]; reg [7:0] data_mem_grain1[0:511]; reg [8:0] memadr_8; always @(posedge sys_clk) begin if (data_port_we[1]) data_mem_grain1[data_port_adr] <= data_port_dat_w[15:8]; memadr_8 <= data_port_adr; end assign data_port_dat_r[15:8] = data_mem_grain1[memadr_8]; reg [7:0] data_mem_grain2[0:511]; reg [8:0] memadr_9; always @(posedge sys_clk) begin if (data_port_we[2]) data_mem_grain2[data_port_adr] <= data_port_dat_w[23:16]; memadr_9 <= data_port_adr; end assign data_port_dat_r[23:16] = data_mem_grain2[memadr_9]; reg [7:0] data_mem_grain3[0:511]; reg [8:0] memadr_10; always @(posedge sys_clk) begin if (data_port_we[3]) data_mem_grain3[data_port_adr] <= data_port_dat_w[31:24]; memadr_10 <= data_port_adr; end assign data_port_dat_r[31:24] = data_mem_grain3[memadr_10]; reg [7:0] data_mem_grain4[0:511]; reg [8:0] memadr_11; always @(posedge sys_clk) begin if (data_port_we[4]) data_mem_grain4[data_port_adr] <= data_port_dat_w[39:32]; memadr_11 <= data_port_adr; end assign data_port_dat_r[39:32] = data_mem_grain4[memadr_11]; reg [7:0] data_mem_grain5[0:511]; reg [8:0] memadr_12; always @(posedge sys_clk) begin if (data_port_we[5]) data_mem_grain5[data_port_adr] <= data_port_dat_w[47:40]; memadr_12 <= data_port_adr; end assign data_port_dat_r[47:40] = data_mem_grain5[memadr_12]; reg [7:0] data_mem_grain6[0:511]; reg [8:0] memadr_13; always @(posedge sys_clk) begin if (data_port_we[6]) data_mem_grain6[data_port_adr] <= data_port_dat_w[55:48]; memadr_13 <= data_port_adr; end assign data_port_dat_r[55:48] = data_mem_grain6[memadr_13]; reg [7:0] data_mem_grain7[0:511]; reg [8:0] memadr_14; always @(posedge sys_clk) begin if (data_port_we[7]) data_mem_grain7[data_port_adr] <= data_port_dat_w[63:56]; memadr_14 <= data_port_adr; end assign data_port_dat_r[63:56] = data_mem_grain7[memadr_14]; reg [7:0] data_mem_grain8[0:511]; reg [8:0] memadr_15; always @(posedge sys_clk) begin if (data_port_we[8]) data_mem_grain8[data_port_adr] <= data_port_dat_w[71:64]; memadr_15 <= data_port_adr; end assign data_port_dat_r[71:64] = data_mem_grain8[memadr_15]; reg [7:0] data_mem_grain9[0:511]; reg [8:0] memadr_16; always @(posedge sys_clk) begin if (data_port_we[9]) data_mem_grain9[data_port_adr] <= data_port_dat_w[79:72]; memadr_16 <= data_port_adr; end assign data_port_dat_r[79:72] = data_mem_grain9[memadr_16]; reg [7:0] data_mem_grain10[0:511]; reg [8:0] memadr_17; always @(posedge sys_clk) begin if (data_port_we[10]) data_mem_grain10[data_port_adr] <= data_port_dat_w[87:80]; memadr_17 <= data_port_adr; end assign data_port_dat_r[87:80] = data_mem_grain10[memadr_17]; reg [7:0] data_mem_grain11[0:511]; reg [8:0] memadr_18; always @(posedge sys_clk) begin if (data_port_we[11]) data_mem_grain11[data_port_adr] <= data_port_dat_w[95:88]; memadr_18 <= data_port_adr; end assign data_port_dat_r[95:88] = data_mem_grain11[memadr_18]; reg [7:0] data_mem_grain12[0:511]; reg [8:0] memadr_19; always @(posedge sys_clk) begin if (data_port_we[12]) data_mem_grain12[data_port_adr] <= data_port_dat_w[103:96]; memadr_19 <= data_port_adr; end assign data_port_dat_r[103:96] = data_mem_grain12[memadr_19]; reg [7:0] data_mem_grain13[0:511]; reg [8:0] memadr_20; always @(posedge sys_clk) begin if (data_port_we[13]) data_mem_grain13[data_port_adr] <= data_port_dat_w[111:104]; memadr_20 <= data_port_adr; end assign data_port_dat_r[111:104] = data_mem_grain13[memadr_20]; reg [7:0] data_mem_grain14[0:511]; reg [8:0] memadr_21; always @(posedge sys_clk) begin if (data_port_we[14]) data_mem_grain14[data_port_adr] <= data_port_dat_w[119:112]; memadr_21 <= data_port_adr; end assign data_port_dat_r[119:112] = data_mem_grain14[memadr_21]; reg [7:0] data_mem_grain15[0:511]; reg [8:0] memadr_22; always @(posedge sys_clk) begin if (data_port_we[15]) data_mem_grain15[data_port_adr] <= data_port_dat_w[127:120]; memadr_22 <= data_port_adr; end assign data_port_dat_r[127:120] = data_mem_grain15[memadr_22]; (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_1 ( .C(sys_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl0), .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_2 ( .C(sys_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl0_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl0), .Q(sys_rst) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_3 ( .C(sys4x_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl1), .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_4 ( .C(sys4x_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl1_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl1), .Q(xilinxasyncresetsynchronizerimpl1_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_5 ( .C(sys4x_dqs_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl2), .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_6 ( .C(sys4x_dqs_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl2_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl2), .Q(xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_7 ( .C(idelay_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl3), .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_8 ( .C(idelay_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl3_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl3), .Q(idelay_rst) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_9 ( .C(clk100_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl4), .Q(xilinxasyncresetsynchronizerimpl4_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_10 ( .C(clk100_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl4_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl4), .Q(clk100_rst) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_11 ( .C(sata_tx_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl5), .Q(xilinxasyncresetsynchronizerimpl5_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_12 ( .C(sata_tx_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl5_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl5), .Q(sata_tx_rst) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_13 ( .C(sata_rx_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl6), .Q(xilinxasyncresetsynchronizerimpl6_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_14 ( .C(sata_rx_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl6_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl6), .Q(sata_rx_rst) ); endmodule