38 lines
1.5 KiB
ReStructuredText
38 lines
1.5 KiB
ReStructuredText
LiteX SATA demo
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~~~~~~~~~~~~~~~
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This example design features a Litex SoC based around VexRiscv soft CPU.
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It also includes a DDR controller and a SATA core.
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The design targets the `Nexys Video <https://digilent.com/reference/programmable-logic/nexys-video/start>`_ board,
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mounting an Artix-7 200T FPGA, and the `FMC adapter board <https://github.com/antmicro/fmc-sata-adapter>`_,
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mounting an M.2 SSD.
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To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs.
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Then depending on your hardware, run:
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.. code-block:: bash
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:name: example-litex-sata-nexys-video-group
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TARGET="nexys_video" make -C litex_sata_demo
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At completion, the bitstreams are located in the build directory:
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.. code-block:: bash
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litex_sata_demo/build/<board>
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.. NOTE::
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To generate the source files for this test, the following packages were used:
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``enjoy-digital/litex@95b310ee0f0d9e78e00eb32b71324b25265da4f4``,
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``enjoy-digital/litesata@fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7``,
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``enjoy-digital/litedram@2c60861929a317af697267d6219da43d10dcf1fa``,
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``enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91``,
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``litex-hub/litex-boards@ea58ef94a784308ae024a1d201d603bc8459a590``,
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and
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``m-labs/migen@c50ecdebd0e93c90ff44ca2e13d9f55fa97947d5``.
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.. NOTE::
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The generated verilog design file (litesata.v) contains a couple of fixes to properly work with the Yosys+VPR flow.
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The fixes are around the GTP high speed transceivers hard blocks.
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