341 lines
11 KiB
Tcl
341 lines
11 KiB
Tcl
################################################################################
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# IO constraints
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################################################################################
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# serial:0.tx
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set_property LOC AA19 [get_ports {serial_tx}]
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set_property IOSTANDARD LVCMOS33 [get_ports {serial_tx}]
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# serial:0.rx
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set_property LOC V18 [get_ports {serial_rx}]
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set_property IOSTANDARD LVCMOS33 [get_ports {serial_rx}]
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# cpu_reset:0
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set_property LOC G4 [get_ports {cpu_reset}]
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set_property IOSTANDARD LVCMOS15 [get_ports {cpu_reset}]
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# clk100:0
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set_property LOC R4 [get_ports {clk100}]
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set_property IOSTANDARD LVCMOS33 [get_ports {clk100}]
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# ddram:0.a
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set_property LOC M2 [get_ports {ddram_a[0]}]
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set_property SLEW FAST [get_ports {ddram_a[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}]
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# ddram:0.a
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set_property LOC M5 [get_ports {ddram_a[1]}]
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set_property SLEW FAST [get_ports {ddram_a[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}]
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# ddram:0.a
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set_property LOC M3 [get_ports {ddram_a[2]}]
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set_property SLEW FAST [get_ports {ddram_a[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}]
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# ddram:0.a
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set_property LOC M1 [get_ports {ddram_a[3]}]
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set_property SLEW FAST [get_ports {ddram_a[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}]
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# ddram:0.a
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set_property LOC L6 [get_ports {ddram_a[4]}]
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set_property SLEW FAST [get_ports {ddram_a[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}]
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# ddram:0.a
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set_property LOC P1 [get_ports {ddram_a[5]}]
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set_property SLEW FAST [get_ports {ddram_a[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}]
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# ddram:0.a
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set_property LOC N3 [get_ports {ddram_a[6]}]
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set_property SLEW FAST [get_ports {ddram_a[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}]
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# ddram:0.a
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set_property LOC N2 [get_ports {ddram_a[7]}]
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set_property SLEW FAST [get_ports {ddram_a[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}]
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# ddram:0.a
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set_property LOC M6 [get_ports {ddram_a[8]}]
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set_property SLEW FAST [get_ports {ddram_a[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}]
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# ddram:0.a
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set_property LOC R1 [get_ports {ddram_a[9]}]
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set_property SLEW FAST [get_ports {ddram_a[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}]
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# ddram:0.a
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set_property LOC L5 [get_ports {ddram_a[10]}]
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set_property SLEW FAST [get_ports {ddram_a[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}]
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# ddram:0.a
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set_property LOC N5 [get_ports {ddram_a[11]}]
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set_property SLEW FAST [get_ports {ddram_a[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}]
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# ddram:0.a
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set_property LOC N4 [get_ports {ddram_a[12]}]
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set_property SLEW FAST [get_ports {ddram_a[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}]
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# ddram:0.a
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set_property LOC P2 [get_ports {ddram_a[13]}]
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set_property SLEW FAST [get_ports {ddram_a[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}]
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# ddram:0.a
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set_property LOC P6 [get_ports {ddram_a[14]}]
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set_property SLEW FAST [get_ports {ddram_a[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}]
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# ddram:0.ba
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set_property LOC L3 [get_ports {ddram_ba[0]}]
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set_property SLEW FAST [get_ports {ddram_ba[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}]
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# ddram:0.ba
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set_property LOC K6 [get_ports {ddram_ba[1]}]
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set_property SLEW FAST [get_ports {ddram_ba[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}]
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# ddram:0.ba
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set_property LOC L4 [get_ports {ddram_ba[2]}]
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set_property SLEW FAST [get_ports {ddram_ba[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}]
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# ddram:0.ras_n
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set_property LOC J4 [get_ports {ddram_ras_n}]
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set_property SLEW FAST [get_ports {ddram_ras_n}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}]
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# ddram:0.cas_n
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set_property LOC K3 [get_ports {ddram_cas_n}]
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set_property SLEW FAST [get_ports {ddram_cas_n}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}]
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# ddram:0.we_n
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set_property LOC L1 [get_ports {ddram_we_n}]
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set_property SLEW FAST [get_ports {ddram_we_n}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}]
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# ddram:0.dm
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set_property LOC G3 [get_ports {ddram_dm[0]}]
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set_property SLEW FAST [get_ports {ddram_dm[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}]
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# ddram:0.dm
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set_property LOC F1 [get_ports {ddram_dm[1]}]
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set_property SLEW FAST [get_ports {ddram_dm[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}]
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# ddram:0.dq
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set_property LOC G2 [get_ports {ddram_dq[0]}]
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set_property SLEW FAST [get_ports {ddram_dq[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}]
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# ddram:0.dq
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set_property LOC H4 [get_ports {ddram_dq[1]}]
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set_property SLEW FAST [get_ports {ddram_dq[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}]
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# ddram:0.dq
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set_property LOC H5 [get_ports {ddram_dq[2]}]
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set_property SLEW FAST [get_ports {ddram_dq[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}]
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# ddram:0.dq
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set_property LOC J1 [get_ports {ddram_dq[3]}]
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set_property SLEW FAST [get_ports {ddram_dq[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}]
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# ddram:0.dq
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set_property LOC K1 [get_ports {ddram_dq[4]}]
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set_property SLEW FAST [get_ports {ddram_dq[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}]
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# ddram:0.dq
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set_property LOC H3 [get_ports {ddram_dq[5]}]
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set_property SLEW FAST [get_ports {ddram_dq[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}]
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# ddram:0.dq
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set_property LOC H2 [get_ports {ddram_dq[6]}]
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set_property SLEW FAST [get_ports {ddram_dq[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}]
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# ddram:0.dq
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set_property LOC J5 [get_ports {ddram_dq[7]}]
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set_property SLEW FAST [get_ports {ddram_dq[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}]
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# ddram:0.dq
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set_property LOC E3 [get_ports {ddram_dq[8]}]
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set_property SLEW FAST [get_ports {ddram_dq[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}]
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# ddram:0.dq
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set_property LOC B2 [get_ports {ddram_dq[9]}]
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set_property SLEW FAST [get_ports {ddram_dq[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}]
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# ddram:0.dq
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set_property LOC F3 [get_ports {ddram_dq[10]}]
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set_property SLEW FAST [get_ports {ddram_dq[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}]
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# ddram:0.dq
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set_property LOC D2 [get_ports {ddram_dq[11]}]
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set_property SLEW FAST [get_ports {ddram_dq[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}]
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# ddram:0.dq
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set_property LOC C2 [get_ports {ddram_dq[12]}]
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set_property SLEW FAST [get_ports {ddram_dq[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}]
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# ddram:0.dq
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set_property LOC A1 [get_ports {ddram_dq[13]}]
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set_property SLEW FAST [get_ports {ddram_dq[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}]
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# ddram:0.dq
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set_property LOC E2 [get_ports {ddram_dq[14]}]
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set_property SLEW FAST [get_ports {ddram_dq[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}]
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# ddram:0.dq
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set_property LOC B1 [get_ports {ddram_dq[15]}]
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set_property SLEW FAST [get_ports {ddram_dq[15]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}]
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# ddram:0.dqs_p
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set_property LOC K2 [get_ports {ddram_dqs_p[0]}]
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set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}]
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# ddram:0.dqs_p
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set_property LOC E1 [get_ports {ddram_dqs_p[1]}]
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set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}]
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# ddram:0.dqs_n
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set_property LOC J2 [get_ports {ddram_dqs_n[0]}]
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set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}]
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# ddram:0.dqs_n
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set_property LOC D1 [get_ports {ddram_dqs_n[1]}]
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set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}]
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# ddram:0.clk_p
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set_property LOC P5 [get_ports {ddram_clk_p}]
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set_property SLEW FAST [get_ports {ddram_clk_p}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}]
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# ddram:0.clk_n
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set_property LOC P4 [get_ports {ddram_clk_n}]
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set_property SLEW FAST [get_ports {ddram_clk_n}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}]
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# ddram:0.cke
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set_property LOC J6 [get_ports {ddram_cke}]
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set_property SLEW FAST [get_ports {ddram_cke}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}]
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# ddram:0.odt
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set_property LOC K4 [get_ports {ddram_odt}]
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set_property SLEW FAST [get_ports {ddram_odt}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}]
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# ddram:0.reset_n
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set_property LOC G1 [get_ports {ddram_reset_n}]
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set_property SLEW FAST [get_ports {ddram_reset_n}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_reset_n}]
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# fmc2sata:0.clk_p
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set_property LOC F10 [get_ports {fmc2sata_clk_p}]
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# fmc2sata:0.clk_n
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set_property LOC E10 [get_ports {fmc2sata_clk_n}]
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# fmc2sata:0.tx_p
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set_property LOC D7 [get_ports {fmc2sata_tx_p}]
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# fmc2sata:0.tx_n
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set_property LOC C7 [get_ports {fmc2sata_tx_n}]
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# fmc2sata:0.rx_p
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set_property LOC D9 [get_ports {fmc2sata_rx_p}]
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# fmc2sata:0.rx_n
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set_property LOC C9 [get_ports {fmc2sata_rx_n}]
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# user_led:0
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set_property LOC T14 [get_ports {user_led0}]
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set_property IOSTANDARD LVCMOS25 [get_ports {user_led0}]
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# user_led:1
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set_property LOC T15 [get_ports {user_led1}]
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set_property IOSTANDARD LVCMOS25 [get_ports {user_led1}]
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# user_led:2
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set_property LOC T16 [get_ports {user_led2}]
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set_property IOSTANDARD LVCMOS25 [get_ports {user_led2}]
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# user_led:3
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set_property LOC U16 [get_ports {user_led3}]
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set_property IOSTANDARD LVCMOS25 [get_ports {user_led3}]
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# user_led:4
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set_property LOC V15 [get_ports {user_led4}]
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set_property IOSTANDARD LVCMOS25 [get_ports {user_led4}]
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# user_led:5
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set_property LOC W16 [get_ports {user_led5}]
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set_property IOSTANDARD LVCMOS25 [get_ports {user_led5}]
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# user_led:6
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set_property LOC W15 [get_ports {user_led6}]
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set_property IOSTANDARD LVCMOS25 [get_ports {user_led6}]
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# user_led:7
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set_property LOC Y13 [get_ports {user_led7}]
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set_property IOSTANDARD LVCMOS25 [get_ports {user_led7}]
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# vadj:0
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set_property LOC AA13 [get_ports {vadj[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vadj[0]}]
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# vadj:1
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set_property LOC AB17 [get_ports {vadj[1]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {vadj[1]}]
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################################################################################
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# Design constraints
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################################################################################
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set_property INTERNAL_VREF 0.750 [get_iobanks 35]
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################################################################################
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