32 lines
597 B
Systemverilog
32 lines
597 B
Systemverilog
`timescale 1ns / 1ps `default_nettype none
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module top (
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input wire logic clk,
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btnc,
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sw,
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output logic [3:0] anode,
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output logic [7:0] segment
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);
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logic [15:0] digitData;
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timer TC0 (
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.clk(clk),
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.reset(btnc),
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.run(sw),
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.digit0(digitData[3:0]),
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.digit1(digitData[7:4]),
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.digit2(digitData[11:8]),
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.digit3(digitData[15:12])
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);
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display_control SSC0 (
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.clk(clk),
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.reset(btnc),
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.dataIn(digitData),
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.digitDisplay(4'b1111),
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.digitPoint(4'b0100),
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.anode(anode),
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.segment(segment)
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);
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endmodule
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