64 lines
1.0 KiB
Systemverilog
64 lines
1.0 KiB
Systemverilog
`timescale 1ns / 1ps `default_nettype none
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module timer (
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input wire logic clk,
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reset,
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run,
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output logic [3:0] digit0,
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digit1,
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digit2,
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digit3
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);
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logic inc0, inc1, inc2, inc3, inc4;
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logic [23:0] timerCount;
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modify_count #(
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.MOD_VALUE(10)
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) M0 (
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.clk(clk),
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.reset(reset),
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.increment(inc0),
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.rolling_over(inc1),
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.count(digit0)
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);
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modify_count #(
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.MOD_VALUE(10)
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) M1 (
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.clk(clk),
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.reset(reset),
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.increment(inc1),
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.rolling_over(inc2),
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.count(digit1)
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);
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modify_count #(
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.MOD_VALUE(10)
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) M2 (
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.clk(clk),
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.reset(reset),
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.increment(inc2),
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.rolling_over(inc3),
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.count(digit2)
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);
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modify_count #(
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.MOD_VALUE(6)
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) M3 (
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.clk(clk),
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.reset(reset),
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.increment(inc3),
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.rolling_over(inc4),
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.count(digit3)
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);
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time_counter #(
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.MOD_VALUE(1000000)
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) T0 (
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.clk(clk),
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.reset(reset),
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.increment(run),
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.rolling_over(inc0),
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.count(timerCount)
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);
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endmodule
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