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< p > Richard Stallman and contributors. GCC, the GNU Compiler Collection. May 1987. URL: < a class = "reference external" href = "https://gcc.gnu.org/" > https://gcc.gnu.org/< / a > .< / p >
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< p > Richard Stallman and GNU Project. GDB: The GNU Project Debugger. 1986. URL: < a class = "reference external" href = "https://www.gnu.org/software/gdb/" > https://www.gnu.org/software/gdb/< / a > .< / p >
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< p > Kevin Thibedeau. Symbolator, a component diagramming tool for VHDL and Verilog. URL: < a class = "reference external" href = "https://kevinpt.github.io/symbolator" > https://kevinpt.github.io/symbolator< / a > .< / p >
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< p > Stephen Williams and contributors. Icarus Verilog, a Verilog simulation and synthesis tool. URL: < a class = "reference external" href = "http://iverilog.icarus.com/" > http://iverilog.icarus.com/< / a > .< / p >
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< p > Claire Wolf and contributors. SymbiYosys: front-end for Yosys-based formal verification flows. URL: < a class = "reference external" href = "https://github.com/YosysHQ/SymbiYosys" > https://github.com/YosysHQ/SymbiYosys< / a > .< / p >
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< p > Claire Wolf and contributors. Yosys Open SYnthesis Suite. URL: < a class = "reference external" href = "https://github.com/YosysHQ/yosys" > https://github.com/YosysHQ/yosys< / a > .< / p >
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< p > Clifford Wolf and Johann Glaser. A Free Verilog Synthesis Suite. In < em > Proceedings of Austrochip 2013< / em > . 2013. URL: < a class = "reference external" href = "https://yosyshq.net/yosys/" > https://yosyshq.net/yosys/< / a > .< / p >
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