f4pga/common_modules: let VprArgs accept cwd of type Path

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>

f4pga/common.py

@@ -28,13 +28,13 @@ from re import match as re_match, finditer as re_finditer
 class F4PGAException(Exception):
     def __init__(self, message = 'unknown exception'):
         self.message = message
-    
+
     def __repr__(self):
         return f'F4PGAException(message = \'{self.message}\')'
-    
+
     def __str__(self):
         return self.message
-        
+
 
 def decompose_depname(name: str):
     spec = 'req'
@@ -188,7 +188,7 @@ def vpr(mode: str, vprargs: VprArgs, cwd=None):
         '--read_rr_graph', vprargs.rr_graph,
         '--read_router_lookahead', vprargs.lookahead,
         '--read_placement_delay_lookup', vprargs.place_delay
-    ] + modeargs + vprargs.optional), cwd=cwd)
+    ] + modeargs + vprargs.optional), cwd=str(cwd))
 
 
 

f4pga/common_modules/analysis.py

@@ -39,7 +39,7 @@ class analysisModule(Module):
         }
 
     def execute(self, ctx: ModuleContext):
-        build_dir = str(Path(ctx.takes.eblif).parent)
+        build_dir = Path(ctx.takes.eblif).parent
 
         vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else []
 

f4pga/common_modules/pack.py

@@ -50,7 +50,7 @@ class PackModule(Module):
                 ctx.values,
                 sdc_file=ctx.takes.sdc
             ),
-            cwd=str(build_dir)
+            cwd=build_dir
         )
 
         og_log = build_dir / 'vpr_stdout.log'

f4pga/common_modules/place.py

@@ -65,7 +65,7 @@ class PlaceModule(Module):
                 sdc_file=ctx.takes.sdc,
                 vpr_extra_opts=['--fix_clusters', place_constraints]
             ),
-            cwd=str(build_dir)
+            cwd=build_dir
         )
 
         # VPR names output on its own. If user requested another name, the
@@ -79,7 +79,7 @@ class PlaceModule(Module):
             Path(default_output_name(str(place_constraints))).rename(ctx.outputs.place)
 
         yield 'Saving log...'
-        save_vpr_log('place.log', build_dir=str(build_dir))
+        save_vpr_log('place.log', build_dir=build_dir)
 
     def __init__(self, _):
         self.name = 'place'

f4pga/common_modules/route.py

@@ -47,14 +47,14 @@ class RouteModule(Module):
                 ctx.values,
                 sdc_file=ctx.takes.sdc
             ),
-            cwd=str(build_dir)
+            cwd=build_dir
         )
 
         if ctx.is_output_explicit('route'):
             route_place_file(ctx).rename(ctx.outputs.route)
 
         yield 'Saving log...'
-        save_vpr_log('route.log', build_dir=str(build_dir))
+        save_vpr_log('route.log', build_dir=build_dir)
 
     def __init__(self, _):
         self.name = 'route'