f4pga/modules/{analysis|route}: fix vpr_options (#618)

f4pga/flows/common.py

@@ -110,21 +110,25 @@ class VprArgs:
     optional: list
 
     def __init__(
-        self, share: str, eblif, values: Namespace, sdc_file: "str | None" = None, vpr_extra_opts: "list | None" = None
+        self,
+        share: str,
+        eblif,
+        arch_def,
+        lookahead,
+        rr_graph,
+        place_delay,
+        device_name,
+        vpr_options={},
+        sdc_file: "str | None" = None,
     ):
         self.arch_dir = str(Path(share) / "arch")
-        self.arch_def = values.arch_def
+        self.arch_def = arch_def
-        self.lookahead = values.rr_graph_lookahead_bin
+        self.lookahead = lookahead
-        self.rr_graph = values.rr_graph_real_bin
+        self.rr_graph = rr_graph
-        self.place_delay = values.vpr_place_delay
+        self.place_delay = place_delay
-        self.device_name = values.vpr_grid_layout_name
+        self.device_name = device_name
         self.eblif = str(Path(eblif).resolve())
-        if values.vpr_options is not None:
+        self.optional = options_dict_to_list(vpr_options)
-            self.optional = options_dict_to_list(values.vpr_options)
-        else:
-            self.optional = []
-        if vpr_extra_opts is not None:
-            self.optional += vpr_extra_opts
         if sdc_file is not None:
             self.optional += ["--sdc_file", sdc_file]
 

f4pga/flows/modules/analysis.py

@@ -41,10 +41,22 @@ class analysisModule(Module):
     def execute(self, ctx: ModuleContext):
         build_dir = Path(ctx.takes.eblif).parent
 
-        vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else []
-
         yield "Analysis with VPR..."
-        common_vpr("analysis", VprArgs(ctx.share, ctx.takes.eblif, ctx.values, sdc_file=ctx.takes.sdc), cwd=build_dir)
+        common_vpr(
+            "analysis",
+            VprArgs(
+                share=ctx.share,
+                eblif=ctx.takes.eblif,
+                arch_def=ctx.values.arch_def,
+                lookahead=ctx.values.rr_graph_lookahead_bin,
+                rr_graph=ctx.values.rr_graph_real_bin,
+                place_delay=ctx.values.vpr_place_delay,
+                device_name=ctx.values.vpr_grid_layout_name,
+                vpr_options=ctx.values.vpr_options if ctx.values.vpr_options else {},
+                sdc_file=ctx.takes.sdc,
+            ),
+            cwd=build_dir,
+        )
 
         if ctx.is_output_explicit("merged_post_implementation_v"):
             Path(analysis_merged_post_implementation_file(ctx)).rename(ctx.outputs.merged_post_implementation_v)

f4pga/flows/modules/fasm.py

@@ -31,7 +31,16 @@ class FasmModule(Module):
     def execute(self, ctx: ModuleContext):
         build_dir = str(Path(ctx.takes.eblif).parent)
 
-        vprargs = VprArgs(ctx.share, ctx.takes.eblif, ctx.values)
+        vprargs = VprArgs(
+            share=ctx.share,
+            eblif=ctx.takes.eblif,
+            arch_def=ctx.values.arch_def,
+            lookahead=ctx.values.rr_graph_lookahead_bin,
+            rr_graph=ctx.values.rr_graph_real_bin,
+            place_delay=ctx.values.vpr_place_delay,
+            device_name=ctx.values.vpr_grid_layout_name,
+            vpr_options=ctx.values.vpr_options if ctx.values.vpr_options else {},
+        )
 
         optional = []
         if ctx.values.pnr_corner is not None:

f4pga/flows/modules/pack.py

@@ -42,7 +42,21 @@ class PackModule(Module):
         build_dir = Path(ctx.outputs.net).parent
 
         yield "Packing with VPR..."
-        common_vpr("pack", VprArgs(ctx.share, ctx.takes.eblif, ctx.values, sdc_file=ctx.takes.sdc), cwd=build_dir)
+        common_vpr(
+            "pack",
+            VprArgs(
+                share=ctx.share,
+                eblif=ctx.takes.eblif,
+                arch_def=ctx.values.arch_def,
+                lookahead=ctx.values.rr_graph_lookahead_bin,
+                rr_graph=ctx.values.rr_graph_real_bin,
+                place_delay=ctx.values.vpr_place_delay,
+                device_name=ctx.values.vpr_grid_layout_name,
+                vpr_options=ctx.values.vpr_options if ctx.values.vpr_options else {},
+                sdc_file=ctx.takes.sdc,
+            ),
+            cwd=build_dir,
+        )
 
         og_log = build_dir / "vpr_stdout.log"
 

f4pga/flows/modules/place.py

@@ -41,21 +41,25 @@ class PlaceModule(Module):
         return {"place": default_output_name(ctx.takes.eblif)}
 
     def execute(self, ctx: ModuleContext):
-        place_constraints = ctx.takes.place_constraints
-
         build_dir = ctx.takes.build_dir
 
-        vpr_options = ["--fix_clusters", place_constraints] if place_constraints else []
+        vpr_options = ctx.values.vpr_options if ctx.values.vpr_options else {}
+        if ctx.takes.place_constraints:
+            vpr_options.update({"fix_clusters": ctx.takes.place_constraints})
 
         yield "Running VPR..."
         common_vpr(
             "place",
             VprArgs(
-                ctx.share,
+                share=ctx.share,
-                ctx.takes.eblif,
+                eblif=ctx.takes.eblif,
-                ctx.values,
+                arch_def=ctx.values.arch_def,
+                lookahead=ctx.values.rr_graph_lookahead_bin,
+                rr_graph=ctx.values.rr_graph_real_bin,
+                place_delay=ctx.values.vpr_place_delay,
+                device_name=ctx.values.vpr_grid_layout_name,
+                vpr_options=vpr_options,
                 sdc_file=ctx.takes.sdc,
-                vpr_extra_opts=["--fix_clusters", place_constraints],
             ),
             cwd=build_dir,
         )

f4pga/flows/modules/route.py

@@ -34,10 +34,22 @@ class RouteModule(Module):
     def execute(self, ctx: ModuleContext):
         build_dir = Path(ctx.takes.eblif).parent
 
-        vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else []
-
         yield "Routing with VPR..."
-        common_vpr("route", VprArgs(ctx.share, ctx.takes.eblif, ctx.values, sdc_file=ctx.takes.sdc), cwd=build_dir)
+        common_vpr(
+            "route",
+            VprArgs(
+                share=ctx.share,
+                eblif=ctx.takes.eblif,
+                arch_def=ctx.values.arch_def,
+                lookahead=ctx.values.rr_graph_lookahead_bin,
+                rr_graph=ctx.values.rr_graph_real_bin,
+                place_delay=ctx.values.vpr_place_delay,
+                device_name=ctx.values.vpr_grid_layout_name,
+                vpr_options=ctx.values.vpr_options if ctx.values.vpr_options else {},
+                sdc_file=ctx.takes.sdc,
+            ),
+            cwd=build_dir,
+        )
 
         if ctx.is_output_explicit("route"):
             route_place_file(ctx).rename(ctx.outputs.route)