From 1f7fb2584793dbab5152abd64739862d05bf7beb Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Mon, 15 Aug 2022 07:03:46 +0200 Subject: [PATCH] f4pga: do not use wildcard imports Signed-off-by: Unai Martinez-Corral --- f4pga/__init__.py | 4 +-- f4pga/common_modules/analysis.py | 8 ++--- f4pga/common_modules/io_rename.py | 3 +- f4pga/common_modules/mkdirs.py | 2 ++ f4pga/common_modules/pack.py | 4 +-- f4pga/common_modules/place.py | 43 ++++++++++++----------- f4pga/common_modules/place_constraints.py | 42 +++++++++------------- f4pga/common_modules/route.py | 14 ++++---- f4pga/common_modules/synth.py | 9 ++--- 9 files changed, 61 insertions(+), 68 deletions(-) diff --git a/f4pga/__init__.py b/f4pga/__init__.py index cc217e7..1ac42db 100755 --- a/f4pga/__init__.py +++ b/f4pga/__init__.py @@ -48,13 +48,13 @@ from colorama import Fore, Style from f4pga.common import ( F4PGAException, ResolutionEnv, + deep, fatal, scan_modules, set_verbosity_level, sfprint, sub as common_sub ) -from f4pga.module import * from f4pga.cache import F4Cache from f4pga.flow_config import ( ProjectFlowConfig, @@ -63,7 +63,7 @@ from f4pga.flow_config import ( open_project_flow_cfg, verify_platform_name ) -from f4pga.module_runner import * +from f4pga.module_runner import ModRunCtx, module_map, module_exec from f4pga.module_inspector import get_module_info from f4pga.stage import Stage from f4pga.argparser import setup_argparser, get_cli_flow_config diff --git a/f4pga/common_modules/analysis.py b/f4pga/common_modules/analysis.py index 1a324a7..065601c 100644 --- a/f4pga/common_modules/analysis.py +++ b/f4pga/common_modules/analysis.py @@ -20,7 +20,7 @@ from pathlib import Path from shutil import move as sh_mv -from f4pga.common import * +from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs from f4pga.module import Module, ModuleContext @@ -42,12 +42,10 @@ class analysisModule(Module): def execute(self, ctx: ModuleContext): build_dir = str(Path(ctx.takes.eblif).parent) - vpr_options = [] - if ctx.values.vpr_options: - vpr_options = options_dict_to_list(ctx.values.vpr_options) + vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else [] yield 'Analysis with VPR...' - vpr( + common_vpr( 'analysis', VprArgs( ctx.share, diff --git a/f4pga/common_modules/io_rename.py b/f4pga/common_modules/io_rename.py index a2cb396..031f161 100644 --- a/f4pga/common_modules/io_rename.py +++ b/f4pga/common_modules/io_rename.py @@ -40,7 +40,6 @@ Accepted module parameters: """ -from f4pga.common import * from f4pga.module import Module, ModuleContext from f4pga.module_runner import get_module @@ -123,4 +122,4 @@ class IORenameModule(Module): if hasattr(module, 'prod_meta'): self.prod_meta = _switch_keys(module.prod_meta, self.rename_produces) -ModuleClass = IORenameModule \ No newline at end of file +ModuleClass = IORenameModule diff --git a/f4pga/common_modules/mkdirs.py b/f4pga/common_modules/mkdirs.py index ad3d6b8..cf1b587 100644 --- a/f4pga/common_modules/mkdirs.py +++ b/f4pga/common_modules/mkdirs.py @@ -26,6 +26,7 @@ the dependency algorithm to lazily create the directories if they become necessa """ from pathlib import Path + from f4pga.module import Module, ModuleContext @@ -49,4 +50,5 @@ class MkDirsModule(Module): self.values = [] self.deps_to_produce = params + ModuleClass = MkDirsModule diff --git a/f4pga/common_modules/pack.py b/f4pga/common_modules/pack.py index f49a28b..f0f616c 100644 --- a/f4pga/common_modules/pack.py +++ b/f4pga/common_modules/pack.py @@ -21,7 +21,7 @@ from pathlib import Path from os import remove as os_remove from shutil import move as sh_mv -from f4pga.common import * +from f4pga.common import vpr_specific_values, noisy_warnings, vpr as common_vpr, VprArgs from f4pga.module import Module, ModuleContext @@ -44,7 +44,7 @@ class PackModule(Module): build_dir = Path(ctx.outputs.net).parent yield 'Packing with VPR...' - vpr( + common_vpr( 'pack', VprArgs( ctx.share, diff --git a/f4pga/common_modules/place.py b/f4pga/common_modules/place.py index e60ae49..258b113 100644 --- a/f4pga/common_modules/place.py +++ b/f4pga/common_modules/place.py @@ -21,35 +21,32 @@ from pathlib import Path import os from shutil import move as sh_mv from re import match as re_match -from f4pga.common import * + +from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs, save_vpr_log from f4pga.module import Module, ModuleContext def default_output_name(place_constraints): - p = place_constraints m = re_match('(.*)\\.[^.]*$', place_constraints) if m: return m.groups()[0] + '.place' - return f'{p}.place' + return f'{place_constraints}.place' def place_constraints_file(ctx: ModuleContext): - p = ctx.takes.place_constraints - if p: - return p, False - p = ctx.takes.io_place - if p: - return p, False + if ctx.takes.place_constraints: + return ctx.takes.place_constraints, False + if ctx.takes.io_place: + return ctx.takes.io_place, False return f'{Path(ctx.takes.eblif).stem}.place', True class PlaceModule(Module): def map_io(self, ctx: ModuleContext): - mapping = {} p, _ = place_constraints_file(ctx) - - mapping['place'] = default_output_name(p) - return mapping + return { + 'place': default_output_name(p) + } def execute(self, ctx: ModuleContext): place_constraints, dummy = place_constraints_file(ctx) @@ -58,14 +55,20 @@ class PlaceModule(Module): with open(place_constraints, 'wb') as f: f.write(b'') - build_dir = str(Path(ctx.takes.eblif).parent) - - vpr_options = ['--fix_clusters', place_constraints] + build_dir = Path(ctx.takes.eblif).parent yield 'Running VPR...' - vprargs = VprArgs(ctx.share, ctx.takes.eblif, ctx.values, - sdc_file=ctx.takes.sdc, vpr_extra_opts=vpr_options) - vpr('place', vprargs, cwd=build_dir) + common_vpr( + 'place', + VprArgs( + ctx.share, + ctx.takes.eblif, + ctx.values, + sdc_file=ctx.takes.sdc, + vpr_extra_opts=['--fix_clusters', place_constraints] + ), + cwd=str(build_dir) + ) # VPR names output on its own. If user requested another name, the # output file should be moved. @@ -79,7 +82,7 @@ class PlaceModule(Module): sh_mv(output_file, ctx.outputs.place) yield 'Saving log...' - save_vpr_log('place.log', build_dir=build_dir) + save_vpr_log('place.log', build_dir=str(build_dir)) def __init__(self, _): self.name = 'place' diff --git a/f4pga/common_modules/place_constraints.py b/f4pga/common_modules/place_constraints.py index 301e71e..16c7474 100644 --- a/f4pga/common_modules/place_constraints.py +++ b/f4pga/common_modules/place_constraints.py @@ -18,7 +18,7 @@ # SPDX-License-Identifier: Apache-2.0 from pathlib import Path -from f4pga.common import * +from f4pga.common import sub as common_sub from f4pga.module import Module, ModuleContext @@ -29,31 +29,23 @@ class PlaceConstraintsModule(Module): } def execute(self, ctx: ModuleContext): - arch_dir = str(Path(ctx.share) / 'arch') - arch_def = str(Path(arch_dir) / ctx.values.device / 'arch.timing.xml') - - database = sub('prjxray-config').decode().replace('\n', '') - - yield 'Generating .place...' - - extra_opts: 'list[str]' - if ctx.values.extra_opts: - extra_opts = options_dict_to_list(ctx.values.extra_opts) - else: - extra_opts = [] - - data = sub(*(['python3', ctx.values.script, - '--net', ctx.takes.net, - '--arch', arch_def, - '--blif', ctx.takes.eblif, - '--input', ctx.takes.io_place, - '--db_root', database, - '--part', ctx.values.part_name] - + extra_opts)) - yield 'Saving place constraint data...' - with open(ctx.outputs.place_constraints, 'wb') as f: - f.write(data) + with Path(ctx.outputs.place_constraints).open('wb') as wfptr: + wfptr.write( + common_sub(*( + [ + 'python3', ctx.values.script, + '--net', ctx.takes.net, + '--arch', str(Path(ctx.share) / 'arch' / ctx.values.device / 'arch.timing.xml'), + '--blif', ctx.takes.eblif, + '--input', ctx.takes.io_place, + '--db_root', common_sub('prjxray-config').decode().replace('\n', ''), + '--part', ctx.values.part_name + ] + ( + options_dict_to_list(ctx.values.extra_opts) if ctx.values.extra_opts else [] + ) + )) + ) def __init__(self, _): self.name = 'place_constraints' diff --git a/f4pga/common_modules/route.py b/f4pga/common_modules/route.py index 5a6fe3c..d528f0d 100644 --- a/f4pga/common_modules/route.py +++ b/f4pga/common_modules/route.py @@ -20,7 +20,7 @@ from pathlib import Path from shutil import move as sh_mv -from f4pga.common import * +from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs, options_dict_to_list, save_vpr_log from f4pga.module import Module, ModuleContext @@ -35,14 +35,12 @@ class RouteModule(Module): } def execute(self, ctx: ModuleContext): - build_dir = str(Path(ctx.takes.eblif).parent) + build_dir = Path(ctx.takes.eblif).parent - vpr_options = [] - if ctx.values.vpr_options: - vpr_options = options_dict_to_list(ctx.values.vpr_options) + vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else [] yield 'Routing with VPR...' - vpr( + common_vpr( 'route', VprArgs( ctx.share, @@ -50,14 +48,14 @@ class RouteModule(Module): ctx.values, sdc_file=ctx.takes.sdc ), - cwd=build_dir + cwd=str(build_dir) ) if ctx.is_output_explicit('route'): sh_mv(route_place_file(ctx), ctx.outputs.route) yield 'Saving log...' - save_vpr_log('route.log', build_dir=build_dir) + save_vpr_log('route.log', build_dir=str(build_dir)) def __init__(self, _): self.name = 'route' diff --git a/f4pga/common_modules/synth.py b/f4pga/common_modules/synth.py index 0c44995..ece9e7f 100755 --- a/f4pga/common_modules/synth.py +++ b/f4pga/common_modules/synth.py @@ -19,7 +19,8 @@ import os from pathlib import Path -from f4pga.common import * + +from f4pga.common import decompose_depname, get_verbosity_level, sub as common_sub from f4pga.module import Module, ModuleContext @@ -57,14 +58,14 @@ def yosys_synth(tcl, tcl_env, verilog_files=[], read_verilog_args=None, log=None verilog_files = [] # Execute YOSYS command - return sub(*(['yosys', '-p', tcl] + optional + verilog_files), env=env) + return common_sub(*(['yosys', '-p', tcl] + optional + verilog_files), env=env) def yosys_conv(tcl, tcl_env, synth_json): # Set up environment for TCL weirdness env = os.environ.copy() env.update(tcl_env) - return sub('yosys', '-p', f'read_json {synth_json}; tcl {tcl}', env=env) + return common_sub('yosys', '-p', f'read_json {synth_json}; tcl {tcl}', env=env) class SynthModule(Module): @@ -113,7 +114,7 @@ class SynthModule(Module): ctx.values.read_verilog_args, ctx.outputs.synth_log) yield f'Splitting in/outs...' - sub('python3', str(split_inouts), '-i', ctx.outputs.json, '-o', + common_sub('python3', str(split_inouts), '-i', ctx.outputs.json, '-o', ctx.outputs.synth_json) if not os.path.isfile(ctx.produces.fasm_extra):