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f4pga/flows/common_modules/route: pass vpr_extra_options 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-08-16 20:49:56 +02:00
parent 7ad00b5c88
commit 2174efa459
1 changed files with 11 additions and 3 deletions
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14
f4pga/flows/modules/route.py
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@ -34,10 +34,18 @@ class RouteModule(Module):
def execute(self, ctx: ModuleContext): def execute(self, ctx: ModuleContext):
build_dir = Path(ctx.takes.eblif).parent build_dir = Path(ctx.takes.eblif).parent
vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else []
yield "Routing with VPR..." yield "Routing with VPR..."
common_vpr("route", VprArgs(ctx.share, ctx.takes.eblif, ctx.values, sdc_file=ctx.takes.sdc), cwd=build_dir) common_vpr(
"route",
VprArgs(
ctx.share,
ctx.takes.eblif,
ctx.values,
sdc_file=ctx.takes.sdc,
vpr_extra_opts=options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else None,
),
cwd=build_dir,
)
if ctx.is_output_explicit("route"): if ctx.is_output_explicit("route"):
route_place_file(ctx).rename(ctx.outputs.route) route_place_file(ctx).rename(ctx.outputs.route)