From 4ebbba1442139fea6c1cb02a33bd058531e378e5 Mon Sep 17 00:00:00 2001
From: Ezra Thomas <46074998+ept221@users.noreply.github.com>
Date: Sat, 21 Jan 2023 12:13:45 -0500
Subject: [PATCH] Grammar fix

---
 docs/flows/f4pga.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/flows/f4pga.rst b/docs/flows/f4pga.rst
index fb7c275..ed33075 100644
--- a/docs/flows/f4pga.rst
+++ b/docs/flows/f4pga.rst
@@ -174,7 +174,7 @@ buffer types that they can use in designs:
 Nevertheless, the actual chips consist only of the ``BUFGCTRL`` primitives,
 which are the most universal and can function as other clock buffer
 primitives from the Xilinx manual. Because of that, only one architecture model
-is required for VPR. The rest of the primitives is mapped to this general
+is required for VPR. The rest of the primitives are mapped to this general
 buffer during the techmapping process. The model of ``BUFGCTRL`` primitive used
 by VPR is called ``BUFGCTR_VPR`` (More information about the architecture
 modeling in VPR can be found in the `VTR FPGA Architecture Description`_).