diff --git a/f4pga/flows/common_modules/synth.py b/f4pga/flows/common_modules/synth.py
index bd6d714..6fae1aa 100755
--- a/f4pga/flows/common_modules/synth.py
+++ b/f4pga/flows/common_modules/synth.py
@@ -53,11 +53,6 @@ class SynthModule(Module):
     def execute(self, ctx: ModuleContext):
         yield f"Synthesizing sources{f': {ctx.takes.sources}...' if get_verbosity_level() >= 2 else f'...'}"
 
-        tcl = f'tcl {str(get_tcl_wrapper_path("synth"))}'
-        args_str = " ".join(ctx.values.read_verilog_args) if ctx.values.read_verilog_args is not None else ""
-        for vfile in ctx.takes.sources:
-            tcl = f"read_verilog {args_str} {vfile}; {tcl}"
-
         # Set up environment for TCL weirdness
         env = environ.copy()
         env.update(
@@ -73,8 +68,19 @@ class SynthModule(Module):
         )
 
         # Execute YOSYS command
+        args_str = "" if ctx.values.read_verilog_args is None else " ".join(ctx.values.read_verilog_args)
         common_sub(
-            *(["yosys", "-p", tcl] + (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else [])),
+            *(
+                [
+                    "yosys",
+                    "-p",
+                    (
+                        " ".join([f"read_verilog {args_str} {vfile};" for vfile in ctx.takes.sources])
+                        + f" tcl {str(get_tcl_wrapper_path())}"
+                    ),
+                ]
+                + (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else [])
+            ),
             env=env,
         )