From 5350ec87f7ed81a4e2688f77041f115eb13291be Mon Sep 17 00:00:00 2001 From: Krzysztof Boronski Date: Tue, 6 Sep 2022 19:26:37 +0200 Subject: [PATCH 1/2] Simplify synth module, always user read_verilog Signed-off-by: Krzysztof Boronski --- f4pga/flows/common_modules/synth.py | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/f4pga/flows/common_modules/synth.py b/f4pga/flows/common_modules/synth.py index 07ab3c1..bd6d714 100755 --- a/f4pga/flows/common_modules/synth.py +++ b/f4pga/flows/common_modules/synth.py @@ -53,16 +53,10 @@ class SynthModule(Module): def execute(self, ctx: ModuleContext): yield f"Synthesizing sources{f': {ctx.takes.sources}...' if get_verbosity_level() >= 2 else f'...'}" - tcl = f"tcl {str(get_tcl_wrapper_path())}" - verilog_files = [] - # Use append read_verilog commands to the scripts for more sophisticated - # input if arguments are specified. Omit direct input throught `yosys` command. - if ctx.values.read_verilog_args: - args_str = " ".join(ctx.values.read_verilog_args) - for vfile in ctx.takes.sources: - tcl = f"read_verilog {args_str} {vfile}; {tcl}" - else: - verilog_files = ctx.takes.sources + tcl = f'tcl {str(get_tcl_wrapper_path("synth"))}' + args_str = " ".join(ctx.values.read_verilog_args) if ctx.values.read_verilog_args is not None else "" + for vfile in ctx.takes.sources: + tcl = f"read_verilog {args_str} {vfile}; {tcl}" # Set up environment for TCL weirdness env = environ.copy() @@ -80,7 +74,7 @@ class SynthModule(Module): # Execute YOSYS command common_sub( - *(["yosys", "-p", tcl] + (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else []) + verilog_files), + *(["yosys", "-p", tcl] + (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else [])), env=env, ) From 409d9ca03c722f6a235bea8a7f610b83feaef8ad Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Wed, 7 Sep 2022 02:19:31 +0200 Subject: [PATCH 2/2] f4pga/flows/common_modules/synth: cleanup Signed-off-by: Unai Martinez-Corral --- f4pga/flows/common_modules/synth.py | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/f4pga/flows/common_modules/synth.py b/f4pga/flows/common_modules/synth.py index bd6d714..6fae1aa 100755 --- a/f4pga/flows/common_modules/synth.py +++ b/f4pga/flows/common_modules/synth.py @@ -53,11 +53,6 @@ class SynthModule(Module): def execute(self, ctx: ModuleContext): yield f"Synthesizing sources{f': {ctx.takes.sources}...' if get_verbosity_level() >= 2 else f'...'}" - tcl = f'tcl {str(get_tcl_wrapper_path("synth"))}' - args_str = " ".join(ctx.values.read_verilog_args) if ctx.values.read_verilog_args is not None else "" - for vfile in ctx.takes.sources: - tcl = f"read_verilog {args_str} {vfile}; {tcl}" - # Set up environment for TCL weirdness env = environ.copy() env.update( @@ -73,8 +68,19 @@ class SynthModule(Module): ) # Execute YOSYS command + args_str = "" if ctx.values.read_verilog_args is None else " ".join(ctx.values.read_verilog_args) common_sub( - *(["yosys", "-p", tcl] + (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else [])), + *( + [ + "yosys", + "-p", + ( + " ".join([f"read_verilog {args_str} {vfile};" for vfile in ctx.takes.sources]) + + f" tcl {str(get_tcl_wrapper_path())}" + ), + ] + + (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else []) + ), env=env, )