From 5e4db92a780e9da8a68cf6b27d1782def97444b8 Mon Sep 17 00:00:00 2001
From: kgugala <kgugala@users.noreply.github.com>
Date: Tue, 10 Dec 2024 00:22:45 +0000
Subject: [PATCH] deploy: 0723f9ca4ea4b686ff9c2e32c9cec56d40de1a62

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 how.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

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@@ -465,7 +465,7 @@ They are created within separate collaborating projects targeting different FPGA
 <ul class="simple">
 <li><p><a class="reference external" href="https://f4pga.readthedocs.io/projects/prjxray/en/latest/index.html" title="(in Project X-Ray v0.0-3807-g72e6371b)"><span class="xref std std-doc">Project X-Ray ➚</span></a> for Xilinx 7-Series</p></li>
 <li><p><a class="reference external" href="http://bygone.clairexen.net/icestorm/">Project IceStorm ➚</a> for Lattice iCE40</p></li>
-<li><p><span class="xref std std-doc">Project Trellis ➚</span> for Lattice ECP5 FPGAs</p></li>
+<li><p><a class="reference external" href="https://prjtrellis.readthedocs.io/en/latest/index.html" title="(in Project Trellis)"><span class="xref std std-doc">Project Trellis ➚</span></a> for Lattice ECP5 FPGAs</p></li>
 </ul>
 <p>More information can be found at <a class="reference external" href="https://f4pga.readthedocs.io/projects/arch-defs/en/latest/index.html" title="(in F4PGA Architecture Definitions vlatest)"><span class="xref std std-doc">F4PGA Architecture Definitions ➚</span></a> and <a class="reference external" href="https://fpga-interchange-schema.readthedocs.io/index.html" title="(in FPGA Interchange Format v0.0-99-gc985b46)"><span class="xref std std-doc">FPGA Interchange ➚</span></a>.</p>
 <p>To prepare a working bitstream for a particular FPGA chip, the toolchain goes through the following stages:</p>