From 6808082757da4e70533320bcfc32cb9a9a91eeda Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Fri, 30 Aug 2019 16:19:54 +0200 Subject: [PATCH] Add more information about SymbiFlow to introduction Signed-off-by: Robert Winkler --- source/images/EDA.svg | 1 + source/images/parts.svg | 1 + source/introduction.rst | 82 +++++++++++++++++++++++++++++++++++++++-- 3 files changed, 81 insertions(+), 3 deletions(-) create mode 100644 source/images/EDA.svg create mode 100644 source/images/parts.svg diff --git a/source/images/EDA.svg b/source/images/EDA.svg new file mode 100644 index 0000000..f278a9c --- /dev/null +++ b/source/images/EDA.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/source/images/parts.svg b/source/images/parts.svg new file mode 100644 index 0000000..97296de --- /dev/null +++ b/source/images/parts.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/source/introduction.rst b/source/introduction.rst index 789e745..2b87743 100644 --- a/source/introduction.rst +++ b/source/introduction.rst @@ -1,8 +1,84 @@ Introduction ============ -This is the documentation for the SymbiFlow open FPGA toolchain project. +SymbiFlow is a Open Source Verilog-to-Bitstream FPGA synthesis flow, +currently targeting Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs. +Think of it as the GCC of FPGAs. -A useful diagram that explains the relationship between various parts/files/programs of the project: +The project aim is to design tools that are highly extendable and multiplatform. -https://docs.google.com/drawings/d/1GwzV6Rs0gbiGI4DznWwG4000BLOcsuYYgYQ0YDqgXHY/edit +EDA Tooling Ecosystem +--------------------- + +For both ASIC- and FPGA-oriented EDA tooling, there are three major areas that +the workflow needs to cover: hardware description, frontend and backend. + +Hardware description languages are generally open, with both established HDLs +such as Verilog and VHDL and emerging software-inspired paradigms like +`Chisel `_, +`SpinalHDL `_ or +`Migen `_. +The major problem lies however in the front- and backend, where previously +there was no established standard, vendor-neutral tooling that would cover +all the necessary components for an end-to-end flow. + +This pertains both to ASIC and FPGA workflows, although SymbiFlow focuses +on the latter (some parts of SymbiFlow will also be useful in the former). + +.. figure:: images/EDA.svg + +Project structure +----------------- + +To achieve SymbiFlow's goal of a complete FOSS FPGA toolchain, +a number of tools and projects are necessary to provide all the needed +components of an end-to-end flow. Thus, SymbiFlow serves as an umbrella +project for several activities, the central of which pertains to the +creation of so-called FPGA "architecture definitions", +i.e. documentation of how specific FPGAs work internally. +More information can be found in the :doc:`Symbiflow Architecture Definitions +<../symbiflow-arch-defs/docs/source/index>` project. + +Those definitions and serve as input to backend tools like +`nextpnr `_ and +`Verilog to Routing `_, and frontend tools +like `Yosys `_. They are created within separate +collaborating projects targeting different FPGAs - :doc:`Project X-Ray +<../prjxray/docs/index>` for Xilinx 7-Series, `Project IceStorm +`_ for Lattice iCE40 and :doc:`Project Trellis +<../prjtrellis/docs/index>` for Lattice ECP5 FPGAs. + +.. figure:: images/parts.svg + +Current status of bitstream documentation +----------------------------------------- + +.. table:: + :align: center + :widths: 40 20 20 20 + + +-----------------+----------+----------+---------+ + | Projects | IceStorm | X-Ray | Trellis | + +=================+==========+==========+=========+ + | **Basic Tiles** | + +-----------------+----------+----------+---------+ + | Logic | Yes | Yes | Yes | + +-----------------+----------+----------+---------+ + | Block RAM | Yes | Partial | N/A | + +-----------------+----------+----------+---------+ + | **Advanced Tiles** | + +-----------------+----------+----------+---------+ + | DSP | Yes | No | Yes | + +-----------------+----------+----------+---------+ + | Hard Blocks | Yes | No | Yes | + +-----------------+----------+----------+---------+ + | Clock Tiles | Yes | Partial | Yes | + +-----------------+----------+----------+---------+ + | IO Tiles | Yes | Partial | Yes | + +-----------------+----------+----------+---------+ + | **Routing** | + +-----------------+----------+----------+---------+ + | Logic | Yes | Yes | Yes | + +-----------------+----------+----------+---------+ + | Clock | Yes | Partial | Yes | + +-----------------+----------+----------+---------+