From 6b4976a028e8a8a3b78711b6471655d3bfe58ed7 Mon Sep 17 00:00:00 2001
From: Unai Martinez-Corral <umartinezcorral@antmicro.com>
Date: Wed, 7 Sep 2022 05:12:25 +0200
Subject: [PATCH] f4pga/wrappers/sh/quicklogic/synth: partially revert 9e327656

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
---
 f4pga/wrappers/sh/quicklogic/synth.f4pga.sh | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh b/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh
index 7b5c34a..232f67f 100755
--- a/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh
+++ b/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh
@@ -108,7 +108,13 @@ else
 fi
 
 yosys_cmds=`echo ${EXTRA_ARGS[*]} | python3 -m f4pga.utils.quicklogic.convert_compile_opts`
+if [ ! -z "${yosys_cmds}" ]; then yosys_cmds="${yosys_cmds//$'\n'/'; '}; "; fi
+
+yosys_read_cmds=''
+for f in ${VERILOG_FILES[*]}; do
+  yosys_read_cmds="read_verilog ${f}; $yosys_read_cmds"
+done
+
 `which yosys` \
-  -p "${yosys_cmds//$'\n'/'; '} tcl $(python3 -m f4pga.wrappers.tcl "${FAMILY}")" \
-  -l "${TOP}_synth.log" \
-  ${VERILOG_FILES[*]}
+  -p "$yosys_cmds $yosys_read_cmds tcl $(python3 -m f4pga.wrappers.tcl "${FAMILY}")" \
+  -l "${TOP}_synth.log"