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f4pga/wrappers/sh/quicklogic/synth: partially revert 9e327656 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-09-07 05:12:25 +02:00
parent 4170bc49ac
commit 6b4976a028
1 changed files with 9 additions and 3 deletions
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12
f4pga/wrappers/sh/quicklogic/synth.f4pga.sh
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@ -108,7 +108,13 @@ else
fi fi
yosys_cmds=`echo ${EXTRA_ARGS[*]} | python3 -m f4pga.utils.quicklogic.convert_compile_opts` yosys_cmds=`echo ${EXTRA_ARGS[*]} | python3 -m f4pga.utils.quicklogic.convert_compile_opts`
if [ ! -z "${yosys_cmds}" ]; then yosys_cmds="${yosys_cmds//$'\n'/'; '}; "; fi
yosys_read_cmds=''
for f in ${VERILOG_FILES[*]}; do
yosys_read_cmds="read_verilog ${f}; $yosys_read_cmds"
done
`which yosys` \ `which yosys` \
-p "${yosys_cmds//$'\n'/'; '} tcl $(python3 -m f4pga.wrappers.tcl "${FAMILY}")" \ -p "$yosys_cmds $yosys_read_cmds tcl $(python3 -m f4pga.wrappers.tcl "${FAMILY}")" \
-l "${TOP}_synth.log" \ -l "${TOP}_synth.log"
${VERILOG_FILES[*]}