From 93392fa9cb1ddf3ec1b07d351c71539becbef42c Mon Sep 17 00:00:00 2001
From: Pawel Czarnecki <pczarnecki@antmicro.com>
Date: Fri, 8 Jul 2022 10:44:50 +0200
Subject: [PATCH] platforms: eos-s3: add fasm2bels stage

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
---
 .github/eos-s3_test.json                      |  3 +-
 f4pga/platforms/ql-eos-s3.json                | 44 +++++++++++++-
 .../wrappers/sh/quicklogic/fasm2bels.f4pga.sh | 60 ++++++++++++-------
 3 files changed, 82 insertions(+), 25 deletions(-)

diff --git a/.github/eos-s3_test.json b/.github/eos-s3_test.json
index aa858c7..6e4c63d 100644
--- a/.github/eos-s3_test.json
+++ b/.github/eos-s3_test.json
@@ -19,7 +19,8 @@
             "sdc-in": "eos-s3/btn_counter/dummy.sdc"
         },
         "values": {
-            "part": "ql-eos-s3"
+            "part": "ql-eos-s3",
+            "part_name": "PD64"
         }
     }
 }
diff --git a/f4pga/platforms/ql-eos-s3.json b/f4pga/platforms/ql-eos-s3.json
index dcacf07..314b929 100644
--- a/f4pga/platforms/ql-eos-s3.json
+++ b/f4pga/platforms/ql-eos-s3.json
@@ -17,7 +17,8 @@
         "bitstream_bitheader": "common:generic_script_wrapper",
         "bitstream_binary": "common:generic_script_wrapper",
         "bitstream_jlink": "common:generic_script_wrapper",
-        "bitstream_openocd": "common:generic_script_wrapper"
+        "bitstream_openocd": "common:generic_script_wrapper",
+        "fasm2bels": "common:generic_script_wrapper"
     },
 
     "values": {
@@ -426,6 +427,47 @@
                     "#3": "${:iomux_binary}"
                 }
             }
+        },
+        "fasm2bels": {
+            "params": {
+                "stage_name": "fasm2bels",
+                "script": "symbiflow_fasm2bels",
+                "outputs": {
+                    "fasm2bels_verilog": {
+                        "mode": "file",
+                        "file": "${:bitstream}.v",
+                        "target": "${:bitstream}.v"
+                    },
+                    "fasm2bels_pcf": {
+                        "mode": "file",
+                        "file": "${:bitstream}.pcf",
+                        "target": "${:bitstream}.pcf"
+                    },
+                    "fasm2bels_qcf": {
+                        "mode": "file",
+                        "file": "${:bitstream}.qcf",
+                        "target": "${:bitstream}.qcf"
+                    },
+                    "fasm2bels_log": {
+                        "mode": "stdout",
+                        "target": "${:bitstream}.log"
+                    }
+                },
+                "inputs": {
+                    "device": "${device}",
+                    "part": "${part_name}",
+                    "pcf": "${:pcf}",
+                    "bit": "${:bitstream}",
+                    "out-verilog": "${:bitstream}.v",
+                    "out-pcf": "${:bitstream}.pcf",
+                    "out-qcf": "${:bitstream}.qcf",
+                    "$F4PGA_INSTALL_DIR": "${shareDir}/../../../../",
+                    "$FPGA_FAM": "eos-s3",
+                    "$PATH": "${shareDir}/../../../conda/envs/eos-s3/bin/:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin",
+                    "$SHARE_DIR_PATH": "${shareDir}",
+                    "$BIN_DIR_PATH": "${binDir}"
+                }
+            }
         }
     }
 }
diff --git a/f4pga/wrappers/sh/quicklogic/fasm2bels.f4pga.sh b/f4pga/wrappers/sh/quicklogic/fasm2bels.f4pga.sh
index 60767e4..c48707c 100755
--- a/f4pga/wrappers/sh/quicklogic/fasm2bels.f4pga.sh
+++ b/f4pga/wrappers/sh/quicklogic/fasm2bels.f4pga.sh
@@ -21,8 +21,8 @@ set -e
 SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_SHARE_DIR"}
 BIN_DIR_PATH=${BIN_DIR_PATH:="$F4PGA_BIN_DIR"}
 
-OPTS=d:P:p:b:
-LONGOPTS=device:,part:,pcf:,bit:,
+OPTS=d:P:p:b:v:o:q
+LONGOPTS=device:,part:,pcf:,bit:,out-verilog:,out-pcf:,out-qcf:,
 
 PARSED_OPTS=`getopt --options=${OPTS} --longoptions=${LONGOPTS} --name $0 -- "$@"`
 eval set -- "${PARSED_OPTS}"
@@ -31,6 +31,9 @@ DEVICE=""
 PART=""
 PCF=""
 BIT=""
+OUT_VERILOG=""
+OUT_PCF=""
+OUT_QCF=""
 
 while true; do
 	case "$1" in
@@ -50,6 +53,18 @@ while true; do
 			BIT=$2
 			shift 2
 			;;
+		-v|--out-verilog)
+			OUT_VERILOG=$2
+			shift 2
+			;;
+		-o|--out-pcf)
+			OUT_PCF=$2
+			shift 2
+			;;
+		-q|--out-qcf)
+			OUT_QCF=$2
+			shift 2
+			;;
 		--)
 			break
 			;;
@@ -67,27 +82,26 @@ if [ -z $BIT ]; then
 fi
 
 
-# Run fasm2bels
-if [[ "$DEVICE" =~ ^(ql-eos-s3|ql-pp3e)$ ]]; then
-
-    VPR_DB=`readlink -f ${SHARE_DIR_PATH}/arch/${DEVICE}_wlcsp/db_phy.pickle`
-    FASM2BELS=`readlink -f ${SHARE_DIR_PATH}/scripts/fasm2bels.py`
-    FASM2BELS_DEVICE=${DEVICE/ql-/}
-    VERILOG_FILE="${BIT}.v"
-    PCF_FILE="${BIT}.v.pcf"
-    QCF_FILE="${BIT}.v.qcf"
-
-    if [ ! -z "{PCF}" ]; then
-        PCF_ARGS="--input-pcf ${PCF}"
-    else
-        PCF_ARGS=""
-    fi
-
-    echo "Running fasm2bels"
-    `which python3` ${FASM2BELS} ${BIT} --phy-db ${VPR_DB} --device-name ${FASM2BELS_DEVICE} --package-name ${PART} --input-type bitstream --output-verilog ${VERILOG_FILE} ${PCF_ARGS} --output-pcf ${PCF_FILE} --output-qcf ${QCF_FILE}
-
-else
-
+# $DEVICE is not ql-eos-s3 or ql-pp3e
+if ! [[ "$DEVICE" =~ ^(ql-eos-s3|ql-pp3e)$ ]]; then
     echo "ERROR: Unsupported device '${DEVICE}' for fasm2bels"
     exit -1
 fi
+
+# Run fasm2bels
+VPR_DB=`readlink -f ${SHARE_DIR_PATH}/arch/${DEVICE}_wlcsp/db_phy.pickle`
+FASM2BELS=`readlink -f ${SHARE_DIR_PATH}/scripts/fasm2bels.py`
+FASM2BELS_DEVICE=${DEVICE/ql-/}
+
+VERILOG_FILE="${OUT_VERILOG:-$BIT.v}"
+PCF_FILE="${OUT_PCF:-$BIT.v.pcf}"
+QCF_FILE="${OUT_QCF:-$BIT.v.qcf}"
+
+if [ ! -z "{PCF}" ]; then
+    PCF_ARGS="--input-pcf ${PCF}"
+else
+    PCF_ARGS=""
+fi
+
+echo "Running fasm2bels"
+`which python3` ${FASM2BELS} ${BIT} --phy-db ${VPR_DB} --device-name ${FASM2BELS_DEVICE} --package-name ${PART} --input-type bitstream --output-verilog ${VERILOG_FILE} ${PCF_ARGS} --output-pcf ${PCF_FILE} --output-qcf ${QCF_FILE}