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f4pga/common_modules/route: use pathlib.rename instead of shutil.move 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-08-15 07:27:27 +02:00
parent 5d919e9dc6
commit 95b4857cd7
1 changed files with 3 additions and 4 deletions
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7
f4pga/common_modules/route.py
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@ -18,20 +18,19 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
from pathlib import Path from pathlib import Path
from shutil import move as sh_mv
from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs, options_dict_to_list, save_vpr_log from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs, options_dict_to_list, save_vpr_log
from f4pga.module import Module, ModuleContext from f4pga.module import Module, ModuleContext
def route_place_file(ctx: ModuleContext): def route_place_file(ctx: ModuleContext):
return str(Path(ctx.takes.eblif).with_suffix('.route')) return Path(ctx.takes.eblif).with_suffix('.route')
class RouteModule(Module): class RouteModule(Module):
def map_io(self, ctx: ModuleContext): def map_io(self, ctx: ModuleContext):
return { return {
'route': route_place_file(ctx) 'route': str(route_place_file(ctx))
} }
def execute(self, ctx: ModuleContext): def execute(self, ctx: ModuleContext):
@ -52,7 +51,7 @@ class RouteModule(Module):
) )
if ctx.is_output_explicit('route'): if ctx.is_output_explicit('route'):
sh_mv(route_place_file(ctx), ctx.outputs.route) route_place_file(ctx).rename(ctx.outputs.route)
yield 'Saving log...' yield 'Saving log...'
save_vpr_log('route.log', build_dir=str(build_dir)) save_vpr_log('route.log', build_dir=str(build_dir))