diff --git a/docs/_static/images/EDA.svg b/docs/_static/images/EDA.svg
index f278a9c..ec4b1fa 100644
--- a/docs/_static/images/EDA.svg
+++ b/docs/_static/images/EDA.svg
@@ -1 +1 @@
-
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+
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diff --git a/docs/_static/images/parts.svg b/docs/_static/images/parts.svg
index 97296de..5d97c92 100644
--- a/docs/_static/images/parts.svg
+++ b/docs/_static/images/parts.svg
@@ -1 +1 @@
-
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+
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diff --git a/docs/how.rst b/docs/how.rst
index c9fc6b6..ab57353 100644
--- a/docs/how.rst
+++ b/docs/how.rst
@@ -1,29 +1,8 @@
How it works
############
-The F4PGA toolchain consists of logic synthesis and implementation tools, as well as chip documentation projects for
-chips of various vendors.
-To prepare a working bitstream for a particular FPGA chip, the toolchain goes through the following stages:
-
-* First, a description of the FPGA chip is created with the information from the relevant bitstream documentation
- project.
- This part is done within the `F4PGA Architecture Definitions `__.
- The project prepares information about the timings and resources available in the chip needed at the implementation
- stage, as well as techmaps for the synthesis tools.
-
-* The second step is logic synthesis.
- It is carried out in the Yosys framework, which expresses the input Verilog file by means of the block and connection
- types available in the chosen chip.
-
-* The next step is implementation.
- Placement and routing tools put individual blocks from the synthesis description in the specific chip locations and
- create paths between them.
- To do that, F4PGA uses either `nextpnr `__ or `Verilog to Routing `__.
-
-* Finally, the design properties are translated into a set of features available in the given FPGA chip.
- These features are saved in the `fasm format `__, which is developed as part of
- F4PGA.
- The fasm file is then translated to bitstream using the information from the bitstream documentation projects.
+To understand how F4PGA works, it is best to start with an overview of the general EDA tooling ecosystem and then
+proceed to see what the F4PGA project consists of.
EDA Tooling Ecosystem
=====================
@@ -65,3 +44,26 @@ collaborating projects targeting different FPGAs - :doc:`Project X-Ray
.. figure:: _static/images/parts.svg
+The F4PGA toolchain consists of logic synthesis and implementation tools, as well as chip documentation projects for
+chips of various vendors.
+To prepare a working bitstream for a particular FPGA chip, the toolchain goes through the following stages:
+
+* First, a description of the FPGA chip is created with the information from the relevant bitstream documentation
+ project.
+ This part is done within the `F4PGA Architecture Definitions `__.
+ The project prepares information about the timings and resources available in the chip needed at the implementation
+ stage, as well as techmaps for the synthesis tools.
+
+* The second step is logic synthesis.
+ It is carried out in the Yosys framework, which expresses the input Verilog file by means of the block and connection
+ types available in the chosen chip.
+
+* The next step is implementation.
+ Placement and routing tools put individual blocks from the synthesis description in the specific chip locations and
+ create paths between them.
+ To do that, F4PGA uses either `nextpnr `__ or `Verilog to Routing `__.
+
+* Finally, the design properties are translated into a set of features available in the given FPGA chip.
+ These features are saved in the `fasm format `__, which is developed as part of
+ F4PGA.
+ The fasm file is then translated to bitstream using the information from the bitstream documentation projects.