docs: add references through sphinxcontrib-bibtex

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>

docs/conf.py

@@ -45,9 +45,13 @@ release = '' # The full version, including alpha/beta/rc tags.
 extensions = [
     'sphinx.ext.extlinks',
     'sphinx.ext.intersphinx',
-    'sphinx_verilog_domain'
+    'sphinx_verilog_domain',
+    'sphinxcontrib.bibtex',
 ]
 
+bibtex_default_style = 'plain'
+bibtex_bibfiles = ['refs.bib']
+
 numfig = True
 
 templates_path = ['_templates']

docs/index.rst

@@ -46,3 +46,4 @@ The project aims to design tools that are highly extendable and multiplatform.
   :caption: Appendix
 
   glossary
+  references

docs/references.rst

@@ -0,0 +1,8 @@
+.. _References:
+
+References
+##########
+
+.. bibliography::
+  :notcited:
+  :labelprefix: R

docs/refs.bib

@@ -0,0 +1,232 @@
+@Online{verilator,
+  author = {Snyder, Wilson and {contributors}},
+  title = {{Verilator, FOSS tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC}},
+  url = {https://www.veripool.org/verilator/},
+  year = {2003},
+}
+
+@InProceedings{wolf13,
+  author = {Wolf, Clifford and Glaser, Johann},
+  title = {{A Free Verilog Synthesis Suite}},
+  booktitle = {Proceedings of Austrochip 2013},
+  year = {2013},
+  url = {https://yosyshq.net/yosys/}
+}
+
+@Online{gh:yosys,
+  author = {Wolf, Claire and {contributors}},
+  title  = {{Yosys Open SYnthesis Suite}},
+  url    = {https://github.com/YosysHQ/yosys},
+}
+
+@Online{gh:symbiyosys,
+  author = {Wolf, Claire and {contributors}},
+  title  = {{SymbiYosys: front-end for Yosys-based formal verification flows}},
+  url    = {https://github.com/YosysHQ/SymbiYosys},
+}
+
+@Online{gh:nextpnr,
+  author = {gatecat and {contributors}},
+  title  = {{nextpnr: portable FPGA place and route tool}},
+  url    = {https://github.com/YosysHQ/nextpnr},
+}
+
+@Online{gh:gtkwave,
+  author = {Bybell, Tony and {contributors}},
+  title  = {{GTKWave: a is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX}},
+  url    = {https://github.com/gtkwave/gtkwave},
+  year   = {1998},
+}
+
+@Online{gh:ghdl,
+  author = {Gingold, Tristan and {contributors}},
+  title  = {{GHDL: open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL}},
+  url    = {https://github.com/ghdl/ghdl},
+  month  = {Sep},
+  year   = {2003},
+}
+
+@Online{gh:ghdl-yosys-plugin,
+  author = {Gingold, Tristan and {contributors}},
+  title  = {{ghdl-yosys-plugin: VHDL synthesis (based on ghdl and yosys)}},
+  url    = {https://github.com/ghdl/ghdl-yosys-plugin},
+  year   = {2017},
+}
+
+@Online{sphinx,
+  author = {Brandl, Georg and KOMIYA, Takeshi and {contributors}},
+  year = {2007},
+  title = {{Sphinx, Python Documentation Generator}},
+  url = {https://www.sphinx-doc.org},
+}
+
+@Online{verible,
+  author = {Fang, David and Zeller, Henner and {contributors}},
+  year = {2019},
+  title = {{Verible, a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter}},
+  url = {https://chipsalliance.github.io/verible/},
+}
+
+@Online{surelog,
+  author = {Dargelas, Alain and Zeller, Henner and {contributors}},
+  year = {2019},
+  title = {{Surelog, SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler}},
+  url = {https://github.com/alainmarcel/Surelog/},
+}
+
+@inproceedings{dargelas20,
+  title = {{Universal Hardware Data Model}},
+  author = {Dargelas, Alain and Zeller, Henner},
+  booktitle = {Workshop on Open-Source EDA Technology 2020 (WOSET)},
+  year = {2020},
+  month = {10},
+  url = {https://woset-workshop.github.io/PDFs/2020/a10.pdf}
+}
+
+@Online{iverilog,
+  author={Williams, Stephen and {contributors}},
+  title={{Icarus Verilog, a Verilog simulation and synthesis tool}},
+  url={http://iverilog.icarus.com/}
+}
+
+@InProceedings{ansell20,
+  author = {Ansell, Tim and Saligane, Mehdi},
+  booktitle = {2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)},
+  title = {{The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts : Invited Paper}},
+  year = {2020},
+  pages = {1-8},
+  url = {https://dl.acm.org/doi/abs/10.1145/3400302.3415736}
+}
+
+@Online{gcc,
+  author = {Stallman, Richard and {contributors}},
+  year = {1987},
+  title = {{GCC, the GNU Compiler Collection}},
+  url = {http://gcc.gnu.org/},
+  month = {May},
+}
+
+@Online{gdb,
+  author = {Stallman, Richard and {GNU Project}},
+  year = {1986},
+  title = {{GDB: The GNU Project Debugger}},
+  url = {https://www.gnu.org/software/gdb/},
+}
+
+@Online{llvm,
+  author = {
+    Adve, Vikram and
+    Lattner, Chris and
+    {LLVM Developer Group}
+  },
+  title = {{LLVM Project, a collection of modular and reusable compiler and toolchain technologies}},
+  url = {https://www.llvm.org/},
+  year = {2003},
+}
+
+@Online{gh:wavedrom,
+  author = {Chapyzhenka, Aliaksei and {contributors}},
+  title  = {{Wavedrom, digital timing diagram rendering engine}},
+  url    = {https://github.com/wavedrom/wavedrom},
+  year   = {2014},
+}
+
+@Online{symbolator,
+  author = {Thibedeau, Kevin},
+  title = {{Symbolator, a component diagramming tool for VHDL and Verilog}},
+  url = {https://kevinpt.github.io/symbolator},
+}
+
+@InProceedings{rovinski20,
+  author={
+    Rovinski, Austin and
+    Ajayi, Tutu and
+    Kim, Minsoo and
+    Wang, Guanru and
+    Saligane, Mehdi
+  },
+  booktitle={2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)},
+  title={{Bridging Academic Open-Source EDA to Real-World Usability}},
+  year={2020},
+  pages={1-7},
+  url={https://dl.acm.org/doi/10.1145/3400302.3415734}
+}
+
+@Article{murray20micro,
+  author={
+    Murray, Kevin E. and
+    Elgammal, Mohamed A. and
+    Betz, Vaughn and
+    Ansell, Tim and
+    Rothman, Keith and
+    Comodi, Alessandro
+  },
+  journal={IEEE Micro},
+  title={{SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs}},
+  year={2020},
+  volume={40},
+  number={4},
+  pages={49-57},
+  doi={10.1109/MM.2020.2998435}
+}
+
+@Article{murray20acm,
+  author = {
+    Murray, Kevin E. and
+    Petelin, Oleg and
+    Zhong, Sheng and
+    Wang, Jia Min and
+    Eldafrawy, Mohamed and
+    Legault, Jean-Philippe and
+    Sha, Eugene and
+    Graham, Aaron G. and
+    Wu, Jean and
+    Walker, Matthew J. P. and
+    Zeng, Hanqing and
+    Patros, Panagiotis and
+    Luu, Jason and
+    Kent, Kenneth B. and
+    Betz, Vaughn
+  },
+  title = {{VTR 8: High-Performance CAD and Customizable FPGA Architecture Modelling}},
+  year = {2020},
+  issue_date = {June 2020},
+  publisher = {Association for Computing Machinery},
+  address = {New York, NY, USA},
+  volume = {13},
+  number = {2},
+  issn = {1936-7406},
+  url = {https://doi.org/10.1145/3388617},
+  doi = {10.1145/3388617},
+  abstract = {Developing Field-programmable Gate Array (FPGA) architectures is challenging due to
+the competing requirements of various application domains and changing manufacturing
+process technology. This is compounded by the difficulty of fairly evaluating FPGA
+architectural choices, which requires sophisticated high-quality Computer Aided Design
+(CAD) tools to target each potential architecture. This article describes version
+8.0 of the open source Verilog to Routing (VTR) project, which provides such a design
+flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing
+VTR to target and model many details of both commercial and proposed FPGA architectures.
+The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It
+is therefore important, for both CAD algorithm comparisons and the validity of architectural
+conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly
+improves optimization quality (reductions of 15% minimum routable channel width, 41%
+wirelength, and 12% critical path delay), run-time (5.3\texttimes{} faster) and memory footprint
+(3.3\texttimes{} lower). Finally, we demonstrate VTR is run-time and memory footprint efficient,
+while producing circuit implementations of reasonable quality compared to highly-tuned
+architecture-specific industrial tools—showing that architecture generality, good
+implementation quality, and run-time efficiency are not mutually exclusive goals.},
+  journal = {ACM Trans. Reconfigurable Technol. Syst.},
+  month = may,
+  articleno = {9},
+  numpages = {55},
+  keywords = {electronic design automation (EDA), Computer aided design (CAD), versatile place and route (VPR), verilog to routing (VTR), routing, placement, packing, field programmable gate array (FPGA)}
+}
+
+@InProceedings{kahng20,
+  author={Kahng, Andrew B.},
+  booktitle={2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)},
+  title={{Open-Source EDA: If We Build It, Who Will Come?}},
+  year={2020},
+  pages={1-6},
+  doi={10.1109/VLSI-SOC46417.2020.9344073}
+}

docs/requirements.txt

@@ -1,4 +1,5 @@
-Sphinx==3.0.4
+sphinx
+sphinxcontrib-bibtex
 http://github.com/SymbiFlow/sphinx_symbiflow_theme/archive/chips.zip#sphinx-symbiflow-theme
 http://github.com/SymbiFlow/sphinx-verilog-domain/archive/master.zip#sphinx-verilog-domain
 tabulate