docs: content moved from the website

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>

docs/community.rst

@@ -1,4 +1,70 @@
 Community
 #########
 
-*TBC*
+`FOSS Flows For FPGA (F4PGA) <https://f4pga.org>`__ project is a `Workgroup <https://chipsalliance.org/workgroups/>`__
+under the `CHIPS Alliance <https://chipsalliance.com/>`__.
+The F4PGA Workgroup consists of members from different backgrounds, including FPGA vendors
+(`Xilinx <https://www.xilinx.com/>`__
+and `QuickLogic <https://www.quicklogic.com/>`__),
+industrial users
+(`Google <https://www.google.com/>`__
+and `Antmicro <https://antmicro.com/>`__)
+and academia
+(`University of Toronto <https://www.utoronto.ca/>`__),
+who collaborate to build a more open source and software-driven FPGA ecosystem (IP, tools and workflows) to drive the
+adoption of FPGAs in existing and new use cases, and eliminate barriers of entry.
+
+Communication
+=============
+
+* `Twitter [@f4pga] <https://twitter.com/f4pga>`__
+
+* `Slack [chipsalliance.slack.com] <https://chipsalliance.slack.com/>`__
+
+  .. TIP::
+    To register to CHIPS Alliance Slack workspace, use the following `Slack Invite <https://slack-invite.chipsalliance.org/>`__.
+
+* `IRC [irc.libera.chat/#F4PGA] <https://kiwiirc.com/nextclient/#irc://irc.libera.chat/#F4PGA>`__
+
+* `Mailing list [lists.chipsalliance.org/g/f4pga-wg] <https://lists.chipsalliance.org/g/f4pga-wg>`__
+
+Souces
+======
+
+* `github.com/chipsalliance <https://github.com/chipsalliance/?q=f4pga>`__
+
+* `github.com/F4PGA <https://github.com/F4PGA>`__
+
+.. _Contributing:
+
+Contributing
+============
+
+Are you interested in helping this project move forward?
+F4PGA is a collaborative project and we welcome your contributions.
+The code is available on GitHub, while the HTML documentation is available on Read The Docs.
+There are multiple areas and technologies we need help with - reach out to us, we're sure we will find something for you.
+
+* Do you know **Python**?
+  Almost all scripts are written in Python!
+
+* Do you know **C++**?
+  VPR & nextpnr & libraries written in C++!
+
+* Do you know **TCL**?
+  All the EDA tools use TCL!
+
+* Do you know **(System) Verilog**, **VHDL**, **Chisel**, **Migen** and/or **Amaranth**?
+  Simulation and models are written in Hardware Description Languages (HDLs)!
+
+* Do you know **XML**?
+  Most file formats are XML!
+
+* Do you know English?
+  Documentation is written in English!
+
+* Do you know **Docker** and/or **Podman**?
+  Help make it easier to set up F4PGA!
+
+* Do you have time?
+  We will find you a task!

docs/getting-started.rst

@@ -3,4 +3,4 @@ Getting started
 
 *TBC*
 
-* For developers ➚ <https://f4pga.readthedocs.io/projects/arch-defs/en/latest/getting-started.html>
+* `For developers ➚ <https://f4pga.readthedocs.io/projects/arch-defs/en/latest/getting-started.html>`__

docs/how.rst

@@ -1,6 +1,30 @@
 How it works
 ############
 
+The F4PGA toolchain consists of logic synthesis and implementation tools, as well as chip documentation projects for
+chips of various vendors.
+To prepare a working bitstream for a particular FPGA chip, the toolchain goes through the following stages:
+
+* First, a description of the FPGA chip is created with the information from the relevant bitstream documentation
+  project.
+  This part is done within the `F4PGA Architecture Definitions <https://github.com/chipsalliance/f4pga-arch-defs>`__.
+  The project prepares information about the timings and resources available in the chip needed at the implementation
+  stage, as well as techmaps for the synthesis tools.
+
+* The second step is logic synthesis.
+  It is carried out in the Yosys framework, which expresses the input Verilog file by means of the block and connection
+  types available in the chosen chip.
+
+* The next step is implementation.
+  Placement and routing tools put individual blocks from the synthesis description in the specific chip locations and
+  create paths between them.
+  To do that, F4PGA uses either `nextpnr <https://github.com/YosysHQ/nextpnr>`__ or `Verilog to Routing <https://github.com/verilog-to-routing/vtr-verilog-to-routing>`__.
+
+* Finally, the design properties are translated into a set of features available in the given FPGA chip.
+  These features are saved in the `fasm format <https://github.com/chipsalliance/fasm>`__, which is developed as part of
+  F4PGA.
+  The fasm file is then translated to bitstream using the information from the bitstream documentation projects.
+
 EDA Tooling Ecosystem
 =====================