From c85a77d15e4140b25ed11f44cff2cc9506910312 Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Tue, 5 Apr 2022 13:32:19 +0200 Subject: [PATCH] docs: s/http:/https:/ Signed-off-by: Unai Martinez-Corral --- LICENSE | 4 ++-- docs/flows/f4pga.rst | 6 +++--- docs/how.rst | 4 ++-- docs/refs.bib | 2 +- docs/requirements.txt | 4 ++-- docs/status.rst | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/LICENSE b/LICENSE index d645695..62589ed 100644 --- a/LICENSE +++ b/LICENSE @@ -1,7 +1,7 @@ Apache License Version 2.0, January 2004 - http://www.apache.org/licenses/ + https://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION @@ -193,7 +193,7 @@ you may not use this file except in compliance with the License. You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 + https://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, diff --git a/docs/flows/f4pga.rst b/docs/flows/f4pga.rst index 13fa879..20073d2 100644 --- a/docs/flows/f4pga.rst +++ b/docs/flows/f4pga.rst @@ -134,7 +134,7 @@ Technology mapping in F4PGA toolchain .. _Xilinx 7 Series FPGAs Clocking Resources User Guide: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#page=38 .. _VTR FPGA Architecture Description: https://docs.verilogtorouting.org/en/latest/arch/ -.. _techmap section in the Yosys Manual: http://yosyshq.net/yosys/files/yosys_manual.pdf#page=153 +.. _techmap section in the Yosys Manual: https://yosyshq.net/yosys/files/yosys_manual.pdf#page=153 It is important to understand the connection between the synthesis and implementation tools used in the F4PGA toolchain. As mentioned before, @@ -190,7 +190,7 @@ Below you can see the pb_type XML for ``BUFGCTRL_VPR`` primitive: .. code-block:: xml - + @@ -406,7 +406,7 @@ More information Additional information about Yosys can be found on the `Yosys Project Website `_ , or in `Yosys Manual -`_. You can also compile +`_. You can also compile one of the tests described in Getting Started section and watch the log file to understand which operations are performed by Yosys. diff --git a/docs/how.rst b/docs/how.rst index c5da1ec..da5f8b0 100644 --- a/docs/how.rst +++ b/docs/how.rst @@ -33,7 +33,7 @@ Thus, F4PGA serves as an umbrella project for several activities. The central resources are the so-called FPGA "architecture definitions" (i.e. documentation of how specific FPGAs work internally) and the "interchange schema" (for logical and physical netlists). Those definitions serve as input to frontend and backend tools, such as -`Yosys ➚ `__, +`Yosys ➚ `__, :gh:`nextpnr ➚ ` and `Verilog to Routing ➚ `_. They are created within separate collaborating projects targeting different FPGAs: @@ -55,7 +55,7 @@ To prepare a working bitstream for a particular FPGA chip, the toolchain goes th This stage is typically pre-built and installed as assets. However, developers contributing to the bitstream documentation might build it. -* Then, logic synthesis is carried out in the `Yosys ➚ `__ framework, which expresses the +* Then, logic synthesis is carried out in the `Yosys ➚ `__ framework, which expresses the user-provided hardware description by means of the block and connection types available in the chosen chip. * The next step is implementation. diff --git a/docs/refs.bib b/docs/refs.bib index 1605278..3494673 100644 --- a/docs/refs.bib +++ b/docs/refs.bib @@ -102,7 +102,7 @@ author = {Stallman, Richard and {contributors}}, year = {1987}, title = {{GCC, the GNU Compiler Collection}}, - url = {http://gcc.gnu.org/}, + url = {https://gcc.gnu.org/}, month = {May}, } diff --git a/docs/requirements.txt b/docs/requirements.txt index 9999645..a7505cb 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,5 +1,5 @@ sphinx>=4.5.0 sphinxcontrib-bibtex -http://github.com/SymbiFlow/sphinx_symbiflow_theme/archive/chips.zip#sphinx-symbiflow-theme -http://github.com/SymbiFlow/sphinx-verilog-domain/archive/master.zip#sphinx-verilog-domain +https://github.com/SymbiFlow/sphinx_symbiflow_theme/archive/chips.zip#sphinx-symbiflow-theme +https://github.com/SymbiFlow/sphinx-verilog-domain/archive/master.zip#sphinx-verilog-domain tabulate diff --git a/docs/status.rst b/docs/status.rst index 6d8fae8..378a71b 100644 --- a/docs/status.rst +++ b/docs/status.rst @@ -5,7 +5,7 @@ Supported Architectures * `Xilinx 7-Series `__: the most popular Xilinx FPGA family. -* `Lattice ice40 `__: +* `Lattice ice40 `__: world's smallest FPGAs for mobile devices. * `Lattice ecp5 `__: