From cb7f555511c44ff5f61d32a3f99caebb027f01a1 Mon Sep 17 00:00:00 2001
From: Unai Martinez-Corral <umartinezcorral@antmicro.com>
Date: Thu, 11 Aug 2022 15:06:43 +0200
Subject: [PATCH] f4pga/wrappers/sh/quicklogic/ql: remove redundant condition

Co-Authored-By: Pawel Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
---
 f4pga/wrappers/sh/quicklogic/ql.f4pga.sh | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh b/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh
index e7c8d30..f30f915 100755
--- a/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh
+++ b/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh
@@ -147,17 +147,15 @@ echo "$VERILOG_FILES" >${SOURCE}/v_list
 
 ## Validate the verlog source files
 if [ ${#VERILOG_FILES[@]} -eq 0 ]; then
-  if [[ $1 != "-h" || $1 != "--help" ]];then
-    echo "Please provide at least one Verilog file"
-    exit 1
-  fi
-else
-  echo "verilog files: $VERILOG_FILES"
-  echo $VERILOG_FILES >${SOURCE}/v_list
-  sed '/^$/d' $SOURCE/v_list > $SOURCE/f_list_temp
-  VERILOG_FILES=`cat $SOURCE/f_list_temp`
+  echo "Please provide at least one Verilog file"
+  exit 1
 fi
 
+echo "verilog files: $VERILOG_FILES"
+echo $VERILOG_FILES >${SOURCE}/v_list
+sed '/^$/d' $SOURCE/v_list > $SOURCE/f_list_temp
+VERILOG_FILES=`cat $SOURCE/f_list_temp`
+
 
 if [[ $1 == "-compile" || $1 == "-post_verilog" ]]; then
   if [ -z "$DEVICE" ]; then