f4pga/wrappers/sh/quicklogic/ql: remove redundant condition
Co-Authored-By: Pawel Czarnecki <pczarnecki@antmicro.com> Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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@ -147,17 +147,15 @@ echo "$VERILOG_FILES" >${SOURCE}/v_list
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## Validate the verlog source files
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## Validate the verlog source files
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if [ ${#VERILOG_FILES[@]} -eq 0 ]; then
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if [ ${#VERILOG_FILES[@]} -eq 0 ]; then
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if [[ $1 != "-h" || $1 != "--help" ]];then
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echo "Please provide at least one Verilog file"
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echo "Please provide at least one Verilog file"
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exit 1
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exit 1
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fi
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else
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echo "verilog files: $VERILOG_FILES"
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echo $VERILOG_FILES >${SOURCE}/v_list
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sed '/^$/d' $SOURCE/v_list > $SOURCE/f_list_temp
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VERILOG_FILES=`cat $SOURCE/f_list_temp`
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fi
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fi
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echo "verilog files: $VERILOG_FILES"
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echo $VERILOG_FILES >${SOURCE}/v_list
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sed '/^$/d' $SOURCE/v_list > $SOURCE/f_list_temp
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VERILOG_FILES=`cat $SOURCE/f_list_temp`
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if [[ $1 == "-compile" || $1 == "-post_verilog" ]]; then
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if [[ $1 == "-compile" || $1 == "-post_verilog" ]]; then
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if [ -z "$DEVICE" ]; then
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if [ -z "$DEVICE" ]; then
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