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f4pga/wrappers/sh/quicklogic/ql: remove redundant condition 

Co-Authored-By: Pawel Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-08-11 15:06:43 +02:00
parent 453fffea4e
commit cb7f555511
1 changed files with 7 additions and 9 deletions
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16
f4pga/wrappers/sh/quicklogic/ql.f4pga.sh
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@ -147,17 +147,15 @@ echo "$VERILOG_FILES" >${SOURCE}/v_list
## Validate the verlog source files
if [ ${#VERILOG_FILES[@]} -eq 0 ]; then
if [[ $1 != "-h" || $1 != "--help" ]];then
echo "Please provide at least one Verilog file"
exit 1
fi
else
echo "verilog files: $VERILOG_FILES"
echo $VERILOG_FILES >${SOURCE}/v_list
sed '/^$/d' $SOURCE/v_list > $SOURCE/f_list_temp
VERILOG_FILES=`cat $SOURCE/f_list_temp`
echo "Please provide at least one Verilog file"
exit 1
fi
echo "verilog files: $VERILOG_FILES"
echo $VERILOG_FILES >${SOURCE}/v_list
sed '/^$/d' $SOURCE/v_list > $SOURCE/f_list_temp
VERILOG_FILES=`cat $SOURCE/f_list_temp`
if [[ $1 == "-compile" || $1 == "-post_verilog" ]]; then
if [ -z "$DEVICE" ]; then