docs/conf: add ExtLinks
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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docs/conf.py
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docs/conf.py
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@ -43,6 +43,7 @@ version = ''
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release = '' # The full version, including alpha/beta/rc tags.
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release = '' # The full version, including alpha/beta/rc tags.
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extensions = [
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extensions = [
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'sphinx.ext.extlinks',
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'sphinx.ext.intersphinx',
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'sphinx.ext.intersphinx',
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'sphinx_verilog_domain'
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'sphinx_verilog_domain'
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]
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]
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@ -140,3 +141,14 @@ intersphinx_mapping = {
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"prjxray": ("https://f4pga.readthedocs.io/projects/prjxray/en/latest/", None),
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"prjxray": ("https://f4pga.readthedocs.io/projects/prjxray/en/latest/", None),
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"vtr": ("https://docs.verilogtorouting.org/en/latest/", None),
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"vtr": ("https://docs.verilogtorouting.org/en/latest/", None),
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}
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}
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# -- Sphinx.Ext.ExtLinks -----------------------------------------------------------------------------------------------
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extlinks = {
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'wikipedia': ('https://en.wikipedia.org/wiki/%s', 'wikipedia:'),
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'gh': ('https://github.com/%s', 'gh:'),
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'ghsharp': ('https://github.com/chipsalliance/f4pga/issues/%s', '#'),
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'ghissue': ('https://github.com/chipsalliance/f4pga/issues/%s', 'issue #'),
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'ghpull': ('https://github.com/chipsalliance/f4pga/pull/%s', 'pull request #'),
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'ghsrc': ('https://github.com/chipsalliance/f4pga/blob/master/%s', '')
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}
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