From 46c892f4f6590c623ee2d0ea7e726f4dbb6eee96 Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Tue, 21 Jun 2022 13:04:13 +0200 Subject: [PATCH] docs/_static/images: SVGs with embedded fonts Signed-off-by: Unai Martinez-Corral --- docs/_static/images/EDA.svg | 710 +------ docs/_static/images/parts.svg | 3253 +-------------------------------- 2 files changed, 6 insertions(+), 3957 deletions(-) diff --git a/docs/_static/images/EDA.svg b/docs/_static/images/EDA.svg index 371174e..28c7d45 100644 --- a/docs/_static/images/EDA.svg +++ b/docs/_static/images/EDA.svg @@ -1,707 +1,3 @@ - - - - - - - - - - - - - - Hardware - -Description Languages - - - - - - - - - - - - - - - - - - - - - - - - - Synthesis tools - - - - - - - - - - - - - - - - - - - - - - - - - - - - FPGA tools - - - - - - - - - - - - - - - - - - - - - - - ASIC tools - - - - - - - - - - - - - - - - - - - - - - - Verification, Testing and Simulation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Description - - - - - - - - - - - - - - - - - - - - - - - - - Frontend - - - - - - - - - - - - - - - - - - - - - - Backend - - - - - - - - - - - - - - - - - - - - - - Viewer does not support full SVG 1.1 - - - + + +
Hardware
Description Languages
Hardware...
Synthesis tools
Synthesis to...
FPGA tools
FPGA tools
ASIC tools
ASIC tools
Verification, Testing and Simulation
Verification, Testing and Simulation
Description
Description
Frontend
Frontend
Backend
Backend
Text is not SVG - cannot display
\ No newline at end of file diff --git a/docs/_static/images/parts.svg b/docs/_static/images/parts.svg index 10d0c36..bad3d35 100644 --- a/docs/_static/images/parts.svg +++ b/docs/_static/images/parts.svg @@ -1,3250 +1,3 @@ - - - - - - - - - - - - - - - - - - - - - - - Yosys            -ABC              - - - - YosysABC - - - - - - - - - Verification, Testing and Simulation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Description - - - - - - - - - - - - - - - - - - - - - - - - - Frontend - - - - - - - - - - - - - - - - - - - - - - Backend - - - - - - - - - - - - - - - - - - - - - GHDL - - - - - - - - - - - - - - - - - - Surelog -UHDM - - - - - - - - - - - - - - - - - - - - - - - - - VHDL - - - - - - - - - - - - - - - - - - System Verilog - - - - - - - - - - - - - - - - - - - - - - - - - - - Verilog - - - - - - - - - - - - - - - - - - - - - - - - - - - Project IceStorm - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Project X-Ray - - - - - - - - - - - - - - - - - - - - - - - - - - Project U-Ray - - - - - - - - - - - - - - - - - - - - - - - - - - Project Trellis - - - - - - - - - - - - - - - - - - - - - - - - - - - - QuickLogic DB - - - - - - - - - - - - - - - - - - - - - - - - - - Project Apicula - - - - - - - - - - - - - - - - - - - - - - - - - - - - Project Oxide - - - - - - - - - - - - - - - - - - - - - - - - - - Verilog to Routing - - - - Verilog toRouting - - - - - - - - - nextpnr - - - - - - - - - - - - - - - - - - - - - Amaranth - - - - - - - - - - - - - - - - - - - - - - - - Architecture definitions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Clash - - - - - - - - - - - - - - - - - - - SpinalHDL - - - - - - - - - - - - - - - - - - - - - - - Chisel - - - - - - - - - - - - - - - - - - - - BlueSpec - - - - - - - - - - - - - - - - - - - - - - migen/Litex - - - - - - - - - - - - - - - - - - - - - - - - - Silice - - - - - - - - - - - - - - - - - - - - Synthesijer - - - - - - - - - - - - - - - - - - - - - - - - - HLS - - - - - - - - - - - - - - - - - PipelineC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Interchange logical netlist - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - FASM - - - - - - - - - - - - - - - - - - icepack - - - - - - - - - - - - - - - - - - - - - ecppack - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RapidWright -(Vivado) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Interchange physical netlist - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Viewer does not support full SVG 1.1 - - - + + +
Yosys           
ABC             
Yosys...
Verification, Testing and Simulation
Verification, Testing and Simulation
Description
Description
Frontend
Frontend
Backend
Backend
GHDL
GHDL
Surelog
UHDM
Surelog...
VHDL
VHDL
System Verilog
System Ver...
Verilog
Verilog
Project IceStorm
Project IceS...
Project X-Ray
Project X-Ray
Project U-Ray
Project U-Ray
Project Trellis
Project Trel...
QuickLogic DB
QuickLogic DB
Project Apicula
Project Apic...
Project Oxide
Project Oxide
Verilog to Routing
Verilog to...
nextpnr
nextpnr
Amaranth
Amaranth
Architecture definitions
Architecture definitions
Clash
Clash
SpinalHDL
SpinalHDL
Chisel
Chisel
BlueSpec
BlueSpec
migen/Litex
migen/Litex
Silice
Silice
Synthesijer
Synthesijer
HLS
HLS
PipelineC
PipelineC
Interchange logical netlist
Interchange logical netl...
FASM
FASM
icepack
icepack
ecppack
ecppack
RapidWright
(Vivado)
RapidWrig...
Interchange physical netlist
Interchange physical netli...
Text is not SVG - cannot display
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