Rewrite the description of RTL generation to make more sense
I was having trouble understanding the language here. I *think* this is what it meant to mean.
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@ -22,15 +22,15 @@ Look Up Tables implement only the functionality of logic gates.
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Due to that, the synthesis process has to convert the complicated
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Due to that, the synthesis process has to convert the complicated
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Behavioral model to a simpler description.
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Behavioral model to a simpler description.
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Firstly, the design is described in terms of registers and logical operations.
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First, the design is described in terms of registers and logical operations.
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This is the so-called *Register-Transfer Level* (*RTL*).
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This is the so-called *Register-Transfer Level* (*RTL*).
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Secondly, in order to simplify the design even more, some complex logic is
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Second, in order to simplify the design even more, some complex logic is
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rewritten in the way that the final result contain only logic gates
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rewritten in such a way that the final result contains only logic gates
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and registers. This model is on *Logical Gate level* of abstraction.
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and registers. This model is on the *Logical Gate level* of abstraction.
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The process of simplification is quite complicated, because of that it often
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This process of simplification is quite complicated, so it is often necessary
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demands additional simulations between mentioned steps to prove that the input
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to have additional simulations between the mentioned steps, to prove that the
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design is equivalent to its simplified form.
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input design is equivalent to its simplified form.
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Technology mapping
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Technology mapping
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==================
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==================
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