diff --git a/source/_static/favicon.svg b/source/_static/favicon.svg
new file mode 100644
index 0000000..5535f19
--- /dev/null
+++ b/source/_static/favicon.svg
@@ -0,0 +1 @@
+
\ No newline at end of file
diff --git a/source/images/EDA.svg b/source/_static/images/EDA.svg
similarity index 100%
rename from source/images/EDA.svg
rename to source/_static/images/EDA.svg
diff --git a/source/images/parts.svg b/source/_static/images/parts.svg
similarity index 100%
rename from source/images/parts.svg
rename to source/_static/images/parts.svg
diff --git a/source/images/toolchain-flow.svg b/source/_static/images/toolchain-flow.svg
similarity index 100%
rename from source/images/toolchain-flow.svg
rename to source/_static/images/toolchain-flow.svg
diff --git a/source/_static/logo.svg b/source/_static/logo.svg
new file mode 100644
index 0000000..29b511d
--- /dev/null
+++ b/source/_static/logo.svg
@@ -0,0 +1,66 @@
+
+
diff --git a/source/conf.py b/source/conf.py
index 7035546..9bee510 100644
--- a/source/conf.py
+++ b/source/conf.py
@@ -4,6 +4,7 @@
# https://www.sphinx-doc.org/en/master/usage/configuration.html
import sys, os
+from pathlib import Path
#sys.path.insert(0, os.path.abspath('.'))
@@ -60,6 +61,11 @@ html_theme_options = {
'color_accent': 'blue',
}
+html_static_path = ['_static']
+
+html_logo = str(Path(html_static_path[0]) / 'logo.svg')
+html_favicon = str(Path(html_static_path[0]) / 'favicon.svg')
+
# -- Options for LaTeX output --------------------------------------------------
latex_documents = [
diff --git a/source/introduction.rst b/source/introduction.rst
index e8fe353..32d5ca3 100644
--- a/source/introduction.rst
+++ b/source/introduction.rst
@@ -25,7 +25,7 @@ all the necessary components for an end-to-end flow.
This pertains both to ASIC and FPGA workflows, although SymbiFlow focuses
on the latter (some parts of SymbiFlow will also be useful in the former).
-.. figure:: images/EDA.svg
+.. figure:: _static/images/EDA.svg
Project structure
-----------------
@@ -48,7 +48,7 @@ collaborating projects targeting different FPGAs - :doc:`Project X-Ray
`_ for Lattice iCE40 and :doc:`Project Trellis
` for Lattice ECP5 FPGAs.
-.. figure:: images/parts.svg
+.. figure:: _static/images/parts.svg
Current status of bitstream documentation
-----------------------------------------
diff --git a/source/toolchain-desc/design-flow.rst b/source/toolchain-desc/design-flow.rst
index d17f337..4bc3efb 100644
--- a/source/toolchain-desc/design-flow.rst
+++ b/source/toolchain-desc/design-flow.rst
@@ -15,7 +15,7 @@ SymbiFlow uses different programs to create the bitstream and is
responsible for their proper integration. The procedure of converting
Verilog file into the bitstream is described in the next sections.
-.. figure:: ../images/toolchain-flow.svg
+.. figure:: ../_static/images/toolchain-flow.svg
:align: center
Symbiflow Toolchain design flow