From fbf7a4d131ebd0ddd50fafe6812c88475137ad01 Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Thu, 21 Apr 2022 13:25:25 +0200 Subject: [PATCH] f4pga: use envvar F4PGA_ENV_BIN and F4PGA_ENV_SHARE Signed-off-by: Unai Martinez-Corral --- .github/workflows/Pipeline.yml | 4 ++-- f4pga/wrappers/sh/quicklogic/analysis.f4pga.sh | 4 ++-- f4pga/wrappers/sh/quicklogic/generate_bitstream.f4pga.sh | 2 +- f4pga/wrappers/sh/quicklogic/generate_constraints.f4pga.sh | 4 ++-- f4pga/wrappers/sh/quicklogic/generate_libfile.f4pga.sh | 4 ++-- f4pga/wrappers/sh/quicklogic/pack.f4pga.sh | 2 +- f4pga/wrappers/sh/quicklogic/place.f4pga.sh | 2 +- f4pga/wrappers/sh/quicklogic/ql.f4pga.sh | 4 ++-- f4pga/wrappers/sh/quicklogic/repack.f4pga.sh | 4 ++-- f4pga/wrappers/sh/quicklogic/route.f4pga.sh | 2 +- f4pga/wrappers/sh/quicklogic/synth.f4pga.sh | 4 ++-- f4pga/wrappers/sh/quicklogic/write_fasm.f4pga.sh | 2 +- f4pga/wrappers/sh/xc7/generate_constraints.f4pga.sh | 2 +- f4pga/wrappers/sh/xc7/synth.f4pga.sh | 2 +- f4pga/wrappers/sh/xc7/vpr_common.f4pga.sh | 2 +- 15 files changed, 22 insertions(+), 22 deletions(-) diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml index 69403a4..d6985a2 100644 --- a/.github/workflows/Pipeline.yml +++ b/.github/workflows/Pipeline.yml @@ -95,8 +95,8 @@ jobs: run: | . ./.github/scripts/activate.sh - f4pga-env bin - f4pga-env share + echo "F4PGA_ENV_BIN=$(f4pga-env bin)" >> "$GITHUB_ENV" + echo "F4PGA_ENV_SHARE=$(f4pga-env share)" >> "$GITHUB_ENV" - name: '🚧 Test make example' run: | diff --git a/f4pga/wrappers/sh/quicklogic/analysis.f4pga.sh b/f4pga/wrappers/sh/quicklogic/analysis.f4pga.sh index 90ebb2a..78ed5ba 100755 --- a/f4pga/wrappers/sh/quicklogic/analysis.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/analysis.f4pga.sh @@ -19,7 +19,7 @@ set -e if [ -z $VPRPATH ]; then - export VPRPATH=$(f4pga-env bin) + export VPRPATH="$F4PGA_ENV_BIN" export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH} fi @@ -32,7 +32,7 @@ run_vpr --analysis --gen_post_synthesis_netlist on --verify_file_digests off mv vpr_stdout.log analysis.log -python3 $(f4pga-env bin)/python/vpr_fixup_post_synth.py \ +python3 "$F4PGA_ENV_BIN"/python/vpr_fixup_post_synth.py \ --vlog-in ${TOP}_post_synthesis.v \ --vlog-out ${TOP}_post_synthesis.v \ --sdf-in ${TOP}_post_synthesis.sdf \ diff --git a/f4pga/wrappers/sh/quicklogic/generate_bitstream.f4pga.sh b/f4pga/wrappers/sh/quicklogic/generate_bitstream.f4pga.sh index 165e8cf..a899be9 100755 --- a/f4pga/wrappers/sh/quicklogic/generate_bitstream.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/generate_bitstream.f4pga.sh @@ -54,6 +54,6 @@ if [ -z $BIT ]; then exit 1 fi -DB_ROOT=$(f4pga-env share)/fasm_database/${DEVICE} +DB_ROOT="$F4PGA_ENV_SHARE"/fasm_database/${DEVICE} `which qlf_fasm` --db-root ${DB_ROOT} --format ${BIT_FORMAT} --assemble $FASM $BIT diff --git a/f4pga/wrappers/sh/quicklogic/generate_constraints.f4pga.sh b/f4pga/wrappers/sh/quicklogic/generate_constraints.f4pga.sh index eb5fabb..777acf7 100755 --- a/f4pga/wrappers/sh/quicklogic/generate_constraints.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/generate_constraints.f4pga.sh @@ -36,14 +36,14 @@ else DEVICE_1=${DEVICE} fi -SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)} +SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_ENV_SHARE"} PINMAP_XML=`realpath ${SHARE_DIR_PATH}/arch/${DEVICE_1}_${DEVICE_1}/${PINMAPXML}` PROJECT=$(basename -- "$EBLIF") IOPLACE_FILE="${PROJECT%.*}_io.place" -python3 $(realpath $(f4pga-env bin)/python/create_ioplace.py) \ +python3 $(realpath "$F4PGA_ENV_BIN"/python/create_ioplace.py) \ --pcf $PCF \ --blif $EBLIF \ --pinmap_xml $PINMAP_XML \ diff --git a/f4pga/wrappers/sh/quicklogic/generate_libfile.f4pga.sh b/f4pga/wrappers/sh/quicklogic/generate_libfile.f4pga.sh index 192531a..a8a83e3 100755 --- a/f4pga/wrappers/sh/quicklogic/generate_libfile.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/generate_libfile.f4pga.sh @@ -31,10 +31,10 @@ else DEVICE_1=${DEVICE} fi -ARCH_DIR=$(f4pga-env share)/arch/${DEVICE_1}_${DEVICE_1} +ARCH_DIR="$F4PGA_ENV_SHARE"/arch/${DEVICE_1}_${DEVICE_1} PINMAP_XML=${ARCH_DIR}/${PINMAPXML} -python3 $(f4pga-env bin)/python/create_lib.py \ +python3 "$F4PGA_ENV_BIN"/python/create_lib.py \ -n ${DEV}_0P72_SSM40 \ -m fpga_top \ -c $PART \ diff --git a/f4pga/wrappers/sh/quicklogic/pack.f4pga.sh b/f4pga/wrappers/sh/quicklogic/pack.f4pga.sh index 67b7602..a880122 100755 --- a/f4pga/wrappers/sh/quicklogic/pack.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/pack.f4pga.sh @@ -19,7 +19,7 @@ set -e if [ -z $VPRPATH ]; then - export VPRPATH=$(f4pga-env bin) + export VPRPATH="$F4PGA_ENV_BIN" export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH} fi diff --git a/f4pga/wrappers/sh/quicklogic/place.f4pga.sh b/f4pga/wrappers/sh/quicklogic/place.f4pga.sh index f646837..9b8d8dd 100755 --- a/f4pga/wrappers/sh/quicklogic/place.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/place.f4pga.sh @@ -19,7 +19,7 @@ set -e if [ -z $VPRPATH ]; then - export VPRPATH=$(f4pga-env bin) + export VPRPATH="$F4PGA_ENV_BIN" export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH} fi diff --git a/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh b/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh index b4f8003..26328ae 100755 --- a/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh @@ -20,7 +20,7 @@ set -e BUILDDIR=build -source $(f4pga-env bin)/vpr_common +source "$F4PGA_ENV_BIN"/vpr_common VERSION="v2.0.1" @@ -341,7 +341,7 @@ else PCF_MAKE="\${current_dir}/build/${TOP}_dummy.pcf" fi -PROCESS_SDC=$(realpath $(f4pga-env bin)/python/process_sdc_constraints.py) +PROCESS_SDC=$(realpath "$F4PGA_ENV_BIN"/python/process_sdc_constraints.py) if ! [ -z "$SDC" ]; then if ! [ -f "$SOURCE"/$SDC ];then echo "The sdc file: $SDC is missing at: $SOURCE" diff --git a/f4pga/wrappers/sh/quicklogic/repack.f4pga.sh b/f4pga/wrappers/sh/quicklogic/repack.f4pga.sh index e8d1a71..60f145d 100755 --- a/f4pga/wrappers/sh/quicklogic/repack.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/repack.f4pga.sh @@ -19,7 +19,7 @@ set -e if [ -z $VPRPATH ]; then - export VPRPATH=$(f4pga-env bin) + export VPRPATH="$F4PGA_ENV_BIN" export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH} fi @@ -31,7 +31,7 @@ DESIGN=${EBLIF/.eblif/} [ ! -z "${JSON}" ] && JSON_ARGS="--json-constraints ${JSON}" || JSON_ARGS= [ ! -z "${PCF_PATH}" ] && PCF_ARGS="--pcf-constraints ${PCF_PATH}" || PCF_ARGS= -python3 $(f4pga-env bin)/python/repacker/repack.py \ +python3 "$F4PGA_ENV_BIN"/python/repacker/repack.py \ --vpr-arch ${ARCH_DEF} \ --repacking-rules ${ARCH_DIR}/${DEVICE_1}.repacking_rules.json \ $JSON_ARGS \ diff --git a/f4pga/wrappers/sh/quicklogic/route.f4pga.sh b/f4pga/wrappers/sh/quicklogic/route.f4pga.sh index 37b55a8..571ea61 100755 --- a/f4pga/wrappers/sh/quicklogic/route.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/route.f4pga.sh @@ -19,7 +19,7 @@ set -e if [ -z $VPRPATH ]; then - export VPRPATH=$(f4pga-env bin) + export VPRPATH="$F4PGA_ENV_BIN" export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH} fi diff --git a/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh b/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh index 7e832fc..9c0b98f 100755 --- a/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh @@ -18,8 +18,8 @@ set -e -export SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)} -VPRPATH=${VPRPATH:=$(f4pga-env bin)} +export SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_ENV_SHARE"} +VPRPATH=${VPRPATH:="$F4PGA_ENV_BIN"} SPLIT_INOUTS=`realpath ${VPRPATH}/python/split_inouts.py` CONVERT_OPTS=`realpath ${VPRPATH}/python/convert_compile_opts.py` diff --git a/f4pga/wrappers/sh/quicklogic/write_fasm.f4pga.sh b/f4pga/wrappers/sh/quicklogic/write_fasm.f4pga.sh index 804cbec..00e98e2 100755 --- a/f4pga/wrappers/sh/quicklogic/write_fasm.f4pga.sh +++ b/f4pga/wrappers/sh/quicklogic/write_fasm.f4pga.sh @@ -19,7 +19,7 @@ set -e if [ -z $VPRPATH ]; then - export VPRPATH=$(f4pga-env bin) + export VPRPATH="$F4PGA_ENV_BIN" export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH} fi diff --git a/f4pga/wrappers/sh/xc7/generate_constraints.f4pga.sh b/f4pga/wrappers/sh/xc7/generate_constraints.f4pga.sh index 8307490..69c9725 100755 --- a/f4pga/wrappers/sh/xc7/generate_constraints.f4pga.sh +++ b/f4pga/wrappers/sh/xc7/generate_constraints.f4pga.sh @@ -29,7 +29,7 @@ if [ ! -z $PCF ]; then PCF_OPTS="--pcf $PCF" fi -SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)} +SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_ENV_SHARE"} PROJECT=$(basename -- "$EBLIF") IOPLACE_FILE="${PROJECT%.*}.ioplace" diff --git a/f4pga/wrappers/sh/xc7/synth.f4pga.sh b/f4pga/wrappers/sh/xc7/synth.f4pga.sh index ec7c0f8..cb28ef2 100755 --- a/f4pga/wrappers/sh/xc7/synth.f4pga.sh +++ b/f4pga/wrappers/sh/xc7/synth.f4pga.sh @@ -18,7 +18,7 @@ set -e -export SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)} +export SHARE_DIR_PATH="$F4PGA_ENV_SHARE" export TECHMAP_PATH=${SHARE_DIR_PATH}/techmaps/xc7_vpr/techmap export UTILS_PATH=${SHARE_DIR_PATH}/scripts diff --git a/f4pga/wrappers/sh/xc7/vpr_common.f4pga.sh b/f4pga/wrappers/sh/xc7/vpr_common.f4pga.sh index 8bd109e..416caf0 100755 --- a/f4pga/wrappers/sh/xc7/vpr_common.f4pga.sh +++ b/f4pga/wrappers/sh/xc7/vpr_common.f4pga.sh @@ -16,7 +16,7 @@ # # SPDX-License-Identifier: Apache-2.0 -SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)} +SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_ENV_SHARE"} if [ -z $VPR_OPTIONS ]; then echo "Using default VPR options."