litedram/examples/arty.yml

57 lines
2.0 KiB
YAML
Raw Permalink Normal View History

#
# This file is part of LiteDRAM.
#
# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
2019-08-28 01:08:10 -04:00
{
# General ------------------------------------------------------------------
"speedgrade": -1, # FPGA speedgrade
"cpu": "vexriscv", # CPU type (ex vexriscv, serv, None)
"memtype": "DDR3", # DRAM type
"uart": "rs232", # Type of UART interface (rs232, fifo)
# PHY ----------------------------------------------------------------------
2019-08-28 01:08:10 -04:00
"cmd_latency": 0, # Command additional latency
"sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM
"sdram_module_nb": 2, # Number of byte groups
"sdram_rank_nb": 1, # Number of ranks
"sdram_phy": "A7DDRPHY", # Type of FPGA PHY
# Electrical ---------------------------------------------------------------
"rtt_nom": "60ohm", # Nominal termination
"rtt_wr": "60ohm", # Write termination
"ron": "34ohm", # Output driver impedance
# Frequency ----------------------------------------------------------------
"input_clk_freq": 100e6, # Input clock frequency
"sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
# Core ---------------------------------------------------------------------
"cmd_buffer_depth": 16, # Depth of the command buffer
# User Ports ---------------------------------------------------------------
"user_ports": {
"axi_0" : {
"type": "axi",
"id_width": 32,
},
"wishbone_0" : {
"type": "wishbone",
"block_until_ready": True,
},
"avalon_0" : {
"type": "avalon",
},
"native_0" : {
"type": "native",
},
"fifo_0" : {
"type": "fifo",
"base": 0x00000000,
"depth": 0x01000000,
},
},
}